#include "inc/hw/dmcu.h"
#include "dml/display_mode_lib.h"
-#define DC_VER "3.2.35"
+#define DC_VER "3.2.41"
#define MAX_SURFACES 3
#define MAX_PLANES 6
uint32_t argb8888 : 1;
uint32_t nv12 : 1;
uint32_t fp16 : 1;
+ uint32_t p010 : 1;
+ uint32_t ayuv : 1;
} pixel_format_support;
// max upscaling factor x1000
// upscaling factors are always >= 1
bool force_dp_tps4_for_cp2520;
bool disable_dp_clk_share;
bool psp_setup_panel_mode;
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ bool hw_3d_lut;
+#endif
struct dc_plane_cap planes[MAX_PLANES];
};
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+struct dc_bug_wa {
+ bool no_connect_phy_config;
+ bool dedcn20_305_wa;
+};
+#endif
+
struct dc_dcc_surface_param {
struct dc_size surface_size;
enum surface_pixel_format format;
bool allow_seamless_boot_optimization;
bool power_down_display_on_boot;
bool edp_not_connected;
+ bool forced_clocks;
+
};
enum visual_confirm {
struct dc_clocks {
int dispclk_khz;
int max_supported_dppclk_khz;
+ int max_supported_dispclk_khz;
int dppclk_khz;
+ int bw_dppclk_khz; /*a copy of dppclk_khz*/
+ int bw_dispclk_khz;
int dcfclk_khz;
int socclk_khz;
int dcfclk_deep_sleep_khz;
bool disable_dfs_bypass;
bool disable_dpp_power_gate;
bool disable_hubp_power_gate;
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ bool disable_dsc_power_gate;
+#endif
bool disable_pplib_wm_range;
enum wm_report_mode pplib_wm_report_mode;
unsigned int min_disp_clk_khz;
+ unsigned int min_dpp_clk_khz;
int sr_exit_time_dpm0_ns;
int sr_enter_plus_exit_time_dpm0_ns;
int sr_exit_time_ns;
int sr_enter_plus_exit_time_ns;
int urgent_latency_ns;
+ uint32_t underflow_assert_delay_us;
int percent_of_ideal_drambw;
int dram_clock_change_latency_ns;
bool optimized_watermark;
unsigned int force_fclk_khz;
bool disable_tri_buf;
struct dc_bw_validation_profile bw_val_profile;
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ bool disable_fec;
+#endif
+ /* This forces a hard min on the DCFCLK requested to SMU/PP
+ * watermarks are not affected.
+ */
+ unsigned int force_min_dcfclk_mhz;
+ bool disable_timing_sync;
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ bool cm_in_bypass;
+#endif
+ int force_clock_mode;/*every mode change.*/
};
struct dc_debug_data {
uint32_t auxErrorCount;
};
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+struct dc_phy_addr_space_config {
+ struct {
+ uint64_t start_addr;
+ uint64_t end_addr;
+ uint64_t fb_top;
+ uint64_t fb_offset;
+ uint64_t fb_base;
+ uint64_t agp_top;
+ uint64_t agp_bot;
+ uint64_t agp_base;
+ } system_aperture;
+
+ struct {
+ uint64_t page_table_start_addr;
+ uint64_t page_table_end_addr;
+ uint64_t page_table_base_addr;
+ } gart_config;
+
+ bool valid;
+};
+
+struct dc_virtual_addr_space_config {
+ uint64_t page_table_base_addr;
+ uint64_t page_table_start_addr;
+ uint64_t page_table_end_addr;
+ uint32_t page_table_block_size_in_bytes;
+ uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid
+};
+#endif
+
struct dc_bounding_box_overrides {
int sr_exit_time_ns;
int sr_enter_plus_exit_time_ns;
int urgent_latency_ns;
int percent_of_ideal_drambw;
int dram_clock_change_latency_ns;
+ /* This forces a hard min on the DCFCLK we use
+ * for DML. Unlike the debug option for forcing
+ * DCFCLK, this override affects watermark calculations
+ */
int min_dcfclk_mhz;
};
struct dc_state;
struct resource_pool;
struct dce_hwseq;
+struct gpu_info_soc_bounding_box_v1_0;
struct dc {
struct dc_versions versions;
struct dc_caps caps;
struct dc_config config;
struct dc_debug_options debug;
struct dc_bounding_box_overrides bb_overrides;
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct dc_bug_wa work_arounds;
+#endif
struct dc_context *ctx;
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ struct dc_phy_addr_space_config vm_pa_config;
+#endif
uint8_t link_count;
struct dc_link *links[MAX_PIPES * 2];
struct dc_debug_data debug_data;
const char *build_id;
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ struct vm_helper *vm_helper;
+ const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
+#endif
};
enum frame_buffer_mode {
struct dc_config flags;
uint32_t log_mask;
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ /**
+ * gpu_info FW provided soc bounding box struct or 0 if not
+ * available in FW
+ */
+ const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
+#endif
};
struct dc_callback_init {
};
struct dc *dc_create(const struct dc_init_data *init_params);
+int dc_get_vmid_use_vector(struct dc *dc);
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
+/* Returns the number of vmids supported */
+int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
+#endif
void dc_init_callbacks(struct dc *dc,
const struct dc_callback_init *init_params);
void dc_destroy(struct dc **dc);
};
};
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+
+union dc_3dlut_state {
+ struct {
+ uint32_t initialized:1; /*if 3dlut is went through color module for initialization */
+ uint32_t rmu_idx_valid:1; /*if mux settings are valid*/
+ uint32_t rmu_mux_num:3; /*index of mux to use*/
+ uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/
+ uint32_t mpc_rmu1_mux:4;
+ uint32_t mpc_rmu2_mux:4;
+ uint32_t reserved:15;
+ } bits;
+ uint32_t raw;
+};
+
+
+struct dc_3dlut {
+ struct kref refcount;
+ struct tetrahedral_params lut_3d;
+ uint32_t hdr_multiplier;
+ bool initialized; /*remove after diag fix*/
+ union dc_3dlut_state state;
+ struct dc_context *ctx;
+};
+#endif
/*
* This structure is filled in by dc_surface_get_status and contains
* the last requested address and the currently active address so the called
struct dc_plane_state {
struct dc_plane_address address;
struct dc_plane_flip_time time;
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ bool triplebuffer_flips;
+#endif
struct scaling_taps scaling_quality;
struct rect src_rect;
struct rect dst_rect;
struct rect clip_rect;
- union plane_size plane_size;
+ struct plane_size plane_size;
union dc_tiling_info tiling_info;
struct dc_plane_dcc_param dcc;
enum dc_color_space color_space;
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ struct dc_3dlut *lut3d_func;
+ struct dc_transfer_func *in_shaper_func;
+ struct dc_transfer_func *blend_tf;
+#endif
+
enum surface_pixel_format format;
enum dc_rotation_angle rotation;
enum plane_stereo_format stereo_format;
};
struct dc_plane_info {
- union plane_size plane_size;
+ struct plane_size plane_size;
union dc_tiling_info tiling_info;
struct dc_plane_dcc_param dcc;
enum surface_pixel_format format;
const struct dc_csc_transform *input_csc_color_matrix;
const struct fixed31_32 *coeff_reduction_factor;
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ const struct dc_transfer_func *func_shaper;
+ const struct dc_3dlut *lut3d_func;
+ const struct dc_transfer_func *blend_tf;
+#endif
};
/*
void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
struct dc_transfer_func *dc_create_transfer_func(void);
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+struct dc_3dlut *dc_create_3dlut_func(void);
+void dc_3dlut_func_release(struct dc_3dlut *lut);
+void dc_3dlut_func_retain(struct dc_3dlut *lut);
+#endif
/*
* This structure holds a surface address. There could be multiple addresses
* in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such
void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
+bool dc_set_generic_gpio_for_stereo(bool enable,
+ struct gpio_service *gpio_service);
+
/*
* fast_validate: we return after determining if we can support the new state,
* but before we populate the programming info
bool panel_mode_edp;
bool dpcd_display_control_capable;
bool ext_receiver_cap_field_present;
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ union dpcd_fec_capability fec_cap;
+ struct dpcd_dsc_capabilities dsc_caps;
+#endif
};
#include "dc_link.h"
};
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+struct dc_sink_dsc_caps {
+ // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),
+ // 'false' if they are sink's DSC caps
+ bool is_virtual_dpcd_dsc;
+ struct dsc_dec_dpcd_caps dsc_dec_caps;
+};
+#endif
/*
* The sink structure contains EDID and other display device properties
struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
bool converter_disable_audio;
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ struct dc_sink_dsc_caps sink_dsc_caps;
+#endif
+
/* private to DC core */
struct dc_link *link;
struct dc_context *ctx;
bool dc_is_dmcu_initialized(struct dc *dc);
+enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
+void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
+#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
+/*******************************************************************************
+ * DSC Interfaces
+ ******************************************************************************/
+#include "dc_dsc.h"
+#endif
#endif /* DC_INTERFACE_H_ */
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