drm/amdgpu: add new device to use atpx quirk

[sfrench/cifs-2.6.git] / drivers / gpu / drm / amd / amdgpu / nbio_v6_1.c

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index 9a3546f8b42beaef61bb0cb25fe99bfc00b8a503..d4da663d5eb0c7aed8826c72302008b757cd8d68 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -33,7 +33,7 @@
 #define smnPCIE_CNTL2                                                                                   0x11180070
 #define smnPCIE_CONFIG_CNTL                                                                             0x11180044
 
-u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
+static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
 {
         u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
 
@@ -43,19 +43,7 @@ u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
        return tmp;
 }
 
-u32 nbio_v6_1_get_atombios_scratch_regs(struct amdgpu_device *adev,
-                                       uint32_t idx)
-{
-       return RREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx);
-}
-
-void nbio_v6_1_set_atombios_scratch_regs(struct amdgpu_device *adev,
-                                        uint32_t idx, uint32_t val)
-{
-       WREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx, val);
-}
-
-void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable)
+static void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable)
 {
        if (enable)
                WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
@@ -65,17 +53,17 @@ void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable)
                WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
 }
 
-void nbio_v6_1_hdp_flush(struct amdgpu_device *adev)
+static void nbio_v6_1_hdp_flush(struct amdgpu_device *adev)
 {
        WREG32_SOC15_NO_KIQ(NBIO, 0, mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL, 0);
 }
 
-u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)
+static u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)
 {
        return RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE);
 }
 
-void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
+static void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
                                  bool use_doorbell, int doorbell_index)
 {
        u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
@@ -93,14 +81,14 @@ void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
 
 }
 
-void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev,
-                                       bool enable)
+static void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev,
+                                              bool enable)
 {
        WREG32_FIELD15(NBIO, 0, RCC_PF_0_0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
 }
 
-void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
-                                       bool enable)
+static void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
+                                                       bool enable)
 {
        u32 tmp = 0;
 
@@ -119,8 +107,8 @@ void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
 }
 
 
-void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev,
-                               bool use_doorbell, int doorbell_index)
+static void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev,
+                                       bool use_doorbell, int doorbell_index)
 {
        u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
 
@@ -133,7 +121,7 @@ void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev,
        WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
 }
 
-void nbio_v6_1_ih_control(struct amdgpu_device *adev)
+static void nbio_v6_1_ih_control(struct amdgpu_device *adev)
 {
        u32 interrupt_cntl;
 
@@ -149,8 +137,8 @@ void nbio_v6_1_ih_control(struct amdgpu_device *adev)
        WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
 }
 
-void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev,
-                                               bool enable)
+static void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev,
+                                                      bool enable)
 {
        uint32_t def, data;
 
@@ -177,8 +165,8 @@ void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev,
                WREG32_PCIE(smnCPM_CONTROL, data);
 }
 
-void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev,
-                                              bool enable)
+static void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev,
+                                                     bool enable)
 {
        uint32_t def, data;
 
@@ -197,7 +185,8 @@ void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev,
                WREG32_PCIE(smnPCIE_CNTL2, data);
 }
 
-void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, u32 *flags)
+static void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev,
+                                           u32 *flags)
 {
        int data;
 
@@ -212,27 +201,27 @@ void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, u32 *flags)
                *flags |= AMD_CG_SUPPORT_BIF_LS;
 }
 
-static u32 get_hdp_flush_req_offset(struct amdgpu_device *adev)
+static u32 nbio_v6_1_get_hdp_flush_req_offset(struct amdgpu_device *adev)
 {
        return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
 }
 
-static u32 get_hdp_flush_done_offset(struct amdgpu_device *adev)
+static u32 nbio_v6_1_get_hdp_flush_done_offset(struct amdgpu_device *adev)
 {
        return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
 }
 
-static u32 get_pcie_index_offset(struct amdgpu_device *adev)
+static u32 nbio_v6_1_get_pcie_index_offset(struct amdgpu_device *adev)
 {
        return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX);
 }
 
-static u32 get_pcie_data_offset(struct amdgpu_device *adev)
+static u32 nbio_v6_1_get_pcie_data_offset(struct amdgpu_device *adev)
 {
        return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA);
 }
 
-const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {
+static const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {
        .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
        .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
        .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
@@ -247,15 +236,7 @@ const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {
        .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK
 };
 
-const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
-       .get_hdp_flush_req_offset = get_hdp_flush_req_offset,
-       .get_hdp_flush_done_offset = get_hdp_flush_done_offset,
-       .get_pcie_index_offset = get_pcie_index_offset,
-       .get_pcie_data_offset = get_pcie_data_offset,
-};
-
-
-void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev)
+static void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev)
 {
        uint32_t reg;
 
@@ -272,7 +253,7 @@ void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev)
        }
 }
 
-void nbio_v6_1_init_registers(struct amdgpu_device *adev)
+static void nbio_v6_1_init_registers(struct amdgpu_device *adev)
 {
        uint32_t def, data;
 
@@ -283,3 +264,25 @@ void nbio_v6_1_init_registers(struct amdgpu_device *adev)
        if (def != data)
                WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);
 }
+
+const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
+       .hdp_flush_reg = &nbio_v6_1_hdp_flush_reg,
+       .get_hdp_flush_req_offset = nbio_v6_1_get_hdp_flush_req_offset,
+       .get_hdp_flush_done_offset = nbio_v6_1_get_hdp_flush_done_offset,
+       .get_pcie_index_offset = nbio_v6_1_get_pcie_index_offset,
+       .get_pcie_data_offset = nbio_v6_1_get_pcie_data_offset,
+       .get_rev_id = nbio_v6_1_get_rev_id,
+       .mc_access_enable = nbio_v6_1_mc_access_enable,
+       .hdp_flush = nbio_v6_1_hdp_flush,
+       .get_memsize = nbio_v6_1_get_memsize,
+       .sdma_doorbell_range = nbio_v6_1_sdma_doorbell_range,
+       .enable_doorbell_aperture = nbio_v6_1_enable_doorbell_aperture,
+       .enable_doorbell_selfring_aperture = nbio_v6_1_enable_doorbell_selfring_aperture,
+       .ih_doorbell_range = nbio_v6_1_ih_doorbell_range,
+       .update_medium_grain_clock_gating = nbio_v6_1_update_medium_grain_clock_gating,
+       .update_medium_grain_light_sleep = nbio_v6_1_update_medium_grain_light_sleep,
+       .get_clockgating_state = nbio_v6_1_get_clockgating_state,
+       .ih_control = nbio_v6_1_ih_control,
+       .init_registers = nbio_v6_1_init_registers,
+       .detect_hw_virt = nbio_v6_1_detect_hw_virt,
+};