amd64_edac: Fix type usage in NB IDs and memory ranges

[sfrench/cifs-2.6.git] / drivers / edac / amd64_edac.h

diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index e864f407806c2bef8d0240e01df639fe51c9d909..35637d83f2351270f8b73a0358f8fe43b0bc6825 100644 (file)
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -292,12 +292,6 @@
 /* MSRs */
 #define MSR_MCGCTL_NBE                 BIT(4)
 
-/* AMD sets the first MC device at device ID 0x18. */
-static inline u8 get_node_id(struct pci_dev *pdev)
-{
-       return PCI_SLOT(pdev->devfn) - 0x18;
-}
-
 enum amd_families {
        K8_CPUS = 0,
        F10_CPUS,
@@ -340,7 +334,7 @@ struct amd64_pvt {
        /* pci_device handles which we utilize */
        struct pci_dev *F1, *F2, *F3;
 
-       unsigned mc_node_id;    /* MC index of this MC node */
+       u16 mc_node_id;         /* MC index of this MC node */
        int ext_model;          /* extended model value of this node */
        int channel_count;
 
@@ -393,7 +387,7 @@ struct err_info {
        u32 offset;
 };
 
-static inline u64 get_dram_base(struct amd64_pvt *pvt, unsigned i)
+static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
 {
        u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
 
@@ -403,7 +397,7 @@ static inline u64 get_dram_base(struct amd64_pvt *pvt, unsigned i)
        return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;
 }
 
-static inline u64 get_dram_limit(struct amd64_pvt *pvt, unsigned i)
+static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)
 {
        u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;