Merge branch 'for-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/percpu
[sfrench/cifs-2.6.git] / drivers / clk / tegra / clk-tegra30.c
index 5bbacd01094f3770fcd3161e733070ea3412b97c..4b9d8bd3d0bfdd8e93f0436ea3bd0f016d5091fb 100644 (file)
@@ -177,6 +177,7 @@ static unsigned long input_freq;
 
 static DEFINE_SPINLOCK(cml_lock);
 static DEFINE_SPINLOCK(pll_d_lock);
+static DEFINE_SPINLOCK(emc_lock);
 
 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset,  \
                            _clk_num, _gate_flags, _clk_id)     \
@@ -1157,11 +1158,15 @@ static void __init tegra30_periph_clk_init(void)
                               ARRAY_SIZE(mux_pllmcp_clkm),
                               CLK_SET_RATE_NO_REPARENT,
                               clk_base + CLK_SOURCE_EMC,
-                              30, 2, 0, NULL);
+                              30, 2, 0, &emc_lock);
        clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
                                    57, periph_clk_enb_refcnt);
        clks[TEGRA30_CLK_EMC] = clk;
 
+       clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
+                                   &emc_lock);
+       clks[TEGRA30_CLK_MC] = clk;
+
        /* cml0 */
        clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
                                0, 0, &cml_lock);