Merge tag 'trace-v6.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux...

[sfrench/cifs-2.6.git] / drivers / clk / qcom / gcc-sc8180x.c

diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c
index ae21473815596d55bfabd2e5532350274b7cc150..5261bfc92b3dc3d6c5c2b09d7b7e6a4b6d500d50 100644 (file)
--- a/drivers/clk/qcom/gcc-sc8180x.c
+++ b/drivers/clk/qcom/gcc-sc8180x.c
@@ -3347,6 +3347,19 @@ static struct clk_branch gcc_ufs_card_2_unipro_core_clk = {
        },
 };
 
+static struct clk_branch gcc_ufs_card_clkref_en = {
+       .halt_reg = 0x8c004,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x8c004,
+               .enable_mask = BIT(0),
+               .hw.init = &(const struct clk_init_data) {
+                       .name = "gcc_ufs_card_clkref_en",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
 static struct clk_branch gcc_ufs_card_ahb_clk = {
        .halt_reg = 0x75014,
        .halt_check = BRANCH_HALT,
@@ -3561,6 +3574,19 @@ static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {
        },
 };
 
+static struct clk_branch gcc_ufs_mem_clkref_en = {
+       .halt_reg = 0x8c000,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x8c000,
+               .enable_mask = BIT(0),
+               .hw.init = &(const struct clk_init_data) {
+                       .name = "gcc_ufs_mem_clkref_en",
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
 static struct clk_branch gcc_ufs_phy_ahb_clk = {
        .halt_reg = 0x77014,
        .halt_check = BRANCH_HALT,
@@ -4413,6 +4439,7 @@ static struct clk_regmap *gcc_sc8180x_clocks[] = {
        [GCC_UFS_CARD_2_TX_SYMBOL_0_CLK] = &gcc_ufs_card_2_tx_symbol_0_clk.clkr,
        [GCC_UFS_CARD_2_UNIPRO_CORE_CLK] = &gcc_ufs_card_2_unipro_core_clk.clkr,
        [GCC_UFS_CARD_2_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_2_unipro_core_clk_src.clkr,
+       [GCC_UFS_CARD_CLKREF_EN] = &gcc_ufs_card_clkref_en.clkr,
        [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
        [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
        [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
@@ -4429,6 +4456,7 @@ static struct clk_regmap *gcc_sc8180x_clocks[] = {
        [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
        [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_card_unipro_core_clk_src.clkr,
        [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr,
+       [GCC_UFS_MEM_CLKREF_EN] = &gcc_ufs_mem_clkref_en.clkr,
        [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
        [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
        [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
@@ -4528,9 +4556,9 @@ static const struct qcom_reset_map gcc_sc8180x_resets[] = {
        [GCC_USB30_PRIM_BCR] = { 0xf000 },
        [GCC_USB30_SEC_BCR] = { 0x10000 },
        [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
-       [GCC_VIDEO_AXIC_CLK_BCR] = { 0xb02c, 2 },
-       [GCC_VIDEO_AXI0_CLK_BCR] = { 0xb024, 2 },
-       [GCC_VIDEO_AXI1_CLK_BCR] = { 0xb028, 2 },
+       [GCC_VIDEO_AXIC_CLK_BCR] = { .reg = 0xb02c, .bit = 2, .udelay = 150 },
+       [GCC_VIDEO_AXI0_CLK_BCR] = { .reg = 0xb024, .bit = 2, .udelay = 150 },
+       [GCC_VIDEO_AXI1_CLK_BCR] = { .reg = 0xb028, .bit = 2, .udelay = 150 },
 };
 
 static struct gdsc *gcc_sc8180x_gdscs[] = {
@@ -4579,23 +4607,17 @@ static int gcc_sc8180x_probe(struct platform_device *pdev)
        if (IS_ERR(regmap))
                return PTR_ERR(regmap);
 
-       /*
-        * Enable the following always-on clocks:
-        * GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, GCC_DISP_AHB_CLK,
-        * GCC_VIDEO_XO_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_XO_CLK,
-        * GCC_CPUSS_GNOC_CLK, GCC_CPUSS_DVM_BUS_CLK, GCC_NPU_CFG_AHB_CLK and
-        * GCC_GPU_CFG_AHB_CLK
-        */
-       regmap_update_bits(regmap, 0xb004, BIT(0), BIT(0));
-       regmap_update_bits(regmap, 0xb008, BIT(0), BIT(0));
-       regmap_update_bits(regmap, 0xb00c, BIT(0), BIT(0));
-       regmap_update_bits(regmap, 0xb040, BIT(0), BIT(0));
-       regmap_update_bits(regmap, 0xb044, BIT(0), BIT(0));
-       regmap_update_bits(regmap, 0xb048, BIT(0), BIT(0));
-       regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0));
-       regmap_update_bits(regmap, 0x48190, BIT(0), BIT(0));
-       regmap_update_bits(regmap, 0x4d004, BIT(0), BIT(0));
-       regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
+       /* Keep some clocks always-on */
+       qcom_branch_set_clk_en(regmap, 0xb004); /* GCC_VIDEO_AHB_CLK */
+       qcom_branch_set_clk_en(regmap, 0xb008); /* GCC_CAMERA_AHB_CLK */
+       qcom_branch_set_clk_en(regmap, 0xb00c); /* GCC_DISP_AHB_CLK */
+       qcom_branch_set_clk_en(regmap, 0xb040); /* GCC_VIDEO_XO_CLK */
+       qcom_branch_set_clk_en(regmap, 0xb044); /* GCC_CAMERA_XO_CLK */
+       qcom_branch_set_clk_en(regmap, 0xb048); /* GCC_DISP_XO_CLK */
+       qcom_branch_set_clk_en(regmap, 0x48004); /* GCC_CPUSS_GNOC_CLK */
+       qcom_branch_set_clk_en(regmap, 0x48190); /* GCC_CPUSS_DVM_BUS_CLK */
+       qcom_branch_set_clk_en(regmap, 0x4d004); /* GCC_NPU_CFG_AHB_CLK */
+       qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */
 
        /* Disable the GPLL0 active input to NPU and GPU via MISC registers */
        regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);