Merge branch 'for-4.14-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj...

[sfrench/cifs-2.6.git] / drivers / clk / clk-qoriq.c

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index f3931e38fac0fb58a9bb6262e0fe7d9da33a6269..b0ea753b8709dafa7f4fdc886b0765de1ea1c248 100644 (file)
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -12,6 +12,7 @@
 
 #include <linux/clk.h>
 #include <linux/clk-provider.h>
+#include <linux/clkdev.h>
 #include <linux/fsl/guts.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
@@ -536,6 +537,17 @@ static const struct clockgen_chipinfo chipinfo[] = {
                .pll_mask = 0x07,
                .flags = CG_PLL_8BIT,
        },
+       {
+               .compat = "fsl,ls1088a-clockgen",
+               .cmux_groups = {
+                       &clockgen2_cmux_cga12
+               },
+               .cmux_to_group = {
+                       0, 0, -1
+               },
+               .pll_mask = 0x07,
+               .flags = CG_VER3 | CG_LITTLE_ENDIAN,
+       },
        {
                .compat = "fsl,ls1012a-clockgen",
                .cmux_groups = {
@@ -1113,6 +1125,7 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
 
        for (i = 0; i < ARRAY_SIZE(pll->div); i++) {
                struct clk *clk;
+               int ret;
 
                snprintf(pll->div[i].name, sizeof(pll->div[i].name),
                         "cg-pll%d-div%d", idx, i + 1);
@@ -1126,6 +1139,11 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
                }
 
                pll->div[i].clk = clk;
+               ret = clk_register_clkdev(clk, pll->div[i].name, NULL);
+               if (ret != 0)
+                       pr_err("%s: %s: register to lookup table failed %ld\n",
+                              __func__, pll->div[i].name, PTR_ERR(clk));
+
        }
 }
 
@@ -1348,8 +1366,7 @@ static void __init clockgen_init(struct device_node *np)
        }
 
        if (i == ARRAY_SIZE(chipinfo)) {
-               pr_err("%s: unknown clockgen node %s\n", __func__,
-                      np->full_name);
+               pr_err("%s: unknown clockgen node %pOF\n", __func__, np);
                goto err;
        }
        clockgen.info = chipinfo[i];
@@ -1362,8 +1379,8 @@ static void __init clockgen_init(struct device_node *np)
                if (guts) {
                        clockgen.guts = of_iomap(guts, 0);
                        if (!clockgen.guts) {
-                               pr_err("%s: Couldn't map %s regs\n", __func__,
-                                      guts->full_name);
+                               pr_err("%s: Couldn't map %pOF regs\n", __func__,
+                                      guts);
                        }
                }
 
@@ -1398,6 +1415,7 @@ CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
 
 /* Legacy nodes */