*/
n6 = num_clocks_min(t6min, fsclk);
if (mode >= 0 && mode <= 4 && n6 >= 1) {
- pr_debug("set piomode: mode=%d, fsclk=%ud\n", mode, fsclk);
+ dev_dbg(adev->link->ap->dev, "set piomode: mode=%d, fsclk=%ud\n", mode, fsclk);
/* calculate the timing values for register transfers. */
while (mode > 0 && pio_fsclk[mode] > fsclk)
mode--;
mode = adev->dma_mode - XFER_UDMA_0;
if (mode >= 0 && mode <= 5) {
- pr_debug("set udmamode: mode=%d\n", mode);
+ dev_dbg(adev->link->ap->dev, "set udmamode: mode=%d\n", mode);
/* the most restrictive timing value is t6 and tc,
* the DIOW - data hold. If one SCLK pulse is longer
* than this minimum value then register
mode = adev->dma_mode - XFER_MW_DMA_0;
if (mode >= 0 && mode <= 2) {
- pr_debug("set mdmamode: mode=%d\n", mode);
+ dev_dbg(adev->link->ap->dev, "set mdmamode: mode=%d\n", mode);
/* the most restrictive timing value is tf, the DMACK to
* read data released. If one SCLK pulse is longer than
* this maximum value then the MDMA mode
write_atapi_register(base, ATA_REG_LBAL, tf->hob_lbal);
write_atapi_register(base, ATA_REG_LBAM, tf->hob_lbam);
write_atapi_register(base, ATA_REG_LBAH, tf->hob_lbah);
- pr_debug("hob: feat 0x%X nsect 0x%X, lba 0x%X "
+ dev_dbg(ap->dev, "hob: feat 0x%X nsect 0x%X, lba 0x%X "
"0x%X 0x%X\n",
tf->hob_feature,
tf->hob_nsect,
write_atapi_register(base, ATA_REG_LBAL, tf->lbal);
write_atapi_register(base, ATA_REG_LBAM, tf->lbam);
write_atapi_register(base, ATA_REG_LBAH, tf->lbah);
- pr_debug("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
+ dev_dbg(ap->dev, "feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
tf->feature,
tf->nsect,
tf->lbal,
if (tf->flags & ATA_TFLAG_DEVICE) {
write_atapi_register(base, ATA_REG_DEVICE, tf->device);
- pr_debug("device 0x%X\n", tf->device);
+ dev_dbg(ap->dev, "device 0x%X\n", tf->device);
}
ata_wait_idle(ap);
const struct ata_taskfile *tf)
{
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- pr_debug("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
+ dev_dbg(ap->dev, "ata%u: cmd 0x%X\n", ap->print_id, tf->command);
write_atapi_register(base, ATA_REG_CMD, tf->command);
ata_pause(ap);
{
unsigned short config = WDSIZE_16;
struct scatterlist *sg;
+ unsigned int si;
- pr_debug("in atapi dma setup\n");
+ dev_dbg(qc->ap->dev, "in atapi dma setup\n");
/* Program the ATA_CTRL register with dir */
if (qc->tf.flags & ATA_TFLAG_WRITE) {
/* fill the ATAPI DMA controller */
set_dma_config(CH_ATAPI_TX, config);
set_dma_x_modify(CH_ATAPI_TX, 2);
- ata_for_each_sg(sg, qc) {
+ for_each_sg(qc->sg, sg, qc->n_elem, si) {
set_dma_start_addr(CH_ATAPI_TX, sg_dma_address(sg));
set_dma_x_count(CH_ATAPI_TX, sg_dma_len(sg) >> 1);
}
/* fill the ATAPI DMA controller */
set_dma_config(CH_ATAPI_RX, config);
set_dma_x_modify(CH_ATAPI_RX, 2);
- ata_for_each_sg(sg, qc) {
+ for_each_sg(qc->sg, sg, qc->n_elem, si) {
set_dma_start_addr(CH_ATAPI_RX, sg_dma_address(sg));
set_dma_x_count(CH_ATAPI_RX, sg_dma_len(sg) >> 1);
}
struct ata_port *ap = qc->ap;
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
struct scatterlist *sg;
+ unsigned int si;
- pr_debug("in atapi dma start\n");
+ dev_dbg(qc->ap->dev, "in atapi dma start\n");
if (!(ap->udma_mask || ap->mwdma_mask))
return;
* data cache is enabled. Otherwise, this loop
* is an empty loop and optimized out.
*/
- ata_for_each_sg(sg, qc) {
+ for_each_sg(qc->sg, sg, qc->n_elem, si) {
flush_dcache_range(sg_dma_address(sg),
sg_dma_address(sg) + sg_dma_len(sg));
}
enable_dma(CH_ATAPI_TX);
- pr_debug("enable udma write\n");
+ dev_dbg(qc->ap->dev, "enable udma write\n");
/* Send ATA DMA write command */
bfin_exec_command(ap, &qc->tf);
| XFER_DIR));
} else {
enable_dma(CH_ATAPI_RX);
- pr_debug("enable udma read\n");
+ dev_dbg(qc->ap->dev, "enable udma read\n");
/* Send ATA DMA read command */
bfin_exec_command(ap, &qc->tf);
ATAPI_SET_CONTROL(base, ATAPI_GET_CONTROL(base) | TFRCNT_RST);
/* Set transfer length to buffer len */
- ata_for_each_sg(sg, qc) {
+ for_each_sg(qc->sg, sg, qc->n_elem, si) {
ATAPI_SET_XFER_LEN(base, (sg_dma_len(sg) >> 1));
}
{
struct ata_port *ap = qc->ap;
struct scatterlist *sg;
+ unsigned int si;
- pr_debug("in atapi dma stop\n");
+ dev_dbg(qc->ap->dev, "in atapi dma stop\n");
if (!(ap->udma_mask || ap->mwdma_mask))
return;
* data cache is enabled. Otherwise, this loop
* is an empty loop and optimized out.
*/
- ata_for_each_sg(sg, qc) {
+ for_each_sg(qc->sg, sg, qc->n_elem, si) {
invalidate_dcache_range(
sg_dma_address(sg),
sg_dma_address(sg)
* Note: Original code is ata_std_softreset().
*/
-static int bfin_std_softreset(struct ata_port *ap, unsigned int *classes,
+static int bfin_std_softreset(struct ata_link *link, unsigned int *classes,
unsigned long deadline)
{
+ struct ata_port *ap = link->ap;
unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
unsigned int devmask = 0, err_mask;
u8 err;
- if (ata_port_offline(ap)) {
+ if (ata_link_offline(link)) {
classes[0] = ATA_DEV_NONE;
goto out;
}
}
/* determine by signature whether we have ATA or ATAPI devices */
- classes[0] = ata_dev_try_classify(ap, 0, &err);
+ classes[0] = ata_dev_try_classify(&ap->link.device[0],
+ devmask & (1 << 0), &err);
if (slave_possible && err != 0x81)
- classes[1] = ata_dev_try_classify(ap, 1, &err);
+ classes[1] = ata_dev_try_classify(&ap->link.device[1],
+ devmask & (1 << 1), &err);
out:
return 0;
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
unsigned short int_status = ATAPI_GET_INT_STATUS(base);
- if (ATAPI_GET_STATUS(base) & (MULTI_XFER_ON|ULTRA_XFER_ON)) {
- host_stat = ATA_DMA_ACTIVE;
- }
- if (int_status & (MULTI_DONE_INT|UDMAIN_DONE_INT|UDMAOUT_DONE_INT)) {
- host_stat = ATA_DMA_INTR;
- }
- if (int_status & (MULTI_TERM_INT|UDMAIN_TERM_INT|UDMAOUT_TERM_INT)) {
- host_stat = ATA_DMA_ERR;
- }
+ if (ATAPI_GET_STATUS(base) & (MULTI_XFER_ON|ULTRA_XFER_ON))
+ host_stat |= ATA_DMA_ACTIVE;
+ if (int_status & (MULTI_DONE_INT|UDMAIN_DONE_INT|UDMAOUT_DONE_INT|
+ ATAPI_DEV_INT))
+ host_stat |= ATA_DMA_INTR;
+ if (int_status & (MULTI_TERM_INT|UDMAIN_TERM_INT|UDMAOUT_TERM_INT))
+ host_stat |= ATA_DMA_ERR|ATA_DMA_INTR;
+
+ dev_dbg(ap->dev, "ATAPI: host_stat=0x%x\n", host_stat);
return host_stat;
}
* Note: Original code is ata_data_xfer().
*/
-static void bfin_data_xfer(struct ata_device *adev, unsigned char *buf,
- unsigned int buflen, int write_data)
+static unsigned int bfin_data_xfer(struct ata_device *dev, unsigned char *buf,
+ unsigned int buflen, int rw)
{
- struct ata_port *ap = adev->ap;
- unsigned int words = buflen >> 1;
- unsigned short *buf16 = (u16 *) buf;
+ struct ata_port *ap = dev->link->ap;
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
+ unsigned int words = buflen >> 1;
+ unsigned short *buf16 = (u16 *)buf;
/* Transfer multiple of 2 bytes */
- if (write_data) {
- write_atapi_data(base, words, buf16);
- } else {
+ if (rw == READ)
read_atapi_data(base, words, buf16);
- }
+ else
+ write_atapi_data(base, words, buf16);
/* Transfer trailing 1 byte, if any. */
if (unlikely(buflen & 0x01)) {
unsigned short align_buf[1] = { 0 };
unsigned char *trailing_buf = buf + buflen - 1;
- if (write_data) {
- memcpy(align_buf, trailing_buf, 1);
- write_atapi_data(base, 1, align_buf);
- } else {
+ if (rw == READ) {
read_atapi_data(base, 1, align_buf);
memcpy(trailing_buf, align_buf, 1);
+ } else {
+ memcpy(align_buf, trailing_buf, 1);
+ write_atapi_data(base, 1, align_buf);
}
+ words++;
}
+
+ return words << 1;
}
/**
{
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- pr_debug("in atapi irq clear\n");
- ATAPI_SET_INT_STATUS(base, 0x1FF);
+ dev_dbg(ap->dev, "in atapi irq clear\n");
+ ATAPI_SET_INT_STATUS(base, ATAPI_GET_INT_STATUS(base)|ATAPI_DEV_INT
+ | MULTI_DONE_INT | UDMAIN_DONE_INT | UDMAOUT_DONE_INT
+ | MULTI_TERM_INT | UDMAIN_TERM_INT | UDMAOUT_TERM_INT);
}
/**
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
u8 tmp;
- pr_debug("in atapi irq on\n");
+ dev_dbg(ap->dev, "in atapi irq on\n");
ap->ctl &= ~ATA_NIEN;
ap->last_ctl = ap->ctl;
return tmp;
}
-/**
- * bfin_irq_ack - Acknowledge a device interrupt.
- * @ap: Port on which interrupts are enabled.
- *
- * Note: Original code is ata_irq_ack().
- */
-
-static unsigned char bfin_irq_ack(struct ata_port *ap, unsigned int chk_drq)
-{
- void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- unsigned int bits = chk_drq ? ATA_BUSY | ATA_DRQ : ATA_BUSY;
- unsigned char status;
-
- pr_debug("in atapi irq ack\n");
- status = ata_busy_wait(ap, bits, 1000);
- if (status & bits)
- if (ata_msg_err(ap))
- dev_err(ap->dev, "abnormal status 0x%X\n", status);
-
- /* get controller status; clear intr, err bits */
- ATAPI_SET_INT_STATUS(base, ATAPI_GET_INT_STATUS(base)|ATAPI_DEV_INT
- | MULTI_DONE_INT | UDMAIN_DONE_INT | UDMAOUT_DONE_INT
- | MULTI_TERM_INT | UDMAIN_TERM_INT | UDMAOUT_TERM_INT);
-
- return bfin_bmdma_status(ap);
-}
-
/**
* bfin_bmdma_freeze - Freeze DMA controller port
* @ap: port to freeze
{
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
- pr_debug("in atapi dma freeze\n");
+ dev_dbg(ap->dev, "in atapi dma freeze\n");
ap->ctl |= ATA_NIEN;
ap->last_ctl = ap->ctl;
* Note: Original code is ata_std_postreset().
*/
-static void bfin_std_postreset(struct ata_port *ap, unsigned int *classes)
+static void bfin_std_postreset(struct ata_link *link, unsigned int *classes)
{
+ struct ata_port *ap = link->ap;
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
/* re-enable interrupts */
static void bfin_port_stop(struct ata_port *ap)
{
- pr_debug("in atapi port stop\n");
+ dev_dbg(ap->dev, "in atapi port stop\n");
if (ap->udma_mask != 0 || ap->mwdma_mask != 0) {
free_dma(CH_ATAPI_RX);
free_dma(CH_ATAPI_TX);
static int bfin_port_start(struct ata_port *ap)
{
- pr_debug("in atapi port start\n");
+ dev_dbg(ap->dev, "in atapi port start\n");
if (!(ap->udma_mask || ap->mwdma_mask))
return 0;
.slave_configure = ata_scsi_slave_config,
.slave_destroy = ata_scsi_slave_destroy,
.bios_param = ata_std_bios_param,
-#ifdef CONFIG_PM
- .resume = ata_scsi_device_resume,
- .suspend = ata_scsi_device_suspend,
-#endif
};
static const struct ata_port_operations bfin_pata_ops = {
- .port_disable = ata_port_disable,
.set_piomode = bfin_set_piomode,
.set_dmamode = bfin_set_dmamode,
.irq_handler = ata_interrupt,
.irq_clear = bfin_irq_clear,
.irq_on = bfin_irq_on,
- .irq_ack = bfin_irq_ack,
.port_start = bfin_port_start,
.port_stop = bfin_port_stop,
| ATA_FLAG_NO_LEGACY,
.pio_mask = 0x1f, /* pio0-4 */
.mwdma_mask = 0,
-#ifdef CONFIG_PATA_BF54X_DMA
- .udma_mask = ATA_UDMA5,
-#else
.udma_mask = 0,
-#endif
.port_ops = &bfin_pata_ops,
},
};
int board_idx = 0;
struct resource *res;
struct ata_host *host;
+ unsigned int fsclk = get_sclk();
+ int udma_mode = 5;
const struct ata_port_info *ppi[] =
{ &bfin_port_info[board_idx], NULL };
if (res == NULL)
return -EINVAL;
+ while (bfin_port_info[board_idx].udma_mask > 0 &&
+ udma_fsclk[udma_mode] > fsclk) {
+ udma_mode--;
+ bfin_port_info[board_idx].udma_mask >>= 1;
+ }
+
/*
* Now that that's out of the way, wire up the port..
*/
},
};
+#define ATAPI_MODE_SIZE 10
+static char bfin_atapi_mode[ATAPI_MODE_SIZE];
+
static int __init bfin_atapi_init(void)
{
pr_info("register bfin atapi driver\n");
+
+ switch(bfin_atapi_mode[0]) {
+ case 'p':
+ case 'P':
+ break;
+ case 'm':
+ case 'M':
+ bfin_port_info[0].mwdma_mask = ATA_MWDMA2;
+ break;
+ default:
+ bfin_port_info[0].udma_mask = ATA_UDMA5;
+ };
+
return platform_driver_register(&bfin_atapi_driver);
}
module_init(bfin_atapi_init);
module_exit(bfin_atapi_exit);
+/*
+ * ATAPI mode:
+ * pio/PIO
+ * udma/UDMA (default)
+ * mwdma/MWDMA
+ */
+module_param_string(bfin_atapi_mode, bfin_atapi_mode, ATAPI_MODE_SIZE, 0);
MODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>");
MODULE_DESCRIPTION("PATA driver for blackfin 54x ATAPI controller");
git.samba.org / sfrench / cifs-2.6.git / blobdiff