Merge patch series "RISC-V: Align the shadow stack"

[sfrench/cifs-2.6.git] / arch / riscv / kernel / entry.S

diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 32b2ddafedb0cb1083492bbd68ab3e3c2df0bfb7..99d38fdf8b18f2f18fe3bae2dce2d7a3e5b11b5a 100644 (file)
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -397,6 +397,19 @@ handle_syscall_trace_exit:
 
 #ifdef CONFIG_VMAP_STACK
 handle_kernel_stack_overflow:
+       /*
+        * Takes the psuedo-spinlock for the shadow stack, in case multiple
+        * harts are concurrently overflowing their kernel stacks.  We could
+        * store any value here, but since we're overflowing the kernel stack
+        * already we only have SP to use as a scratch register.  So we just
+        * swap in the address of the spinlock, as that's definately non-zero.
+        *
+        * Pairs with a store_release in handle_bad_stack().
+        */
+1:     la sp, spin_shadow_stack
+       REG_AMOSWAP_AQ sp, sp, (sp)
+       bnez sp, 1b
+
        la sp, shadow_stack
        addi sp, sp, SHADOW_OVERFLOW_STACK_SIZE