* This version of the driver is somewhat selectable for the different
* processor/board combinations. It works for the boards I know about
* now, and should be easily modified to include others. Some of the
- * configuration information is contained in <asm/commproc.h> and the
+ * configuration information is contained in <asm/cpm1.h> and the
* remainder is here.
*
* Buffer descriptors are kept in the CPM dual port RAM, and the frame
#include <asm/pgtable.h>
#include <asm/mpc8xx.h>
#include <asm/uaccess.h>
-#include <asm/commproc.h>
+#include <asm/cpm1.h>
+#include <asm/cacheflush.h>
/*
* Theory of Operation
* programming documents for details unique to your board.
*
* For the TQM8xx(L) modules, there is no control register interface.
- * All functions are directly controlled using I/O pins. See <asm/commproc.h>.
+ * All functions are directly controlled using I/O pins. See <asm/cpm1.h>.
*/
/* The transmitter timeout
*((volatile uint *)BCSR1) &= ~BCSR1_ETHEN;
#endif
-#ifdef CONFIG_MPC885ADS
-
- /* Deassert PHY reset and enable the PHY.
- */
- {
- volatile uint __iomem *bcsr = ioremap(BCSR_ADDR, BCSR_SIZE);
- uint tmp;
-
- tmp = in_be32(bcsr + 1 /* BCSR1 */);
- tmp |= BCSR1_ETHEN;
- out_be32(bcsr + 1, tmp);
- tmp = in_be32(bcsr + 4 /* BCSR4 */);
- tmp |= BCSR4_ETH10_RST;
- out_be32(bcsr + 4, tmp);
- iounmap(bcsr);
- }
-
- /* On MPC885ADS SCC ethernet PHY defaults to the full duplex mode
- * upon reset. SCC is set to half duplex by default. So this
- * inconsistency should be better fixed by the software.
- */
-#endif
-
dev->base_addr = (unsigned long)ep;
#if 0
dev->name = "CPM_ENET";