MIPS: Tidy up CP0.Config6 bits definition

[sfrench/cifs-2.6.git] / arch / mips / include / asm / mipsregs.h

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 796fe47cfd1737994923aecff019c0bfea09274a..796dbb86575ba75876db3edfd974b09e10c5aad2 100644 (file)
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -468,6 +468,7 @@
 #define EXCCODE_THREAD         25      /* Thread exceptions (MT) */
 #define EXCCODE_DSPDIS         26      /* DSP disabled exception */
 #define EXCCODE_GE             27      /* Virtualized guest exception (VZ) */
+#define EXCCODE_CACHEERR       30      /* Parity/ECC occured on a core */
 
 /* Implementation specific trap codes used by MIPS cores */
 #define MIPS_EXCCODE_TLBPAR    16      /* TLB parity error exception */
@@ -563,6 +564,17 @@
 #define MIPS_CONF_MT_FTLB      (_ULCAST_(4) <<  7)
 #define MIPS_CONF_AR           (_ULCAST_(7) << 10)
 #define MIPS_CONF_AT           (_ULCAST_(3) << 13)
+#define MIPS_CONF_BE           (_ULCAST_(1) << 15)
+#define MIPS_CONF_BM           (_ULCAST_(1) << 16)
+#define MIPS_CONF_MM           (_ULCAST_(3) << 17)
+#define MIPS_CONF_MM_SYSAD     (_ULCAST_(1) << 17)
+#define MIPS_CONF_MM_FULL      (_ULCAST_(2) << 17)
+#define MIPS_CONF_SB           (_ULCAST_(1) << 21)
+#define MIPS_CONF_UDI          (_ULCAST_(1) << 22)
+#define MIPS_CONF_DSP          (_ULCAST_(1) << 23)
+#define MIPS_CONF_ISP          (_ULCAST_(1) << 24)
+#define MIPS_CONF_KU           (_ULCAST_(3) << 25)
+#define MIPS_CONF_K23          (_ULCAST_(3) << 28)
 #define MIPS_CONF_M            (_ULCAST_(1) << 31)
 
 /*
@@ -674,13 +686,38 @@
 #define MIPS_CONF5_CV          (_ULCAST_(1) << 29)
 #define MIPS_CONF5_K           (_ULCAST_(1) << 30)
 
-#define MIPS_CONF6_SYND                (_ULCAST_(1) << 13)
+/* Config6 feature bits for proAptiv/P5600 */
+
+/* Jump register cache prediction disable */
+#define MIPS_CONF6_MTI_JRCD            (_ULCAST_(1) << 0)
+/* MIPSr6 extensions enable */
+#define MIPS_CONF6_MTI_R6              (_ULCAST_(1) << 2)
+/* IFU Performance Control */
+#define MIPS_CONF6_MTI_IFUPERFCTL      (_ULCAST_(3) << 10)
+#define MIPS_CONF6_MTI_SYND            (_ULCAST_(1) << 13)
+/* Sleep state performance counter disable */
+#define MIPS_CONF6_MTI_SPCD            (_ULCAST_(1) << 14)
 /* proAptiv FTLB on/off bit */
-#define MIPS_CONF6_FTLBEN      (_ULCAST_(1) << 15)
-/* Loongson-3 FTLB on/off bit */
-#define MIPS_CONF6_FTLBDIS     (_ULCAST_(1) << 22)
+#define MIPS_CONF6_MTI_FTLBEN          (_ULCAST_(1) << 15)
+/* Disable load/store bonding */
+#define MIPS_CONF6_MTI_DLSB            (_ULCAST_(1) << 21)
 /* FTLB probability bits */
-#define MIPS_CONF6_FTLBP_SHIFT (16)
+#define MIPS_CONF6_MTI_FTLBP_SHIFT     (16)
+
+/* Config6 feature bits for Loongson-3 */
+
+/* Loongson-3 internal timer bit */
+#define MIPS_CONF6_LOONGSON_INTIMER    (_ULCAST_(1) << 6)
+/* Loongson-3 external timer bit */
+#define MIPS_CONF6_LOONGSON_EXTIMER    (_ULCAST_(1) << 7)
+/* Loongson-3 SFB on/off bit, STFill in manual */
+#define MIPS_CONF6_LOONGSON_SFBEN      (_ULCAST_(1) << 8)
+/* Loongson-3's LL on exclusive cacheline */
+#define MIPS_CONF6_LOONGSON_LLEXC      (_ULCAST_(1) << 16)
+/* Loongson-3's SC has a random delay */
+#define MIPS_CONF6_LOONGSON_SCRAND     (_ULCAST_(1) << 17)
+/* Loongson-3 FTLB on/off bit, VTLBOnly in manual */
+#define MIPS_CONF6_LOONGSON_FTLBDIS    (_ULCAST_(1) << 22)
 
 #define MIPS_CONF7_WII         (_ULCAST_(1) << 31)
 
@@ -753,10 +790,18 @@
 
 /* MAAR bit definitions */
 #define MIPS_MAAR_VH           (_U64CAST_(1) << 63)
-#define MIPS_MAAR_ADDR         ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
+#define MIPS_MAAR_ADDR         GENMASK_ULL(55, 12)
 #define MIPS_MAAR_ADDR_SHIFT   12
 #define MIPS_MAAR_S            (_ULCAST_(1) << 1)
 #define MIPS_MAAR_VL           (_ULCAST_(1) << 0)
+#ifdef CONFIG_XPA
+#define MIPS_MAAR_V            (MIPS_MAAR_VH | MIPS_MAAR_VL)
+#else
+#define MIPS_MAAR_V            MIPS_MAAR_VL
+#endif
+#define MIPS_MAARX_VH          (_ULCAST_(1) << 31)
+#define MIPS_MAARX_ADDR                0xF
+#define MIPS_MAARX_ADDR_SHIFT  32
 
 /* MAARI bit definitions */
 #define MIPS_MAARI_INDEX       (_ULCAST_(0x3f) << 0)
@@ -997,6 +1042,8 @@
 #define LOONGSON_DIAG_ITLB     (_ULCAST_(1) << 2)
 /* Flush DTLB */
 #define LOONGSON_DIAG_DTLB     (_ULCAST_(1) << 3)
+/* Allow some CACHE instructions (CACHE0, 1, 3, 21 and 23) in user mode */
+#define LOONGSON_DIAG_UCAC     (_ULCAST_(1) << 8)
 /* Flush VTLB */
 #define LOONGSON_DIAG_VTLB     (_ULCAST_(1) << 12)
 /* Flush FTLB */
@@ -1717,6 +1764,8 @@ do {                                                                      \
 #define write_c0_lladdr(val)   __write_ulong_c0_register($17, 0, val)
 #define read_c0_maar()         __read_ulong_c0_register($17, 1)
 #define write_c0_maar(val)     __write_ulong_c0_register($17, 1, val)
+#define readx_c0_maar()                __readx_32bit_c0_register($17, 1)
+#define writex_c0_maar(val)    __writex_32bit_c0_register($17, 1, val)
 #define read_c0_maari()                __read_32bit_c0_register($17, 2)
 #define write_c0_maari(val)    __write_32bit_c0_register($17, 2, val)