Merge tag 'zonefs-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/dlemoal...

[sfrench/cifs-2.6.git] / arch / arm64 / boot / dts / ti / k3-am64-main.dtsi

diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index e348114f42e017cfaa3dd02ab20e06e12dfed138..6f9aa5e02138f4613d7b8da9cf8a6841710ad571 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -1,8 +1,8 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
 /*
  * Device Tree Source for AM642 SoC Family Main Domain peripherals
  *
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <dt-bindings/phy/phy-cadence.h>
@@ -51,10 +51,11 @@
                        reg = <0x00000014 0x4>;
                };
 
-               serdes_ln_ctrl: mux-controller {
-                       compatible = "mmio-mux";
+               serdes_ln_ctrl: mux-controller@4080 {
+                       compatible = "reg-mux";
+                       reg = <0x4080 0x4>;
                        #mux-control-cells = <1>;
-                       mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */
+                       mux-reg-masks = <0x0 0x3>; /* SERDES0 lane0 select */
                };
 
                phy_gmii_sel: phy@4044 {
@@ -626,13 +627,18 @@
                power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 57 0>, <&k3_clks 57 1>;
                clock-names = "clk_ahb", "clk_xin";
+               bus-width = <8>;
                mmc-ddr-1_8v;
                mmc-hs200-1_8v;
+               ti,clkbuf-sel = <0x7>;
                ti,trm-icp = <0x2>;
                ti,otap-del-sel-legacy = <0x0>;
                ti,otap-del-sel-mmc-hs = <0x0>;
                ti,otap-del-sel-ddr52 = <0x6>;
                ti,otap-del-sel-hs200 = <0x7>;
+               ti,itap-del-sel-legacy = <0x10>;
+               ti,itap-del-sel-mmc-hs = <0xa>;
+               ti,itap-del-sel-ddr52 = <0x3>;
                status = "disabled";
        };
 
@@ -643,15 +649,19 @@
                power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
                clocks = <&k3_clks 58 3>, <&k3_clks 58 4>;
                clock-names = "clk_ahb", "clk_xin";
-               ti,trm-icp = <0x2>;
+               bus-width = <4>;
+               ti,clkbuf-sel = <0x7>;
                ti,otap-del-sel-legacy = <0x0>;
-               ti,otap-del-sel-sd-hs = <0xf>;
+               ti,otap-del-sel-sd-hs = <0x0>;
                ti,otap-del-sel-sdr12 = <0xf>;
                ti,otap-del-sel-sdr25 = <0xf>;
                ti,otap-del-sel-sdr50 = <0xc>;
                ti,otap-del-sel-sdr104 = <0x6>;
                ti,otap-del-sel-ddr50 = <0x9>;
-               ti,clkbuf-sel = <0x7>;
+               ti,itap-del-sel-legacy = <0x0>;
+               ti,itap-del-sel-sd-hs = <0x0>;
+               ti,itap-del-sel-sdr12 = <0x0>;
+               ti,itap-del-sel-sdr25 = <0x0>;
                status = "disabled";
        };
 
@@ -1041,25 +1051,6 @@
                status = "disabled";
        };
 
-       pcie0_ep: pcie-ep@f102000 {
-               compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep";
-               reg = <0x00 0x0f102000 0x00 0x1000>,
-                     <0x00 0x0f100000 0x00 0x400>,
-                     <0x00 0x0d000000 0x00 0x00800000>,
-                     <0x00 0x68000000 0x00 0x08000000>;
-               reg-names = "intd_cfg", "user_cfg", "reg", "mem";
-               interrupt-names = "link_state";
-               interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
-               ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
-               max-link-speed = <2>;
-               num-lanes = <1>;
-               power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
-               clocks = <&k3_clks 114 0>;
-               clock-names = "fck";
-               max-functions = /bits/ 8 <1>;
-               status = "disabled";
-       };
-
        epwm0: pwm@23000000 {
                compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
                #pwm-cells = <3>;
@@ -1244,6 +1235,18 @@
                        };
                };
 
+               icssg0_iep0: iep@2e000 {
+                       compatible = "ti,am654-icss-iep";
+                       reg = <0x2e000 0x1000>;
+                       clocks = <&icssg0_iepclk_mux>;
+               };
+
+               icssg0_iep1: iep@2f000 {
+                       compatible = "ti,am654-icss-iep";
+                       reg = <0x2f000 0x1000>;
+                       clocks = <&icssg0_iepclk_mux>;
+               };
+
                icssg0_mii_rt: mii-rt@32000 {
                        compatible = "ti,pruss-mii", "syscon";
                        reg = <0x32000 0x100>;
@@ -1385,6 +1388,18 @@
                        };
                };
 
+               icssg1_iep0: iep@2e000 {
+                       compatible = "ti,am654-icss-iep";
+                       reg = <0x2e000 0x1000>;
+                       clocks = <&icssg1_iepclk_mux>;
+               };
+
+               icssg1_iep1: iep@2f000 {
+                       compatible = "ti,am654-icss-iep";
+                       reg = <0x2f000 0x1000>;
+                       clocks = <&icssg1_iepclk_mux>;
+               };
+
                icssg1_mii_rt: mii-rt@32000 {
                        compatible = "ti,pruss-mii", "syscon";
                        reg = <0x32000 0x100>;