Merge tag 'zonefs-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/dlemoal...

[sfrench/cifs-2.6.git] / arch / arm64 / boot / dts / renesas / r9a07g054.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 1f1d481dc7830de9dcdbad91a0cc48534dcd1708..53d8905f367afd5b8ef95bd08da6122cef240317 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -798,6 +798,22 @@
                        reset-names = "rst", "arst", "prst";
                        power-domains = <&cpg>;
                        status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                                       dsi0_in: endpoint {
+                                               remote-endpoint = <&du_out_dsi>;
+                                       };
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+                               };
+                       };
                };
 
                vspd: vsp@10870000 {
@@ -826,6 +842,37 @@
                        resets = <&cpg R9A07G054_LCDC_RESET_N>;
                };
 
+               du: display@10890000 {
+                       compatible = "renesas,r9a07g054-du",
+                                    "renesas,r9a07g044-du";
+                       reg = <0 0x10890000 0 0x10000>;
+                       interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>,
+                                <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>,
+                                <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>;
+                       clock-names = "aclk", "pclk", "vclk";
+                       power-domains = <&cpg>;
+                       resets = <&cpg R9A07G054_LCDC_RESET_N>;
+                       renesas,vsps = <&vspd 0>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                                       du_out_dsi: endpoint {
+                                               remote-endpoint = <&dsi0_in>;
+                                       };
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+                               };
+                       };
+               };
+
                cpg: clock-controller@11010000 {
                        compatible = "renesas,r9a07g054-cpg";
                        reg = <0 0x11010000 0 0x10000>;
@@ -912,7 +959,27 @@
                                     <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
+                                    <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "nmi", "irq0", "irq1", "irq2", "irq3",
+                                         "irq4", "irq5", "irq6", "irq7",
+                                         "tint0", "tint1", "tint2", "tint3",
+                                         "tint4", "tint5", "tint6", "tint7",
+                                         "tint8", "tint9", "tint10", "tint11",
+                                         "tint12", "tint13", "tint14", "tint15",
+                                         "tint16", "tint17", "tint18", "tint19",
+                                         "tint20", "tint21", "tint22", "tint23",
+                                         "tint24", "tint25", "tint26", "tint27",
+                                         "tint28", "tint29", "tint30", "tint31",
+                                         "bus-err", "ec7tie1-0", "ec7tie2-0",
+                                         "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
+                                         "ec7tiovf-1";
                        clocks = <&cpg CPG_MOD R9A07G054_IA55_CLK>,
                                 <&cpg CPG_MOD R9A07G054_IA55_PCLK>;
                        clock-names = "clk", "pclk";