Merge tag 'zonefs-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/dlemoal...
[sfrench/cifs-2.6.git] / arch / arm64 / boot / dts / qcom / sa8775p.dtsi
index a7eaca33d326441d64df943bc72258b6d2d29707..231cea1f0fa8f46d890146ed8d7f469bbf40d210 100644 (file)
                        no-map;
                };
 
+               ddr_training_checksum: ddr-training-checksum@908c0000 {
+                       reg = <0x0 0x908c0000 0x0 0x1000>;
+                       no-map;
+               };
+
                reserved_mem: reserved@908f0000 {
-                       reg = <0x0 0x908f0000 0x0 0xf000>;
+                       reg = <0x0 0x908f0000 0x0 0xe000>;
                        no-map;
                };
 
-               secdata_apss_mem: secdata-apss@908ff000 {
-                       reg = <0x0 0x908ff000 0x0 0x1000>;
+               secdata_apss_mem: secdata-apss@908fe000 {
+                       reg = <0x0 0x908fe000 0x0 0x2000>;
                        no-map;
                };
 
                        hwlocks = <&tcsr_mutex 3>;
                };
 
-               cpucp_fw_mem: cpucp-fw@90b00000 {
-                       reg = <0x0 0x90b00000 0x0 0x100000>;
+               tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 {
+                       reg = <0x0 0x90c00000 0x0 0x100000>;
+                       no-map;
+               };
+
+               sail_mailbox_mem: sail-ss@90d00000 {
+                       reg = <0x0 0x90d00000 0x0 0x100000>;
+                       no-map;
+               };
+
+               sail_ota_mem: sail-ss@90e00000 {
+                       reg = <0x0 0x90e00000 0x0 0x300000>;
+                       no-map;
+               };
+
+               aoss_backup_mem: aoss-backup@91b00000 {
+                       reg = <0x0 0x91b00000 0x0 0x40000>;
+                       no-map;
+               };
+
+               cpucp_backup_mem: cpucp-backup@91b40000 {
+                       reg = <0x0 0x91b40000 0x0 0x40000>;
+                       no-map;
+               };
+
+               tz_config_backup_mem: tz-config-backup@91b80000 {
+                       reg = <0x0 0x91b80000 0x0 0x10000>;
+                       no-map;
+               };
+
+               ddr_training_data_mem: ddr-training-data@91b90000 {
+                       reg = <0x0 0x91b90000 0x0 0x10000>;
+                       no-map;
+               };
+
+               cdt_data_backup_mem: cdt-data-backup@91ba0000 {
+                       reg = <0x0 0x91ba0000 0x0 0x1000>;
                        no-map;
                };
 
                        no-map;
                };
 
+               audio_mdf_mem: audio-mdf-region@ae000000 {
+                       reg = <0x0 0xae000000 0x0 0x1000000>;
+                       no-map;
+               };
+
+               firmware_mem: firmware-region@b0000000 {
+                       reg = <0x0 0xb0000000 0x0 0x800000>;
+                       no-map;
+               };
+
                hyptz_reserved_mem: hyptz-reserved@beb00000 {
                        reg = <0x0 0xbeb00000 0x0 0x11500000>;
                        no-map;
                };
 
-               tz_stat_mem: tz-stat@d0000000 {
-                       reg = <0x0 0xd0000000 0x0 0x100000>;
+               scmi_mem: scmi-region@d0000000 {
+                       reg = <0x0 0xd0000000 0x0 0x40000>;
+                       no-map;
+               };
+
+               firmware_logs_mem: firmware-logs@d0040000 {
+                       reg = <0x0 0xd0040000 0x0 0x10000>;
+                       no-map;
+               };
+
+               firmware_audio_mem: firmware-audio@d0050000 {
+                       reg = <0x0 0xd0050000 0x0 0x4000>;
+                       no-map;
+               };
+
+               firmware_reserved_mem: firmware-reserved@d0054000 {
+                       reg = <0x0 0xd0054000 0x0 0x9c000>;
+                       no-map;
+               };
+
+               firmware_quantum_test_mem: firmware-quantum-test@d00f0000 {
+                       reg = <0x0 0xd00f0000 0x0 0x10000>;
                        no-map;
                };
 
                        no-map;
                };
 
-               trusted_apps_mem: trusted-apps@d1800000 {
-                       reg = <0x0 0xd1800000 0x0 0x3900000>;
+               deepsleep_backup_mem: deepsleep-backup@d1800000 {
+                       reg = <0x0 0xd1800000 0x0 0x100000>;
+                       no-map;
+               };
+
+               trusted_apps_mem: trusted-apps@d1900000 {
+                       reg = <0x0 0xd1900000 0x0 0x3800000>;
+                       no-map;
+               };
+
+               tz_stat_mem: tz-stat@db100000 {
+                       reg = <0x0 0xdb100000 0x0 0x100000>;
+                       no-map;
+               };
+
+               cpucp_fw_mem: cpucp-fw@db200000 {
+                       reg = <0x0 0xdb200000 0x0 0x100000>;
                        no-map;
                };
        };
                        assigned-clock-rates = <19200000>, <200000000>;
 
                        interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
                                              <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
                                              <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
                                              <&pdc 12 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "pwr_event",
+                                         "hs_phy_irq",
                                          "dp_hs_phy_irq",
                                          "dm_hs_phy_irq",
                                          "ss_phy_irq";
                        assigned-clock-rates = <19200000>, <200000000>;
 
                        interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
                                              <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
                                              <&pdc 7 IRQ_TYPE_EDGE_BOTH>,
                                              <&pdc 13 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "pwr_event",
+                                         "hs_phy_irq",
                                          "dp_hs_phy_irq",
                                          "dm_hs_phy_irq",
                                          "ss_phy_irq";
                        assigned-clock-rates = <19200000>, <200000000>;
 
                        interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
                                              <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
                                              <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
                        interrupt-names = "pwr_event",
+                                         "hs_phy_irq",
                                          "dp_hs_phy_irq",
                                          "dm_hs_phy_irq";
 
                              <0x0 0x23016000 0x0 0x100>;
                        reg-names = "stmmaceth", "rgmii";
 
-                       interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-names = "macirq";
+                       interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "macirq", "sfty";
 
                        clocks = <&gcc GCC_EMAC1_AXI_CLK>,
                                 <&gcc GCC_EMAC1_SLV_AHB_CLK>,
                              <0x0 0x23056000 0x0 0x100>;
                        reg-names = "stmmaceth", "rgmii";
 
-                       interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-names = "macirq";
+                       interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "macirq", "sfty";
 
                        clocks = <&gcc GCC_EMAC0_AXI_CLK>,
                                 <&gcc GCC_EMAC0_SLV_AHB_CLK>,