Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...

[sfrench/cifs-2.6.git] / arch / arm64 / boot / dts / qcom / msm8916.dtsi

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 039991f808317027822148650831c3509b7d349c..dc3817593e144708a514a5605491801056e662ab 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -88,6 +88,11 @@
                        no-map;
                };
 
+               venus_mem: venus@89900000 {
+                       reg = <0x0 0x89900000 0x0 0x600000>;
+                       no-map;
+               };
+
                mba_mem: mba@8ea00000 {
                        no-map;
                        reg = <0 0x8ea00000 0 0x100000>;
@@ -204,6 +209,17 @@
 
        };
 
+       gpu_opp_table: opp_table {
+               compatible = "operating-points-v2";
+
+               opp-400000000 {
+                       opp-hz = /bits/ 64 <400000000>;
+               };
+               opp-19200000 {
+                       opp-hz = /bits/ 64 <19200000>;
+               };
+       };
+
        timer {
                compatible = "arm,armv8-timer";
                interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@@ -694,6 +710,84 @@
                        #thermal-sensor-cells = <1>;
                };
 
+               apps_iommu: iommu@1ef0000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       #iommu-cells = <1>;
+                       compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
+                       ranges = <0 0x1e20000 0x40000>;
+                       reg = <0x1ef0000 0x3000>;
+                       clocks = <&gcc GCC_SMMU_CFG_CLK>,
+                                <&gcc GCC_APSS_TCU_CLK>;
+                       clock-names = "iface", "bus";
+                       qcom,iommu-secure-id = <17>;
+
+                       // mdp_0:
+                       iommu-ctx@4000 {
+                               compatible = "qcom,msm-iommu-v1-ns";
+                               reg = <0x4000 0x1000>;
+                               interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+
+                       // venus_ns:
+                       iommu-ctx@5000 {
+                               compatible = "qcom,msm-iommu-v1-sec";
+                               reg = <0x5000 0x1000>;
+                               interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+               };
+
+               gpu_iommu: iommu@1f08000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       #iommu-cells = <1>;
+                       compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
+                       ranges = <0 0x1f08000 0x10000>;
+                       clocks = <&gcc GCC_SMMU_CFG_CLK>,
+                                <&gcc GCC_GFX_TCU_CLK>;
+                       clock-names = "iface", "bus";
+                       qcom,iommu-secure-id = <18>;
+
+                       // gfx3d_user:
+                       iommu-ctx@1000 {
+                               compatible = "qcom,msm-iommu-v1-ns";
+                               reg = <0x1000 0x1000>;
+                               interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+
+                       // gfx3d_priv:
+                       iommu-ctx@2000 {
+                               compatible = "qcom,msm-iommu-v1-ns";
+                               reg = <0x2000 0x1000>;
+                               interrupts = <GIC_SPI 242 0>;
+                       };
+               };
+
+               gpu@1c00000 {
+                       compatible = "qcom,adreno-306.0", "qcom,adreno";
+                       reg = <0x01c00000 0x20000>;
+                       reg-names = "kgsl_3d0_reg_memory";
+                       interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "kgsl_3d0_irq";
+                       clock-names =
+                           "core",
+                           "iface",
+                           "mem",
+                           "mem_iface",
+                           "alt_mem_iface",
+                           "gfx3d";
+                       clocks =
+                           <&gcc GCC_OXILI_GFX3D_CLK>,
+                           <&gcc GCC_OXILI_AHB_CLK>,
+                           <&gcc GCC_OXILI_GMEM_CLK>,
+                           <&gcc GCC_BIMC_GFX_CLK>,
+                           <&gcc GCC_BIMC_GPU_CLK>,
+                           <&gcc GFX3D_CLK_SRC>;
+                       power-domains = <&gcc OXILI_GDSC>;
+                       operating-points-v2 = <&gpu_opp_table>;
+                       iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
+               };
+
                mdss: mdss@1a00000 {
                        compatible = "qcom,mdss";
                        reg = <0x1a00000 0x1000>,
@@ -735,6 +829,8 @@
                                              "core_clk",
                                              "vsync_clk";
 
+                               iommus = <&apps_iommu 4>;
+
                                ports {
                                        #address-cells = <1>;
                                        #size-cells = <0>;
@@ -990,7 +1086,7 @@
                };
 
                replicator@824000 {
-                       compatible = "qcom,coresight-replicator1x", "arm,primecell";
+                       compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
                        reg = <0x824000 0x1000>;
 
                        clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
@@ -1207,6 +1303,28 @@
                                };
                        };
                };
+
+               venus: video-codec@1d00000 {
+                       compatible = "qcom,msm8916-venus";
+                       reg = <0x01d00000 0xff000>;
+                       interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+                       power-domains = <&gcc VENUS_GDSC>;
+                       clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
+                                <&gcc GCC_VENUS0_AHB_CLK>,
+                                <&gcc GCC_VENUS0_AXI_CLK>;
+                       clock-names = "core", "iface", "bus";
+                       iommus = <&apps_iommu 5>;
+                       memory-region = <&venus_mem>;
+                       status = "okay";
+
+                       video-decoder {
+                               compatible = "venus-decoder";
+                       };
+
+                       video-encoder {
+                               compatible = "venus-encoder";
+                       };
+               };
        };
 
        smd {