Merge tag 'zonefs-6.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/dlemoal...

[sfrench/cifs-2.6.git] / arch / arm64 / boot / dts / freescale / imx8mm-kontron-bl.dts

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts
index dcec57c20399edf6e457b5fbf4fbc2b9dd0370b1..aab8e24216501e154ea521abf83a2b2fbd8d9219 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts
@@ -279,8 +279,8 @@
 
        pinctrl_i2c4: i2c4grp {
                fsl,pins = <
-                       MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL                  0x400001c3
-                       MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA                  0x400001c3
+                       MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL                  0x40000083
+                       MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA                  0x40000083
                >;
        };
 
@@ -292,19 +292,19 @@
 
        pinctrl_uart1: uart1grp {
                fsl,pins = <
-                       MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX              0x140
-                       MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX             0x140
-                       MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B          0x140
-                       MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B          0x140
+                       MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX              0x0
+                       MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX             0x0
+                       MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B          0x0
+                       MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B          0x0
                >;
        };
 
        pinctrl_uart2: uart2grp {
                fsl,pins = <
-                       MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX             0x140
-                       MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX              0x140
-                       MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B           0x140
-                       MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B           0x140
+                       MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX             0x0
+                       MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX              0x0
+                       MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B           0x0
+                       MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B           0x0
                >;
        };
 
@@ -316,40 +316,40 @@
 
        pinctrl_usdhc2: usdhc2grp {
                fsl,pins = <
-                       MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                 0x190
+                       MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                 0x90
                        MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD                 0x1d0
                        MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0             0x1d0
                        MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1             0x1d0
                        MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2             0x1d0
                        MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3             0x1d0
-                       MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                0x019
-                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0x1d0
+                       MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                0x19
+                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xd0
                >;
        };
 
        pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
                fsl,pins = <
-                       MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                 0x194
+                       MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                 0x94
                        MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD                 0x1d4
                        MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0             0x1d4
                        MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1             0x1d4
                        MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2             0x1d4
                        MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3             0x1d4
-                       MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                0x019
-                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0x1d0
+                       MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                0x19
+                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xd0
                >;
        };
 
        pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
                fsl,pins = <
-                       MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                 0x196
+                       MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                 0x96
                        MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD                 0x1d6
                        MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0             0x1d6
                        MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1             0x1d6
                        MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2             0x1d6
                        MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3             0x1d6
-                       MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                0x019
-                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0x1d0
+                       MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                0x19
+                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xd0
                >;
        };
 };