Merge branch 'avr32-arch' of git://git.kernel.org/pub/scm/linux/kernel/git/hskinnemoe...

[sfrench/cifs-2.6.git] / arch / arm / mm / Kconfig

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index d490f3773c01c12aec0b1266d55aa8b92193649b..20979564e7ee3cc04825e43f4b4af42bc7fc65be 100644 (file)
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -186,6 +186,24 @@ config CPU_ARM926T
          Say Y if you want support for the ARM926T processor.
          Otherwise, say N.
 
+# FA526
+config CPU_FA526
+       bool
+       select CPU_32v4
+       select CPU_ABRT_EV4
+       select CPU_PABRT_NOIFAR
+       select CPU_CACHE_VIVT
+       select CPU_CP15_MMU
+       select CPU_CACHE_FA
+       select CPU_COPY_FA if MMU
+       select CPU_TLB_FA if MMU
+       help
+         The FA526 is a version of the ARMv4 compatible processor with
+         Branch Target Buffer, Unified TLB and cache line size 16.
+
+         Say Y if you want support for the FA526 processor.
+         Otherwise, say N.
+
 # ARM940T
 config CPU_ARM940T
        bool "Support ARM940T processor" if ARCH_INTEGRATOR
@@ -340,6 +358,17 @@ config CPU_XSC3
        select CPU_TLB_V4WBI if MMU
        select IO_36
 
+# Marvell PJ1 (Mohawk)
+config CPU_MOHAWK
+       bool
+       select CPU_32v5
+       select CPU_ABRT_EV5T
+       select CPU_PABRT_NOIFAR
+       select CPU_CACHE_VIVT
+       select CPU_CP15_MMU
+       select CPU_TLB_V4WBI if MMU
+       select CPU_COPY_V4WB if MMU
+
 # Feroceon
 config CPU_FEROCEON
        bool
@@ -484,6 +513,9 @@ config CPU_CACHE_VIVT
 config CPU_CACHE_VIPT
        bool
 
+config CPU_CACHE_FA
+       bool
+
 if MMU
 # The copy-page model
 config CPU_COPY_V3
@@ -498,6 +530,9 @@ config CPU_COPY_V4WB
 config CPU_COPY_FEROCEON
        bool
 
+config CPU_COPY_FA
+       bool
+
 config CPU_COPY_V6
        bool
 
@@ -528,6 +563,13 @@ config CPU_TLB_FEROCEON
        help
          Feroceon TLB (v4wbi with non-outer-cachable page table walks).
 
+config CPU_TLB_FA
+       bool
+       help
+         Faraday ARM FA526 architecture, unified TLB with writeback cache
+         and invalidate instruction cache entry. Branch target buffer is
+         also supported.
+
 config CPU_TLB_V6
        bool
 
@@ -569,7 +611,7 @@ comment "Processor Features"
 
 config ARM_THUMB
        bool "Support Thumb user binaries"
-       depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7 || CPU_FEROCEON
+       depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V7 || CPU_FEROCEON
        default y
        help
          Say Y if you want to include kernel support for running user space
@@ -638,7 +680,7 @@ config CPU_DCACHE_SIZE
 
 config CPU_DCACHE_WRITETHROUGH
        bool "Force write through D-cache"
-       depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE
+       depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
        default y if CPU_ARM925T
        help
          Say Y here to use the data cache in writethrough mode. Unless you
@@ -653,7 +695,7 @@ config CPU_CACHE_ROUND_ROBIN
 
 config CPU_BPREDICT_DISABLE
        bool "Disable branch prediction"
-       depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7
+       depends on CPU_ARM1020 || CPU_V6 || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526
        help
          Say Y here to disable branch prediction.  If unsure, say N.
 
@@ -704,7 +746,8 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
 
 config CACHE_L2X0
        bool "Enable the L2x0 outer cache controller"
-       depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || REALVIEW_EB_A9MP
+       depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
+                  REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31
        default y
        select OUTER_CACHE
        help