{
u32 val = 0;
- if (cpu_is_omap24xx())
+ if (cpu_is_omap24xx()) {
val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
- else if (cpu_is_omap34xx())
+ } else if (cpu_is_omap34xx()) {
val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
- else {
+ } else {
pr_err("Cannot detect omap type!\n");
goto out;
}
u32 cpuid, idcode;
u16 hawkeye;
u8 rev;
- char *rev_name = "ES1.0";
/*
* We cannot access revision registers on ES1.0.
cpuid = read_cpuid(CPUID_ID);
if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
omap_revision = OMAP3430_REV_ES1_0;
- goto out;
+ return;
}
/*
hawkeye = (idcode >> 12) & 0xffff;
rev = (idcode >> 28) & 0xff;
- if (hawkeye == 0xb7ae) {
+ switch (hawkeye) {
+ case 0xb7ae:
+ /* Handle 34xx/35xx devices */
switch (rev) {
- case 0:
+ case 0: /* Take care of early samples */
+ case 1:
omap_revision = OMAP3430_REV_ES2_0;
- rev_name = "ES2.0";
break;
case 2:
omap_revision = OMAP3430_REV_ES2_1;
- rev_name = "ES2.1";
break;
case 3:
omap_revision = OMAP3430_REV_ES3_0;
- rev_name = "ES3.0";
break;
case 4:
- omap_revision = OMAP3430_REV_ES3_1;
- rev_name = "ES3.1";
- break;
+ /* FALLTHROUGH */
default:
/* Use the latest known revision as default */
omap_revision = OMAP3430_REV_ES3_1;
- rev_name = "Unknown revision\n";
}
+ break;
+ case 0xb868:
+ /* Handle OMAP35xx/AM35xx devices
+ *
+ * Set the device to be OMAP3505 here. Actual device
+ * is identified later based on the features.
+ */
+ omap_revision = OMAP3505_REV(rev);
+ break;
+ case 0xb891:
+ /* FALLTHROUGH */
+ default:
+ /* Unknown default to latest silicon rev as default*/
+ omap_revision = OMAP3630_REV_ES1_0;
}
+}
-out:
- pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
+void __init omap4_check_revision(void)
+{
+ u32 idcode;
+ u16 hawkeye;
+ u8 rev;
+ char *rev_name = "ES1.0";
+
+ /*
+ * The IC rev detection is done with hawkeye and rev.
+ * Note that rev does not map directly to defined processor
+ * revision numbers as ES1.0 uses value 0.
+ */
+ idcode = read_tap_reg(OMAP_TAP_IDCODE);
+ hawkeye = (idcode >> 12) & 0xffff;
+ rev = (idcode >> 28) & 0xff;
+
+ if ((hawkeye == 0xb852) && (rev == 0x0)) {
+ omap_revision = OMAP4430_REV_ES1_0;
+ pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
+ return;
+ }
+
+ pr_err("Unknown OMAP4 CPU id\n");
}
#define OMAP3_SHOW_FEATURE(feat) \
- if (omap3_has_ ##feat()) { \
- pr_info (" - "#feat" : Y"); \
- } else { \
- pr_info (" - "#feat" : N"); \
- }
+ if (omap3_has_ ##feat()) \
+ printk(#feat" ");
void __init omap3_cpuinfo(void)
{
+ u8 rev = GET_OMAP_REVISION();
+ char cpu_name[16], cpu_rev[16];
+
+ /* OMAP3430 and OMAP3530 are assumed to be same.
+ *
+ * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
+ * on available features. Upon detection, update the CPU id
+ * and CPU class bits.
+ */
+ if (cpu_is_omap3630()) {
+ strcpy(cpu_name, "OMAP3630");
+ } else if (cpu_is_omap3505()) {
+ /*
+ * AM35xx devices
+ */
+ if (omap3_has_sgx()) {
+ omap_revision = OMAP3517_REV(rev);
+ strcpy(cpu_name, "AM3517");
+ } else {
+ /* Already set in omap3_check_revision() */
+ strcpy(cpu_name, "AM3505");
+ }
+ } else if (omap3_has_iva() && omap3_has_sgx()) {
+ /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
+ strcpy(cpu_name, "OMAP3430/3530");
+ } else if (omap3_has_iva()) {
+ omap_revision = OMAP3525_REV(rev);
+ strcpy(cpu_name, "OMAP3525");
+ } else if (omap3_has_sgx()) {
+ omap_revision = OMAP3515_REV(rev);
+ strcpy(cpu_name, "OMAP3515");
+ } else {
+ omap_revision = OMAP3503_REV(rev);
+ strcpy(cpu_name, "OMAP3503");
+ }
+
+ switch (rev) {
+ case OMAP_REVBITS_00:
+ strcpy(cpu_rev, "1.0");
+ break;
+ case OMAP_REVBITS_10:
+ strcpy(cpu_rev, "2.0");
+ break;
+ case OMAP_REVBITS_20:
+ strcpy(cpu_rev, "2.1");
+ break;
+ case OMAP_REVBITS_30:
+ strcpy(cpu_rev, "3.0");
+ break;
+ case OMAP_REVBITS_40:
+ /* FALLTHROUGH */
+ default:
+ /* Use the latest known revision as default */
+ strcpy(cpu_rev, "3.1");
+ }
+
+ /* Print verbose information */
+ pr_info("%s ES%s (", cpu_name, cpu_rev);
+
OMAP3_SHOW_FEATURE(l2cache);
OMAP3_SHOW_FEATURE(iva);
OMAP3_SHOW_FEATURE(sgx);
OMAP3_SHOW_FEATURE(neon);
OMAP3_SHOW_FEATURE(isp);
+
+ printk(")\n");
}
/*
* At this point we have an idea about the processor revision set
* earlier with omap2_set_globals_tap().
*/
- if (cpu_is_omap24xx())
+ if (cpu_is_omap24xx()) {
omap24xx_check_revision();
- else if (cpu_is_omap34xx()) {
- omap3_check_features();
+ } else if (cpu_is_omap34xx()) {
omap3_check_revision();
+ omap3_check_features();
omap3_cpuinfo();
- }
- else if (cpu_is_omap44xx()) {
- printk(KERN_INFO "FIXME: CPU revision = OMAP4430\n");
+ } else if (cpu_is_omap44xx()) {
+ omap4_check_revision();
return;
- } else
+ } else {
pr_err("OMAP revision unknown, please fix!\n");
+ }
/*
* OK, now we know the exact revision. Initialize omap_chip bits
} else if (cpu_is_omap242x()) {
/* Currently only supports 2420ES2.1.1 and 2420-all */
omap_chip.oc |= CHIP_IS_OMAP2420;
+ } else if (cpu_is_omap3505() || cpu_is_omap3517()) {
+ omap_chip.oc = CHIP_IS_OMAP3430 | CHIP_IS_OMAP3430ES3_1;
} else if (cpu_is_omap343x()) {
omap_chip.oc = CHIP_IS_OMAP3430;
if (omap_rev() == OMAP3430_REV_ES1_0)
omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
else if (omap_rev() == OMAP3430_REV_ES3_1)
omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
+ else if (omap_rev() == OMAP3630_REV_ES1_0)
+ omap_chip.oc |= CHIP_IS_OMAP3630ES1;
} else {
pr_err("Uninitialized omap_chip, please fix!\n");
}
git.samba.org / sfrench / cifs-2.6.git / blobdiff