Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jmorris...

[sfrench/cifs-2.6.git] / arch / arm / mach-kirkwood / include / mach / kirkwood.h

diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index af4f0000dcef31adf260e4c1def6365e4158a002..041653a04a9ccd0db3e8b99cbff4da6ea135f96b 100644 (file)
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -45,7 +45,7 @@
 #define KIRKWOOD_PCIE_IO_SIZE          SZ_64K
 
 #define KIRKWOOD_REGS_PHYS_BASE                0xf1000000
-#define KIRKWOOD_REGS_VIRT_BASE                0xfed00000
+#define KIRKWOOD_REGS_VIRT_BASE                IOMEM(0xfed00000)
 #define KIRKWOOD_REGS_SIZE             SZ_1M
 
 #define KIRKWOOD_PCIE_MEM_PHYS_BASE    0xe0000000
@@ -59,61 +59,61 @@
 /*
  * Register Map
  */
-#define DDR_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x00000)
-#define  DDR_WINDOW_CPU_BASE   (DDR_VIRT_BASE | 0x1500)
-#define DDR_OPERATION_BASE     (DDR_VIRT_BASE | 0x1418)
-
-#define DEV_BUS_PHYS_BASE      (KIRKWOOD_REGS_PHYS_BASE | 0x10000)
-#define DEV_BUS_VIRT_BASE      (KIRKWOOD_REGS_VIRT_BASE | 0x10000)
-#define  SAMPLE_AT_RESET       (DEV_BUS_VIRT_BASE | 0x0030)
-#define  DEVICE_ID             (DEV_BUS_VIRT_BASE | 0x0034)
-#define  GPIO_LOW_VIRT_BASE    (DEV_BUS_VIRT_BASE | 0x0100)
-#define  GPIO_HIGH_VIRT_BASE   (DEV_BUS_VIRT_BASE | 0x0140)
-#define  RTC_PHYS_BASE         (DEV_BUS_PHYS_BASE | 0x0300)
-#define  SPI_PHYS_BASE         (DEV_BUS_PHYS_BASE | 0x0600)
-#define  I2C_PHYS_BASE         (DEV_BUS_PHYS_BASE | 0x1000)
-#define  UART0_PHYS_BASE       (DEV_BUS_PHYS_BASE | 0x2000)
-#define  UART0_VIRT_BASE       (DEV_BUS_VIRT_BASE | 0x2000)
-#define  UART1_PHYS_BASE       (DEV_BUS_PHYS_BASE | 0x2100)
-#define  UART1_VIRT_BASE       (DEV_BUS_VIRT_BASE | 0x2100)
-
-#define BRIDGE_VIRT_BASE       (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
-#define BRIDGE_PHYS_BASE       (KIRKWOOD_REGS_PHYS_BASE | 0x20000)
-
-#define CRYPTO_PHYS_BASE       (KIRKWOOD_REGS_PHYS_BASE | 0x30000)
-
-#define PCIE_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
-#define PCIE_LINK_CTRL         (PCIE_VIRT_BASE | 0x70)
-#define PCIE_STATUS            (PCIE_VIRT_BASE | 0x1a04)
-#define PCIE1_VIRT_BASE                (KIRKWOOD_REGS_VIRT_BASE | 0x44000)
-#define PCIE1_LINK_CTRL                (PCIE1_VIRT_BASE | 0x70)
-#define PCIE1_STATUS           (PCIE1_VIRT_BASE | 0x1a04)
-
-#define USB_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
-
-#define XOR0_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE | 0x60800)
-#define XOR0_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE | 0x60800)
-#define XOR1_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE | 0x60900)
-#define XOR1_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE | 0x60900)
-#define XOR0_HIGH_PHYS_BASE    (KIRKWOOD_REGS_PHYS_BASE | 0x60A00)
-#define XOR0_HIGH_VIRT_BASE    (KIRKWOOD_REGS_VIRT_BASE | 0x60A00)
-#define XOR1_HIGH_PHYS_BASE    (KIRKWOOD_REGS_PHYS_BASE | 0x60B00)
-#define XOR1_HIGH_VIRT_BASE    (KIRKWOOD_REGS_VIRT_BASE | 0x60B00)
-
-#define GE00_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE | 0x70000)
-#define GE01_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE | 0x74000)
-
-#define SATA_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE | 0x80000)
-#define SATA_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE | 0x80000)
-#define SATA0_IF_CTRL          (SATA_VIRT_BASE | 0x2050)
-#define SATA0_PHY_MODE_2       (SATA_VIRT_BASE | 0x2330)
-#define SATA1_IF_CTRL          (SATA_VIRT_BASE | 0x4050)
-#define SATA1_PHY_MODE_2       (SATA_VIRT_BASE | 0x4330)
-
-#define SDIO_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE | 0x90000)
-
-#define AUDIO_PHYS_BASE                (KIRKWOOD_REGS_PHYS_BASE | 0xA0000)
-#define AUDIO_VIRT_BASE                (KIRKWOOD_REGS_VIRT_BASE | 0xA0000)
+#define DDR_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE + 0x00000)
+#define  DDR_WINDOW_CPU_BASE   (DDR_VIRT_BASE + 0x1500)
+#define DDR_OPERATION_BASE     (DDR_VIRT_BASE + 0x1418)
+
+#define DEV_BUS_PHYS_BASE      (KIRKWOOD_REGS_PHYS_BASE + 0x10000)
+#define DEV_BUS_VIRT_BASE      (KIRKWOOD_REGS_VIRT_BASE + 0x10000)
+#define  SAMPLE_AT_RESET       (DEV_BUS_VIRT_BASE + 0x0030)
+#define  DEVICE_ID             (DEV_BUS_VIRT_BASE + 0x0034)
+#define  GPIO_LOW_VIRT_BASE    (DEV_BUS_VIRT_BASE + 0x0100)
+#define  GPIO_HIGH_VIRT_BASE   (DEV_BUS_VIRT_BASE + 0x0140)
+#define  RTC_PHYS_BASE         (DEV_BUS_PHYS_BASE + 0x0300)
+#define  SPI_PHYS_BASE         (DEV_BUS_PHYS_BASE + 0x0600)
+#define  I2C_PHYS_BASE         (DEV_BUS_PHYS_BASE + 0x1000)
+#define  UART0_PHYS_BASE       (DEV_BUS_PHYS_BASE + 0x2000)
+#define  UART0_VIRT_BASE       (DEV_BUS_VIRT_BASE + 0x2000)
+#define  UART1_PHYS_BASE       (DEV_BUS_PHYS_BASE + 0x2100)
+#define  UART1_VIRT_BASE       (DEV_BUS_VIRT_BASE + 0x2100)
+
+#define BRIDGE_VIRT_BASE       (KIRKWOOD_REGS_VIRT_BASE + 0x20000)
+#define BRIDGE_PHYS_BASE       (KIRKWOOD_REGS_PHYS_BASE + 0x20000)
+
+#define CRYPTO_PHYS_BASE       (KIRKWOOD_REGS_PHYS_BASE + 0x30000)
+
+#define PCIE_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE + 0x40000)
+#define PCIE_LINK_CTRL         (PCIE_VIRT_BASE + 0x70)
+#define PCIE_STATUS            (PCIE_VIRT_BASE + 0x1a04)
+#define PCIE1_VIRT_BASE                (KIRKWOOD_REGS_VIRT_BASE + 0x44000)
+#define PCIE1_LINK_CTRL                (PCIE1_VIRT_BASE + 0x70)
+#define PCIE1_STATUS           (PCIE1_VIRT_BASE + 0x1a04)
+
+#define USB_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x50000)
+
+#define XOR0_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE + 0x60800)
+#define XOR0_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE + 0x60800)
+#define XOR1_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE + 0x60900)
+#define XOR1_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE + 0x60900)
+#define XOR0_HIGH_PHYS_BASE    (KIRKWOOD_REGS_PHYS_BASE + 0x60A00)
+#define XOR0_HIGH_VIRT_BASE    (KIRKWOOD_REGS_VIRT_BASE + 0x60A00)
+#define XOR1_HIGH_PHYS_BASE    (KIRKWOOD_REGS_PHYS_BASE + 0x60B00)
+#define XOR1_HIGH_VIRT_BASE    (KIRKWOOD_REGS_VIRT_BASE + 0x60B00)
+
+#define GE00_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE + 0x70000)
+#define GE01_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE + 0x74000)
+
+#define SATA_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE + 0x80000)
+#define SATA_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE + 0x80000)
+#define SATA0_IF_CTRL          (SATA_VIRT_BASE + 0x2050)
+#define SATA0_PHY_MODE_2       (SATA_VIRT_BASE + 0x2330)
+#define SATA1_IF_CTRL          (SATA_VIRT_BASE + 0x4050)
+#define SATA1_PHY_MODE_2       (SATA_VIRT_BASE + 0x4330)
+
+#define SDIO_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE + 0x90000)
+
+#define AUDIO_PHYS_BASE                (KIRKWOOD_REGS_PHYS_BASE + 0xA0000)
+#define AUDIO_VIRT_BASE                (KIRKWOOD_REGS_VIRT_BASE + 0xA0000)
 
 /*
  * Supported devices and revisions.