ARM: sunxi: dt: Remove the FSF address

[sfrench/cifs-2.6.git] / arch / arm / boot / dts / sun6i-a31.dtsi

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index fa2f403ccf28adf4f6aa10c08978dd3b59b6e709..27d60e9a4bb806d55f33fe1c447a713bf2f46e69 100644 (file)
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -18,11 +18,6 @@
  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  *     GNU General Public License for more details.
  *
- *     You should have received a copy of the GNU General Public
- *     License along with this file; if not, write to the Free
- *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- *     MA 02110-1301 USA
- *
  * Or, alternatively,
  *
  *  b) Permission is hereby granted, free of charge, to any person
@@ -50,6 +45,7 @@
 #include "skeleton.dtsi"
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
 
 #include <dt-bindings/pinctrl/sun4i-a10.h>
 
@@ -96,10 +92,22 @@
                #address-cells = <1>;
                #size-cells = <0>;
 
-               cpu@0 {
+               cpu0: cpu@0 {
                        compatible = "arm,cortex-a7";
                        device_type = "cpu";
                        reg = <0>;
+                       clocks = <&cpu>;
+                       clock-latency = <244144>; /* 8 32k periods */
+                       operating-points = <
+                               /* kHz    uV */
+                               1008000 1200000
+                               864000  1200000
+                               720000  1100000
+                               480000  1000000
+                               >;
+                       #cooling-cells = <2>;
+                       cooling-min-level = <0>;
+                       cooling-max-level = <3>;
                };
 
                cpu@1 {
@@ -121,6 +129,38 @@
                };
        };
 
+       thermal-zones {
+               cpu_thermal {
+                       /* milliseconds */
+                       polling-delay-passive = <250>;
+                       polling-delay = <1000>;
+                       thermal-sensors = <&rtp>;
+
+                       cooling-maps {
+                               map0 {
+                                       trip = <&cpu_alert0>;
+                                       cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                               };
+                       };
+
+                       trips {
+                               cpu_alert0: cpu_alert0 {
+                                       /* milliCelsius */
+                                       temperature = <70000>;
+                                       hysteresis = <2000>;
+                                       type = "passive";
+                               };
+
+                               cpu_crit: cpu_crit {
+                                       /* milliCelsius */
+                                       temperature = <100000>;
+                                       hysteresis = <2000>;
+                                       type = "critical";
+                               };
+                       };
+               };
+       };
+
        memory {
                reg = <0x40000000 0x80000000>;
        };
@@ -196,6 +236,14 @@
                        reg = <0x01c20054 0x4>;
                        clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
                        clock-output-names = "ahb1";
+
+                       /*
+                        * Clock AHB1 from PLL6, instead of CPU/AXI which
+                        * has rate changes due to cpufreq. Also the DMA
+                        * controller requires AHB1 clocked from PLL6.
+                        */
+                       assigned-clocks = <&ahb1>;
+                       assigned-clock-parents = <&pll6 0>;
                };
 
                ahb1_gates: clk@01c20060 {
@@ -381,10 +429,6 @@
                        clocks = <&ahb1_gates 6>;
                        resets = <&ahb1_rst 6>;
                        #dma-cells = <1>;
-
-                       /* DMA controller requires AHB1 clocked from PLL6 */
-                       assigned-clocks = <&ahb1>;
-                       assigned-clock-parents = <&pll6 0>;
                };
 
                mmc0: mmc@01c0f000 {
@@ -402,6 +446,8 @@
                        reset-names = "ahb";
                        interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
                        status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
                };
 
                mmc1: mmc@01c10000 {
@@ -419,6 +465,8 @@
                        reset-names = "ahb";
                        interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
                        status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
                };
 
                mmc2: mmc@01c11000 {
@@ -436,6 +484,8 @@
                        reset-names = "ahb";
                        interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
                        status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
                };
 
                mmc3: mmc@01c12000 {
@@ -453,6 +503,8 @@
                        reset-names = "ahb";
                        interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
                        status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
                };
 
                usbphy: phy@01c19400 {
@@ -581,6 +633,14 @@
                                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                        };
 
+                       mmc1_pins_a: mmc1@0 {
+                               allwinner,pins = "PG0", "PG1", "PG2", "PG3",
+                                                "PG4", "PG5";
+                               allwinner,function = "mmc1";
+                               allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+                               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+                       };
+
                        gmac_pins_mii_a: gmac_mii@0 {
                                allwinner,pins = "PA0", "PA1", "PA2", "PA3",
                                                "PA8", "PA9", "PA11",
@@ -973,6 +1033,27 @@
                                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                        };
+
+                       p2wi_pins: p2wi {
+                               allwinner,pins = "PL0", "PL1";
+                               allwinner,function = "s_p2wi";
+                               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+                       };
+               };
+
+               p2wi: i2c@01f03400 {
+                       compatible = "allwinner,sun6i-a31-p2wi";
+                       reg = <0x01f03400 0x400>;
+                       interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&apb0_gates 3>;
+                       clock-frequency = <100000>;
+                       resets = <&apb0_rst 3>;
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&p2wi_pins>;
+                       status = "disabled";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
                };
        };
 };