Merge tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux

[sfrench/cifs-2.6.git] / arch / arm / boot / dts / sun6i-a31.dtsi

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 4083201e93c8cc3a99f912be7cbcbf630869f7c6..f47156b6572bbaf09872686b70f09268200c3cc9 100644 (file)
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -8,18 +8,18 @@
  * licensing only applies to this file, and not this project as a
  * whole.
  *
- *  a) This library is free software; you can redistribute it and/or
+ *  a) This file is free software; you can redistribute it and/or
  *     modify it under the terms of the GNU General Public License as
  *     published by the Free Software Foundation; either version 2 of the
  *     License, or (at your option) any later version.
  *
- *     This library is distributed in the hope that it will be useful,
+ *     This file is distributed in the hope that it will be useful,
  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  *     GNU General Public License for more details.
  *
  *     You should have received a copy of the GNU General Public
- *     License along with this library; if not, write to the Free
+ *     License along with this file; if not, write to the Free
  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  *     MA 02110-1301 USA
  *
@@ -62,6 +62,18 @@
                ethernet0 = &gmac;
        };
 
+       chosen {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               framebuffer@0 {
+                       compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
+                       allwinner,pipeline = "de_be0-lcd0-hdmi";
+                       clocks = <&pll6 0>;
+                       status = "disabled";
+               };
+       };
 
        cpus {
                enable-method = "allwinner,sun6i-a31";
@@ -132,11 +144,11 @@
                };
 
                pll6: clk@01c20028 {
-                       #clock-cells = <0>;
+                       #clock-cells = <1>;
                        compatible = "allwinner,sun6i-a31-pll6-clk";
                        reg = <0x01c20028 0x4>;
                        clocks = <&osc24M>;
-                       clock-output-names = "pll6";
+                       clock-output-names = "pll6", "pll6x2";
                };
 
                cpu: cpu@01c20050 {
@@ -166,7 +178,7 @@
                        #clock-cells = <0>;
                        compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
                        reg = <0x01c20054 0x4>;
-                       clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
+                       clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
                        clock-output-names = "ahb1_mux";
                };
 
@@ -221,7 +233,7 @@
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-apb1-clk";
                        reg = <0x01c20058 0x4>;
-                       clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
+                       clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
                        clock-output-names = "apb2";
                };
 
@@ -240,7 +252,7 @@
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20088 0x4>;
-                       clocks = <&osc24M>, <&pll6>;
+                       clocks = <&osc24M>, <&pll6 0>;
                        clock-output-names = "mmc0";
                };
 
@@ -248,7 +260,7 @@
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c2008c 0x4>;
-                       clocks = <&osc24M>, <&pll6>;
+                       clocks = <&osc24M>, <&pll6 0>;
                        clock-output-names = "mmc1";
                };
 
@@ -256,7 +268,7 @@
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20090 0x4>;
-                       clocks = <&osc24M>, <&pll6>;
+                       clocks = <&osc24M>, <&pll6 0>;
                        clock-output-names = "mmc2";
                };
 
@@ -264,7 +276,7 @@
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c20094 0x4>;
-                       clocks = <&osc24M>, <&pll6>;
+                       clocks = <&osc24M>, <&pll6 0>;
                        clock-output-names = "mmc3";
                };
 
@@ -272,7 +284,7 @@
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a0 0x4>;
-                       clocks = <&osc24M>, <&pll6>;
+                       clocks = <&osc24M>, <&pll6 0>;
                        clock-output-names = "spi0";
                };
 
@@ -280,7 +292,7 @@
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a4 0x4>;
-                       clocks = <&osc24M>, <&pll6>;
+                       clocks = <&osc24M>, <&pll6 0>;
                        clock-output-names = "spi1";
                };
 
@@ -288,7 +300,7 @@
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200a8 0x4>;
-                       clocks = <&osc24M>, <&pll6>;
+                       clocks = <&osc24M>, <&pll6 0>;
                        clock-output-names = "spi2";
                };
 
@@ -296,7 +308,7 @@
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";
                        reg = <0x01c200ac 0x4>;
-                       clocks = <&osc24M>, <&pll6>;
+                       clocks = <&osc24M>, <&pll6 0>;
                        clock-output-names = "spi3";
                };
 
@@ -353,6 +365,10 @@
                        clocks = <&ahb1_gates 6>;
                        resets = <&ahb1_rst 6>;
                        #dma-cells = <1>;
+
+                       /* DMA controller requires AHB1 clocked from PLL6 */
+                       assigned-clocks = <&ahb1_mux>;
+                       assigned-clock-parents = <&pll6 0>;
                };
 
                mmc0: mmc@01c0f000 {
@@ -832,7 +848,7 @@
                        ar100: ar100_clk {
                                compatible = "allwinner,sun6i-a31-ar100-clk";
                                #clock-cells = <0>;
-                               clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
+                               clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
                                clock-output-names = "ar100";
                        };