Merge tag 'armsoc-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

[sfrench/cifs-2.6.git] / arch / arm / boot / dts / sun5i.dtsi

diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 59a9426e3bd4ed68aefa8b3aca7469dd3e27f5dc..0840612b5ed6ddcc875c539f5416b6bdc8558e76 100644 (file)
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -88,6 +88,15 @@
                        clock-output-names = "osc24M";
                };
 
+               osc3M: osc3M_clk {
+                       compatible = "fixed-factor-clock";
+                       #clock-cells = <0>;
+                       clock-div = <8>;
+                       clock-mult = <1>;
+                       clocks = <&osc24M>;
+                       clock-output-names = "osc3M";
+               };
+
                osc32k: clk@0 {
                        #clock-cells = <0>;
                        compatible = "fixed-clock";
@@ -112,6 +121,23 @@
                                             "pll2-4x", "pll2-8x";
                };
 
+               pll3: clk@01c20010 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-pll3-clk";
+                       reg = <0x01c20010 0x4>;
+                       clocks = <&osc3M>;
+                       clock-output-names = "pll3";
+               };
+
+               pll3x2: pll3x2_clk {
+                       compatible = "fixed-factor-clock";
+                       #clock-cells = <0>;
+                       clock-div = <1>;
+                       clock-mult = <2>;
+                       clocks = <&pll3>;
+                       clock-output-names = "pll3-2x";
+               };
+
                pll4: clk@01c20018 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-pll1-clk";
@@ -136,6 +162,23 @@
                        clock-output-names = "pll6_sata", "pll6_other", "pll6";
                };
 
+               pll7: clk@01c20030 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun4i-a10-pll3-clk";
+                       reg = <0x01c20030 0x4>;
+                       clocks = <&osc3M>;
+                       clock-output-names = "pll7";
+               };
+
+               pll7x2: pll7x2_clk {
+                       compatible = "fixed-factor-clock";
+                       #clock-cells = <0>;
+                       clock-div = <1>;
+                       clock-mult = <2>;
+                       clocks = <&pll7>;
+                       clock-output-names = "pll7-2x";
+               };
+
                /* dummy is 200M */
                cpu: cpu@01c20054 {
                        #clock-cells = <0>;