Merge branch 'work.afs' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs

[sfrench/cifs-2.6.git] / arch / arm / boot / dts / socfpga_arria10.dtsi

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index a4dcb68f4322e2c96dd8bad240bb94b7eb307c9e..59ef13e37536c917ecf5caa5db0e5647fed7fa4d 100644 (file)
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -377,13 +377,28 @@
                                                clk-gate = <0xC8 11>;
                                        };
 
-                                       nand_clk: nand_clk {
+                                       nand_x_clk: nand_x_clk {
                                                #clock-cells = <0>;
                                                compatible = "altr,socfpga-a10-gate-clk";
                                                clocks = <&l4_mp_clk>;
                                                clk-gate = <0xC8 10>;
                                        };
 
+                                       nand_ecc_clk: nand_ecc_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-a10-gate-clk";
+                                               clocks = <&nand_x_clk>;
+                                               clk-gate = <0xC8 10>;
+                                       };
+
+                                       nand_clk: nand_clk {
+                                               #clock-cells = <0>;
+                                               compatible = "altr,socfpga-a10-gate-clk";
+                                               clocks = <&nand_x_clk>;
+                                               fixed-divider = <4>;
+                                               clk-gate = <0xC8 10>;
+                                       };
+
                                        spi_m_clk: spi_m_clk {
                                                #clock-cells = <0>;
                                                compatible = "altr,socfpga-a10-gate-clk";
@@ -613,7 +628,7 @@
                        status = "disabled";
                };
 
-               sdr: sdr@ffc25000 {
+               sdr: sdr@ffcfb100 {
                        compatible = "altr,sdr-ctl", "syscon";
                        reg = <0xffcfb100 0x80>;
                };
@@ -650,7 +665,8 @@
                        reg-names = "nand_data", "denali_reg";
                        interrupts = <0 99 4>;
                        dma-mask = <0xffffffff>;
-                       clocks = <&nand_clk>;
+                       clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
+                       clock-names = "nand", "nand_x", "ecc";
                        status = "disabled";
                };
 
@@ -760,7 +776,7 @@
                timer@ffffc600 {
                        compatible = "arm,cortex-a9-twd-timer";
                        reg = <0xffffc600 0x100>;
-                       interrupts = <1 13 0xf04>;
+                       interrupts = <1 13 0xf01>;
                        clocks = <&mpu_periph_clk>;
                };
 
@@ -770,6 +786,8 @@
                        reg = <0xffc02700 0x100>;
                        clocks = <&l4_sp_clk>;
                        clock-names = "timer";
+                       resets = <&rst SPTIMER0_RESET>;
+                       reset-names = "timer";
                };
 
                timer1: timer1@ffc02800 {
@@ -778,6 +796,8 @@
                        reg = <0xffc02800 0x100>;
                        clocks = <&l4_sp_clk>;
                        clock-names = "timer";
+                       resets = <&rst SPTIMER1_RESET>;
+                       reset-names = "timer";
                };
 
                timer2: timer2@ffd00000 {
@@ -786,6 +806,8 @@
                        reg = <0xffd00000 0x100>;
                        clocks = <&l4_sys_free_clk>;
                        clock-names = "timer";
+                       resets = <&rst L4SYSTIMER0_RESET>;
+                       reset-names = "timer";
                };
 
                timer3: timer3@ffd00100 {
@@ -794,6 +816,8 @@
                        reg = <0xffd01000 0x100>;
                        clocks = <&l4_sys_free_clk>;
                        clock-names = "timer";
+                       resets = <&rst L4SYSTIMER1_RESET>;
+                       reset-names = "timer";
                };
 
                uart0: serial0@ffc02000 {