Merge tag 'mvebu-dt-5.1-2' of git://git.infradead.org/linux-mvebu into arm/dt

[sfrench/cifs-2.6.git] / arch / arm / boot / dts / socfpga.dtsi

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 2d300396f0edd49d16ae46b8949801071438d699..ec1966480f2f0376522bda05d1e7347821238a46 100644 (file)
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -1,18 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
- *  Copyright (C) 2012 Altera <www.altera.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ * Copyright (C) 2012 Altera <www.altera.com>
  */
 
 #include <dt-bindings/reset/altr,rst-mgr.h>
@@ -96,6 +84,7 @@
                                #dma-requests = <32>;
                                clocks = <&l4_main_clk>;
                                clock-names = "apb_pclk";
+                               resets = <&rst DMA_RESET>;
                        };
                };
 
@@ -112,6 +101,7 @@
                        reg = <0xffc00000 0x1000>;
                        interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
                        clocks = <&can0_clk>;
+                       resets = <&rst CAN0_RESET>;
                        status = "disabled";
                };
 
@@ -120,6 +110,7 @@
                        reg = <0xffc01000 0x1000>;
                        interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
                        clocks = <&can1_clk>;
+                       resets = <&rst CAN1_RESET>;
                        status = "disabled";
                };
 
@@ -597,6 +588,7 @@
                        compatible = "snps,dw-apb-gpio";
                        reg = <0xff708000 0x1000>;
                        clocks = <&l4_mp_clk>;
+                       resets = <&rst GPIO0_RESET>;
                        status = "disabled";
 
                        porta: gpio-controller@0 {
@@ -617,6 +609,7 @@
                        compatible = "snps,dw-apb-gpio";
                        reg = <0xff709000 0x1000>;
                        clocks = <&l4_mp_clk>;
+                       resets = <&rst GPIO1_RESET>;
                        status = "disabled";
 
                        portb: gpio-controller@0 {
@@ -637,6 +630,7 @@
                        compatible = "snps,dw-apb-gpio";
                        reg = <0xff70a000 0x1000>;
                        clocks = <&l4_mp_clk>;
+                       resets = <&rst GPIO2_RESET>;
                        status = "disabled";
 
                        portc: gpio-controller@0 {
@@ -747,6 +741,7 @@
                        #size-cells = <0>;
                        clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
                        clock-names = "biu", "ciu";
+                       resets = <&rst SDMMC_RESET>;
                        status = "disabled";
                };
 
@@ -758,9 +753,9 @@
                              <0xffb80000 0x10000>;
                        reg-names = "nand_data", "denali_reg";
                        interrupts = <0x0 0x90 0x4>;
-                       dma-mask = <0xffffffff>;
                        clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
                        clock-names = "nand", "nand_x", "ecc";
+                       resets = <&rst NAND_RESET>;
                        status = "disabled";
                };
 
@@ -771,7 +766,7 @@
 
                qspi: spi@ff705000 {
                        compatible = "cdns,qspi-nor";
-                        #address-cells = <1>;
+                       #address-cells = <1>;
                        #size-cells = <0>;
                        reg = <0xff705000 0x1000>,
                              <0xffa00000 0x1000>;
@@ -780,6 +775,7 @@
                        cdns,fifo-width = <4>;
                        cdns,trigger-address = <0x00000000>;
                        clocks = <&qspi_clk>;
+                       resets = <&rst QSPI_RESET>;
                        status = "disabled";
                };
 
@@ -798,6 +794,7 @@
                sdr: sdr@ffc25000 {
                        compatible = "altr,sdr-ctl", "syscon";
                        reg = <0xffc25000 0x1000>;
+                       resets = <&rst SDR_RESET>;
                };
 
                sdramedac {
@@ -814,6 +811,7 @@
                        interrupts = <0 154 4>;
                        num-cs = <4>;
                        clocks = <&spi_m_clk>;
+                       resets = <&rst SPIM0_RESET>;
                        status = "disabled";
                };
 
@@ -825,6 +823,7 @@
                        interrupts = <0 155 4>;
                        num-cs = <4>;
                        clocks = <&spi_m_clk>;
+                       resets = <&rst SPIM1_RESET>;
                        status = "disabled";
                };
 
@@ -891,6 +890,7 @@
                        dmas = <&pdma 28>,
                               <&pdma 29>;
                        dma-names = "tx", "rx";
+                       resets = <&rst UART0_RESET>;
                };
 
                uart1: serial1@ffc03000 {
@@ -903,6 +903,7 @@
                        dmas = <&pdma 30>,
                               <&pdma 31>;
                        dma-names = "tx", "rx";
+                       resets = <&rst UART1_RESET>;
                };
 
                usbphy0: usbphy {
@@ -942,6 +943,7 @@
                        reg = <0xffd02000 0x1000>;
                        interrupts = <0 171 4>;
                        clocks = <&osc1>;
+                       resets = <&rst L4WD0_RESET>;
                        status = "disabled";
                };
 
@@ -950,6 +952,7 @@
                        reg = <0xffd03000 0x1000>;
                        interrupts = <0 172 4>;
                        clocks = <&osc1>;
+                       resets = <&rst L4WD1_RESET>;
                        status = "disabled";
                };
        };