Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input

[sfrench/cifs-2.6.git] / arch / arm / boot / dts / r8a7778.dtsi

diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index 791aafd310a5d78bf0ac92f379b7a77ef2d9a03f..f83a348fc07a49e37f6bef9cbdd33cbc76f6d192 100644 (file)
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -17,6 +17,7 @@
 /include/ "skeleton.dtsi"
 
 #include <dt-bindings/clock/r8a7778-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
 / {
@@ -51,7 +52,7 @@ bsc: bus@1c000000 {
        ether: ethernet@fde00000 {
                compatible = "renesas,ether-r8a7778";
                reg = <0xfde00000 0x400>;
-               interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
+               interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
                power-domains = <&cpg_clocks>;
                phy-mode = "rmii";
@@ -79,17 +80,17 @@ irqpin: interrupt-controller@fe78001c {
                        <0xfe780024 4>,
                        <0xfe780044 4>,
                        <0xfe780064 4>;
-               interrupts =   <0 27 IRQ_TYPE_LEVEL_HIGH
-                               0 28 IRQ_TYPE_LEVEL_HIGH
-                               0 29 IRQ_TYPE_LEVEL_HIGH
-                               0 30 IRQ_TYPE_LEVEL_HIGH>;
+               interrupts =   <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
+                               GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
+                               GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
+                               GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
                sense-bitfield-width = <2>;
        };
 
        gpio0: gpio@ffc40000 {
                compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
                reg = <0xffc40000 0x2c>;
-               interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
+               interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
                gpio-ranges = <&pfc 0 0 32>;
@@ -100,7 +101,7 @@ gpio0: gpio@ffc40000 {
        gpio1: gpio@ffc41000 {
                compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
                reg = <0xffc41000 0x2c>;
-               interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
+               interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
                gpio-ranges = <&pfc 0 32 32>;
@@ -111,7 +112,7 @@ gpio1: gpio@ffc41000 {
        gpio2: gpio@ffc42000 {
                compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
                reg = <0xffc42000 0x2c>;
-               interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
+               interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
                gpio-ranges = <&pfc 0 64 32>;
@@ -122,7 +123,7 @@ gpio2: gpio@ffc42000 {
        gpio3: gpio@ffc43000 {
                compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
                reg = <0xffc43000 0x2c>;
-               interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
+               interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
                gpio-ranges = <&pfc 0 96 32>;
@@ -133,7 +134,7 @@ gpio3: gpio@ffc43000 {
        gpio4: gpio@ffc44000 {
                compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
                reg = <0xffc44000 0x2c>;
-               interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
+               interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
                gpio-ranges = <&pfc 0 128 27>;
@@ -151,7 +152,7 @@ i2c0: i2c@ffc70000 {
                #size-cells = <0>;
                compatible = "renesas,i2c-r8a7778";
                reg = <0xffc70000 0x1000>;
-               interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
+               interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
                power-domains = <&cpg_clocks>;
                status = "disabled";
@@ -162,7 +163,7 @@ i2c1: i2c@ffc71000 {
                #size-cells = <0>;
                compatible = "renesas,i2c-r8a7778";
                reg = <0xffc71000 0x1000>;
-               interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
+               interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
                power-domains = <&cpg_clocks>;
                status = "disabled";
@@ -173,7 +174,7 @@ i2c2: i2c@ffc72000 {
                #size-cells = <0>;
                compatible = "renesas,i2c-r8a7778";
                reg = <0xffc72000 0x1000>;
-               interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
+               interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
                power-domains = <&cpg_clocks>;
                status = "disabled";
@@ -184,7 +185,7 @@ i2c3: i2c@ffc73000 {
                #size-cells = <0>;
                compatible = "renesas,i2c-r8a7778";
                reg = <0xffc73000 0x1000>;
-               interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
+               interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
                power-domains = <&cpg_clocks>;
                status = "disabled";
@@ -193,9 +194,9 @@ i2c3: i2c@ffc73000 {
        tmu0: timer@ffd80000 {
                compatible = "renesas,tmu-r8a7778", "renesas,tmu";
                reg = <0xffd80000 0x30>;
-               interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
-                            <0 33 IRQ_TYPE_LEVEL_HIGH>,
-                            <0 34 IRQ_TYPE_LEVEL_HIGH>;
+               interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
                clock-names = "fck";
                power-domains = <&cpg_clocks>;
@@ -208,9 +209,9 @@ tmu0: timer@ffd80000 {
        tmu1: timer@ffd81000 {
                compatible = "renesas,tmu-r8a7778", "renesas,tmu";
                reg = <0xffd81000 0x30>;
-               interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
-                            <0 37 IRQ_TYPE_LEVEL_HIGH>,
-                            <0 38 IRQ_TYPE_LEVEL_HIGH>;
+               interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
                clock-names = "fck";
                power-domains = <&cpg_clocks>;
@@ -223,9 +224,9 @@ tmu1: timer@ffd81000 {
        tmu2: timer@ffd82000 {
                compatible = "renesas,tmu-r8a7778", "renesas,tmu";
                reg = <0xffd82000 0x30>;
-               interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
-                            <0 41 IRQ_TYPE_LEVEL_HIGH>,
-                            <0 42 IRQ_TYPE_LEVEL_HIGH>;
+               interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
                clock-names = "fck";
                power-domains = <&cpg_clocks>;
@@ -285,72 +286,84 @@ rcar_sound,src {
                };
 
                rcar_sound,ssi {
-                       ssi3: ssi@3 { interrupts = <0 0x85 IRQ_TYPE_LEVEL_HIGH>; };
-                       ssi4: ssi@4 { interrupts = <0 0x85 IRQ_TYPE_LEVEL_HIGH>; };
-                       ssi5: ssi@5 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
-                       ssi6: ssi@6 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
-                       ssi7: ssi@7 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
-                       ssi8: ssi@8 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
-                       ssi9: ssi@9 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
+                       ssi3: ssi@3 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
+                       ssi4: ssi@4 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
+                       ssi5: ssi@5 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
+                       ssi6: ssi@6 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
+                       ssi7: ssi@7 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
+                       ssi8: ssi@8 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
+                       ssi9: ssi@9 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
                };
        };
 
        scif0: serial@ffe40000 {
-               compatible = "renesas,scif-r8a7778", "renesas,scif";
+               compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
+                            "renesas,scif";
                reg = <0xffe40000 0x100>;
-               interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&mstp0_clks R8A7778_CLK_SCIF0>;
-               clock-names = "sci_ick";
+               interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp0_clks R8A7778_CLK_SCIF0>,
+                        <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
+               clock-names = "fck", "brg_int", "scif_clk";
                power-domains = <&cpg_clocks>;
                status = "disabled";
        };
 
        scif1: serial@ffe41000 {
-               compatible = "renesas,scif-r8a7778", "renesas,scif";
+               compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
+                            "renesas,scif";
                reg = <0xffe41000 0x100>;
-               interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&mstp0_clks R8A7778_CLK_SCIF1>;
-               clock-names = "sci_ick";
+               interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp0_clks R8A7778_CLK_SCIF1>,
+                        <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
+               clock-names = "fck", "brg_int", "scif_clk";
                power-domains = <&cpg_clocks>;
                status = "disabled";
        };
 
        scif2: serial@ffe42000 {
-               compatible = "renesas,scif-r8a7778", "renesas,scif";
+               compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
+                            "renesas,scif";
                reg = <0xffe42000 0x100>;
-               interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&mstp0_clks R8A7778_CLK_SCIF2>;
-               clock-names = "sci_ick";
+               interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp0_clks R8A7778_CLK_SCIF2>,
+                        <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
+               clock-names = "fck", "brg_int", "scif_clk";
                power-domains = <&cpg_clocks>;
                status = "disabled";
        };
 
        scif3: serial@ffe43000 {
-               compatible = "renesas,scif-r8a7778", "renesas,scif";
+               compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
+                            "renesas,scif";
                reg = <0xffe43000 0x100>;
-               interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&mstp0_clks R8A7778_CLK_SCIF3>;
-               clock-names = "sci_ick";
+               interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp0_clks R8A7778_CLK_SCIF3>,
+                        <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
+               clock-names = "fck", "brg_int", "scif_clk";
                power-domains = <&cpg_clocks>;
                status = "disabled";
        };
 
        scif4: serial@ffe44000 {
-               compatible = "renesas,scif-r8a7778", "renesas,scif";
+               compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
+                            "renesas,scif";
                reg = <0xffe44000 0x100>;
-               interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&mstp0_clks R8A7778_CLK_SCIF4>;
-               clock-names = "sci_ick";
+               interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp0_clks R8A7778_CLK_SCIF4>,
+                        <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
+               clock-names = "fck", "brg_int", "scif_clk";
                power-domains = <&cpg_clocks>;
                status = "disabled";
        };
 
        scif5: serial@ffe45000 {
-               compatible = "renesas,scif-r8a7778", "renesas,scif";
+               compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
+                            "renesas,scif";
                reg = <0xffe45000 0x100>;
-               interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&mstp0_clks R8A7778_CLK_SCIF5>;
-               clock-names = "sci_ick";
+               interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&mstp0_clks R8A7778_CLK_SCIF5>,
+                        <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
+               clock-names = "fck", "brg_int", "scif_clk";
                power-domains = <&cpg_clocks>;
                status = "disabled";
        };
@@ -358,7 +371,7 @@ scif5: serial@ffe45000 {
        mmcif: mmc@ffe4e000 {
                compatible = "renesas,sh-mmcif";
                reg = <0xffe4e000 0x100>;
-               interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
+               interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7778_CLK_MMC>;
                power-domains = <&cpg_clocks>;
                status = "disabled";
@@ -367,7 +380,7 @@ mmcif: mmc@ffe4e000 {
        sdhi0: sd@ffe4c000 {
                compatible = "renesas,sdhi-r8a7778";
                reg = <0xffe4c000 0x100>;
-               interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
+               interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
                power-domains = <&cpg_clocks>;
                status = "disabled";
@@ -376,7 +389,7 @@ sdhi0: sd@ffe4c000 {
        sdhi1: sd@ffe4d000 {
                compatible = "renesas,sdhi-r8a7778";
                reg = <0xffe4d000 0x100>;
-               interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
+               interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
                power-domains = <&cpg_clocks>;
                status = "disabled";
@@ -385,7 +398,7 @@ sdhi1: sd@ffe4d000 {
        sdhi2: sd@ffe4f000 {
                compatible = "renesas,sdhi-r8a7778";
                reg = <0xffe4f000 0x100>;
-               interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+               interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
                power-domains = <&cpg_clocks>;
                status = "disabled";
@@ -394,7 +407,7 @@ sdhi2: sd@ffe4f000 {
        hspi0: spi@fffc7000 {
                compatible = "renesas,hspi-r8a7778", "renesas,hspi";
                reg = <0xfffc7000 0x18>;
-               interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
+               interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
                power-domains = <&cpg_clocks>;
                #address-cells = <1>;
@@ -405,7 +418,7 @@ hspi0: spi@fffc7000 {
        hspi1: spi@fffc8000 {
                compatible = "renesas,hspi-r8a7778", "renesas,hspi";
                reg = <0xfffc8000 0x18>;
-               interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
+               interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
                power-domains = <&cpg_clocks>;
                #address-cells = <1>;
@@ -416,7 +429,7 @@ hspi1: spi@fffc8000 {
        hspi2: spi@fffc6000 {
                compatible = "renesas,hspi-r8a7778", "renesas,hspi";
                reg = <0xfffc6000 0x18>;
-               interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
+               interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
                power-domains = <&cpg_clocks>;
                #address-cells = <1>;
@@ -437,6 +450,15 @@ extal_clk: extal_clk {
                        clock-output-names = "extal";
                };
 
+               /* External SCIF clock */
+               scif_clk: scif {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       /* This value must be overridden by the board. */
+                       clock-frequency = <0>;
+                       status = "disabled";
+               };
+
                /* Special CPG clocks */
                cpg_clocks: cpg_clocks@ffc80000 {
                        compatible = "renesas,r8a7778-cpg-clocks";