Merge branch 'for-4.14-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj...

[sfrench/cifs-2.6.git] / arch / arm / boot / dts / r8a7743.dtsi

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index f62e8587f1a8d1ea2b643e8e85f10b24aa19ad18..14222c72f0e0f7d5ad95a46d68b310df76fff6cc 100644 (file)
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -18,9 +18,19 @@
        #address-cells = <2>;
        #size-cells = <2>;
 
+       aliases {
+               i2c0 = &i2c0;
+               i2c1 = &i2c1;
+               i2c2 = &i2c2;
+               i2c3 = &i2c3;
+               i2c4 = &i2c4;
+               i2c5 = &i2c5;
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
+               enable-method = "renesas,apmu";
 
                cpu0: cpu@0 {
                        device_type = "cpu";
@@ -28,8 +38,26 @@
                        reg = <0>;
                        clock-frequency = <1500000000>;
                        clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
+                       clock-latency = <300000>; /* 300 us */
                        power-domains = <&sysc R8A7743_PD_CA15_CPU0>;
                        next-level-cache = <&L2_CA15>;
+
+                       /* kHz - uV - OPPs unknown yet */
+                       operating-points = <1500000 1000000>,
+                                          <1312500 1000000>,
+                                          <1125000 1000000>,
+                                          < 937500 1000000>,
+                                          < 750000 1000000>,
+                                          < 375000 1000000>;
+               };
+
+               cpu1: cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a15";
+                       reg = <1>;
+                       clock-frequency = <1500000000>;
+                       power-domains = <&sysc R8A7743_PD_CA15_CPU1>;
+                       next-level-cache = <&L2_CA15>;
                };
 
                L2_CA15: cache-controller-0 {
@@ -48,6 +76,12 @@
                #size-cells = <2>;
                ranges;
 
+               apmu@e6152000 {
+                       compatible = "renesas,r8a7743-apmu", "renesas,apmu";
+                       reg = <0 0xe6152000 0 0x188>;
+                       cpus = <&cpu0 &cpu1>;
+               };
+
                gic: interrupt-controller@f1001000 {
                        compatible = "arm,gic-400";
                        #interrupt-cells = <3>;
@@ -314,6 +348,94 @@
                        dma-channels = <15>;
                };
 
+               /* The memory map in the User's Manual maps the cores to bus
+                *  numbers
+                */
+               i2c0: i2c@e6508000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "renesas,i2c-r8a7743",
+                                    "renesas,rcar-gen2-i2c";
+                       reg = <0 0xe6508000 0 0x40>;
+                       interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 931>;
+                       power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                       resets = <&cpg 931>;
+                       i2c-scl-internal-delay-ns = <6>;
+                       status = "disabled";
+               };
+
+               i2c1: i2c@e6518000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "renesas,i2c-r8a7743",
+                                    "renesas,rcar-gen2-i2c";
+                       reg = <0 0xe6518000 0 0x40>;
+                       interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 930>;
+                       power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                       resets = <&cpg 930>;
+                       i2c-scl-internal-delay-ns = <6>;
+                       status = "disabled";
+               };
+
+               i2c2: i2c@e6530000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "renesas,i2c-r8a7743",
+                                    "renesas,rcar-gen2-i2c";
+                       reg = <0 0xe6530000 0 0x40>;
+                       interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 929>;
+                       power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                       resets = <&cpg 929>;
+                       i2c-scl-internal-delay-ns = <6>;
+                       status = "disabled";
+               };
+
+               i2c3: i2c@e6540000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "renesas,i2c-r8a7743",
+                                    "renesas,rcar-gen2-i2c";
+                       reg = <0 0xe6540000 0 0x40>;
+                       interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 928>;
+                       power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                       resets = <&cpg 928>;
+                       i2c-scl-internal-delay-ns = <6>;
+                       status = "disabled";
+               };
+
+               i2c4: i2c@e6520000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "renesas,i2c-r8a7743",
+                                    "renesas,rcar-gen2-i2c";
+                       reg = <0 0xe6520000 0 0x40>;
+                       interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 927>;
+                       power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                       resets = <&cpg 927>;
+                       i2c-scl-internal-delay-ns = <6>;
+                       status = "disabled";
+               };
+
+               i2c5: i2c@e6528000 {
+                       /* doesn't need pinmux */
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "renesas,i2c-r8a7743",
+                                    "renesas,rcar-gen2-i2c";
+                       reg = <0 0xe6528000 0 0x40>;
+                       interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 925>;
+                       power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
+                       resets = <&cpg 925>;
+                       i2c-scl-internal-delay-ns = <110>;
+                       status = "disabled";
+               };
+
                scifa0: serial@e6c40000 {
                        compatible = "renesas,scifa-r8a7743",
                                     "renesas,rcar-gen2-scifa", "renesas,scifa";