Merge branch 'stable/for-linus-5.1' of git://git.kernel.org/pub/scm/linux/kernel...

[sfrench/cifs-2.6.git] / arch / arm / boot / dts / qcom-msm8660.dtsi

diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
index 1c1a863fa0c29fa966d390f8c06989215471a991..993107ed147682960c8ece764cc27140f0570b17 100644 (file)
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -138,6 +138,7 @@
                        #address-cells = <1>;
                        #size-cells = <1>;
                        ranges;
+                       status = "disabled";
 
                        syscon-tcsr = <&tcsr>;
 
@@ -145,7 +146,7 @@
                                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                                reg = <0x16540000 0x1000>,
                                      <0x16500000 0x1000>;
-                               interrupts = <GIC_SPI 156 IRQ_TYPE_NONE>;
+                               interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
                                clock-names = "core", "iface";
                                status = "disabled";
@@ -154,7 +155,7 @@
                        gsbi6_i2c: i2c@16580000 {
                                compatible = "qcom,i2c-qup-v1.1.1";
                                reg = <0x16580000 0x1000>;
-                               interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
+                               interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
                                clock-names = "core", "iface";
                                #address-cells = <1>;
@@ -172,6 +173,7 @@
                        #address-cells = <1>;
                        #size-cells = <1>;
                        ranges;
+                       status = "disabled";
 
                        syscon-tcsr = <&tcsr>;
 
@@ -179,7 +181,7 @@
                                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                                reg = <0x16640000 0x1000>,
                                      <0x16600000 0x1000>;
-                               interrupts = <GIC_SPI 158 IRQ_TYPE_NONE>;
+                               interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
                                clock-names = "core", "iface";
                                status = "disabled";
@@ -188,7 +190,7 @@
                        gsbi7_i2c: i2c@16680000 {
                                compatible = "qcom,i2c-qup-v1.1.1";
                                reg = <0x16680000 0x1000>;
-                               interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
+                               interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
                                clock-names = "core", "iface";
                                #address-cells = <1>;
@@ -212,7 +214,7 @@
                        gsbi8_i2c: i2c@19880000 {
                                compatible = "qcom,i2c-qup-v1.1.1";
                                reg = <0x19880000 0x1000>;
-                               interrupts = <GIC_SPI 161 IRQ_TYPE_NONE>;
+                               interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>;
                                clock-names = "core", "iface";
                                #address-cells = <1>;
@@ -237,7 +239,7 @@
                                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                                reg = <0x19c40000 0x1000>,
                                      <0x19c00000 0x1000>;
-                               interrupts = <0 195 IRQ_TYPE_NONE>;
+                               interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
                                clock-names = "core", "iface";
                                status = "disabled";
@@ -246,7 +248,7 @@
                        gsbi12_i2c: i2c@19c80000 {
                                compatible = "qcom,i2c-qup-v1.1.1";
                                reg = <0x19c80000 0x1000>;
-                               interrupts = <0 196 IRQ_TYPE_NONE>;
+                               interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
                                clock-names = "core", "iface";
                                #address-cells = <1>;