Merge tag 'v4.18-next-dts32' of https://git.kernel.org/pub/scm/linux/kernel/git/matth...

[sfrench/cifs-2.6.git] / arch / arm / boot / dts / imx6dl.dtsi

diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 558bce81209d2dd26cb218cee80186be6117086f..f0607eb41df42ae00cb517878c347f50f37b9640 100644 (file)
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -1,12 +1,6 @@
-
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright 2013 Freescale Semiconductor, Inc.
 
 #include <dt-bindings/interrupt-controller/irq.h>
 #include "imx6dl-pinfunc.h"
@@ -39,6 +33,7 @@
                                396000  1175000
                        >;
                        clock-latency = <61036>; /* two CLK32 periods */
+                       #cooling-cells = <2>;
                        clocks = <&clks IMX6QDL_CLK_ARM>,
                                 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
                                 <&clks IMX6QDL_CLK_STEP>,
@@ -56,6 +51,29 @@
                        device_type = "cpu";
                        reg = <1>;
                        next-level-cache = <&L2>;
+                       operating-points = <
+                               /* kHz    uV */
+                               996000  1250000
+                               792000  1175000
+                               396000  1150000
+                       >;
+                       fsl,soc-operating-points = <
+                               /* ARM kHz  SOC-PU uV */
+                               996000  1175000
+                               792000  1175000
+                               396000  1175000
+                       >;
+                       clock-latency = <61036>; /* two CLK32 periods */
+                       clocks = <&clks IMX6QDL_CLK_ARM>,
+                                <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+                                <&clks IMX6QDL_CLK_STEP>,
+                                <&clks IMX6QDL_CLK_PLL1_SW>,
+                                <&clks IMX6QDL_CLK_PLL1_SYS>;
+                       clock-names = "arm", "pll2_pfd2_396m", "step",
+                                     "pll1_sw", "pll1_sys";
+                       arm-supply = <&reg_arm>;
+                       pu-supply = <&reg_pu>;
+                       soc-supply = <&reg_soc>;
                };
        };