-/* Analog control register access bits */
-#define ADDA_PR 0x0 /* PRCM base + 0x1c0 */
-#define ADDA_PR_RESET BIT(28)
-#define ADDA_PR_WRITE BIT(24)
-#define ADDA_PR_ADDR_SHIFT 16
-#define ADDA_PR_ADDR_MASK GENMASK(4, 0)
-#define ADDA_PR_DATA_IN_SHIFT 8
-#define ADDA_PR_DATA_IN_MASK GENMASK(7, 0)
-#define ADDA_PR_DATA_OUT_SHIFT 0
-#define ADDA_PR_DATA_OUT_MASK GENMASK(7, 0)
-
-/* regmap access bits */
-static int adda_reg_read(void *context, unsigned int reg, unsigned int *val)
-{
- void __iomem *base = (void __iomem *)context;
- u32 tmp;
-
- /* De-assert reset */
- writel(readl(base) | ADDA_PR_RESET, base);
-
- /* Clear write bit */
- writel(readl(base) & ~ADDA_PR_WRITE, base);
-
- /* Set register address */
- tmp = readl(base);
- tmp &= ~(ADDA_PR_ADDR_MASK << ADDA_PR_ADDR_SHIFT);
- tmp |= (reg & ADDA_PR_ADDR_MASK) << ADDA_PR_ADDR_SHIFT;
- writel(tmp, base);
-
- /* Read back value */
- *val = readl(base) & ADDA_PR_DATA_OUT_MASK;
-
- return 0;
-}
-
-static int adda_reg_write(void *context, unsigned int reg, unsigned int val)
-{
- void __iomem *base = (void __iomem *)context;
- u32 tmp;
-
- /* De-assert reset */
- writel(readl(base) | ADDA_PR_RESET, base);
-
- /* Set register address */
- tmp = readl(base);
- tmp &= ~(ADDA_PR_ADDR_MASK << ADDA_PR_ADDR_SHIFT);
- tmp |= (reg & ADDA_PR_ADDR_MASK) << ADDA_PR_ADDR_SHIFT;
- writel(tmp, base);
-
- /* Set data to write */
- tmp = readl(base);
- tmp &= ~(ADDA_PR_DATA_IN_MASK << ADDA_PR_DATA_IN_SHIFT);
- tmp |= (val & ADDA_PR_DATA_IN_MASK) << ADDA_PR_DATA_IN_SHIFT;
- writel(tmp, base);
-
- /* Set write bit to signal a write */
- writel(readl(base) | ADDA_PR_WRITE, base);
-
- /* Clear write bit */
- writel(readl(base) & ~ADDA_PR_WRITE, base);
-
- return 0;
-}
-
-static const struct regmap_config adda_pr_regmap_cfg = {
- .name = "adda-pr",
- .reg_bits = 5,
- .reg_stride = 1,
- .val_bits = 8,
- .reg_read = adda_reg_read,
- .reg_write = adda_reg_write,
- .fast_io = true,
- .max_register = 24,
-};
-