1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright(c) 2021 Intel Corporation. All rights reserved.
4 #include <linux/platform_device.h>
5 #include <linux/genalloc.h>
6 #include <linux/module.h>
7 #include <linux/mutex.h>
8 #include <linux/acpi.h>
13 #include "../watermark.h"
16 static int interleave_arithmetic;
18 #define NR_CXL_HOST_BRIDGES 2
19 #define NR_CXL_SINGLE_HOST 1
21 #define NR_CXL_ROOT_PORTS 2
22 #define NR_CXL_SWITCH_PORTS 2
23 #define NR_CXL_PORT_DECODERS 8
24 #define NR_BRIDGES (NR_CXL_HOST_BRIDGES + NR_CXL_SINGLE_HOST + NR_CXL_RCH)
26 static struct platform_device *cxl_acpi;
27 static struct platform_device *cxl_host_bridge[NR_CXL_HOST_BRIDGES];
28 #define NR_MULTI_ROOT (NR_CXL_HOST_BRIDGES * NR_CXL_ROOT_PORTS)
29 static struct platform_device *cxl_root_port[NR_MULTI_ROOT];
30 static struct platform_device *cxl_switch_uport[NR_MULTI_ROOT];
31 #define NR_MEM_MULTI \
32 (NR_CXL_HOST_BRIDGES * NR_CXL_ROOT_PORTS * NR_CXL_SWITCH_PORTS)
33 static struct platform_device *cxl_switch_dport[NR_MEM_MULTI];
35 static struct platform_device *cxl_hb_single[NR_CXL_SINGLE_HOST];
36 static struct platform_device *cxl_root_single[NR_CXL_SINGLE_HOST];
37 static struct platform_device *cxl_swu_single[NR_CXL_SINGLE_HOST];
38 #define NR_MEM_SINGLE (NR_CXL_SINGLE_HOST * NR_CXL_SWITCH_PORTS)
39 static struct platform_device *cxl_swd_single[NR_MEM_SINGLE];
41 struct platform_device *cxl_mem[NR_MEM_MULTI];
42 struct platform_device *cxl_mem_single[NR_MEM_SINGLE];
44 static struct platform_device *cxl_rch[NR_CXL_RCH];
45 static struct platform_device *cxl_rcd[NR_CXL_RCH];
47 static inline bool is_multi_bridge(struct device *dev)
51 for (i = 0; i < ARRAY_SIZE(cxl_host_bridge); i++)
52 if (&cxl_host_bridge[i]->dev == dev)
57 static inline bool is_single_bridge(struct device *dev)
61 for (i = 0; i < ARRAY_SIZE(cxl_hb_single); i++)
62 if (&cxl_hb_single[i]->dev == dev)
67 static struct acpi_device acpi0017_mock;
68 static struct acpi_device host_bridge[NR_BRIDGES] = {
70 .handle = &host_bridge[0],
73 .handle = &host_bridge[1],
76 .handle = &host_bridge[2],
79 .handle = &host_bridge[3],
83 static bool is_mock_dev(struct device *dev)
87 for (i = 0; i < ARRAY_SIZE(cxl_mem); i++)
88 if (dev == &cxl_mem[i]->dev)
90 for (i = 0; i < ARRAY_SIZE(cxl_mem_single); i++)
91 if (dev == &cxl_mem_single[i]->dev)
93 for (i = 0; i < ARRAY_SIZE(cxl_rcd); i++)
94 if (dev == &cxl_rcd[i]->dev)
96 if (dev == &cxl_acpi->dev)
101 static bool is_mock_adev(struct acpi_device *adev)
105 if (adev == &acpi0017_mock)
108 for (i = 0; i < ARRAY_SIZE(host_bridge); i++)
109 if (adev == &host_bridge[i])
116 struct acpi_table_cedt cedt;
117 struct acpi_cedt_chbs chbs[NR_BRIDGES];
119 struct acpi_cedt_cfmws cfmws;
123 struct acpi_cedt_cfmws cfmws;
127 struct acpi_cedt_cfmws cfmws;
131 struct acpi_cedt_cfmws cfmws;
135 struct acpi_cedt_cfmws cfmws;
139 struct acpi_cedt_cfmws cfmws;
143 struct acpi_cedt_cfmws cfmws;
147 struct acpi_cedt_cfmws cfmws;
151 struct acpi_cedt_cfmws cfmws;
155 struct acpi_cedt_cxims cxims;
158 } __packed mock_cedt = {
162 .length = sizeof(mock_cedt),
168 .type = ACPI_CEDT_TYPE_CHBS,
169 .length = sizeof(mock_cedt.chbs[0]),
172 .cxl_version = ACPI_CEDT_CHBS_VERSION_CXL20,
176 .type = ACPI_CEDT_TYPE_CHBS,
177 .length = sizeof(mock_cedt.chbs[0]),
180 .cxl_version = ACPI_CEDT_CHBS_VERSION_CXL20,
184 .type = ACPI_CEDT_TYPE_CHBS,
185 .length = sizeof(mock_cedt.chbs[0]),
188 .cxl_version = ACPI_CEDT_CHBS_VERSION_CXL20,
192 .type = ACPI_CEDT_TYPE_CHBS,
193 .length = sizeof(mock_cedt.chbs[0]),
196 .cxl_version = ACPI_CEDT_CHBS_VERSION_CXL11,
201 .type = ACPI_CEDT_TYPE_CFMWS,
202 .length = sizeof(mock_cedt.cfmws0),
204 .interleave_ways = 0,
206 .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
207 ACPI_CEDT_CFMWS_RESTRICT_VOLATILE,
209 .window_size = SZ_256M * 4UL,
216 .type = ACPI_CEDT_TYPE_CFMWS,
217 .length = sizeof(mock_cedt.cfmws1),
219 .interleave_ways = 1,
221 .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
222 ACPI_CEDT_CFMWS_RESTRICT_VOLATILE,
224 .window_size = SZ_256M * 8UL,
231 .type = ACPI_CEDT_TYPE_CFMWS,
232 .length = sizeof(mock_cedt.cfmws2),
234 .interleave_ways = 0,
236 .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
237 ACPI_CEDT_CFMWS_RESTRICT_PMEM,
239 .window_size = SZ_256M * 4UL,
246 .type = ACPI_CEDT_TYPE_CFMWS,
247 .length = sizeof(mock_cedt.cfmws3),
249 .interleave_ways = 1,
251 .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
252 ACPI_CEDT_CFMWS_RESTRICT_PMEM,
254 .window_size = SZ_256M * 8UL,
261 .type = ACPI_CEDT_TYPE_CFMWS,
262 .length = sizeof(mock_cedt.cfmws4),
264 .interleave_ways = 0,
266 .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
267 ACPI_CEDT_CFMWS_RESTRICT_PMEM,
269 .window_size = SZ_256M * 4UL,
276 .type = ACPI_CEDT_TYPE_CFMWS,
277 .length = sizeof(mock_cedt.cfmws5),
279 .interleave_ways = 0,
281 .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
282 ACPI_CEDT_CFMWS_RESTRICT_VOLATILE,
284 .window_size = SZ_256M,
288 /* .cfmws6,7,8 use ACPI_CEDT_CFMWS_ARITHMETIC_XOR */
292 .type = ACPI_CEDT_TYPE_CFMWS,
293 .length = sizeof(mock_cedt.cfmws6),
295 .interleave_arithmetic = ACPI_CEDT_CFMWS_ARITHMETIC_XOR,
296 .interleave_ways = 0,
298 .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
299 ACPI_CEDT_CFMWS_RESTRICT_PMEM,
301 .window_size = SZ_256M * 8UL,
308 .type = ACPI_CEDT_TYPE_CFMWS,
309 .length = sizeof(mock_cedt.cfmws7),
311 .interleave_arithmetic = ACPI_CEDT_CFMWS_ARITHMETIC_XOR,
312 .interleave_ways = 1,
314 .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
315 ACPI_CEDT_CFMWS_RESTRICT_PMEM,
317 .window_size = SZ_256M * 8UL,
324 .type = ACPI_CEDT_TYPE_CFMWS,
325 .length = sizeof(mock_cedt.cfmws8),
327 .interleave_arithmetic = ACPI_CEDT_CFMWS_ARITHMETIC_XOR,
328 .interleave_ways = 2,
330 .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
331 ACPI_CEDT_CFMWS_RESTRICT_PMEM,
333 .window_size = SZ_256M * 16UL,
335 .target = { 0, 1, 0, 1, },
340 .type = ACPI_CEDT_TYPE_CXIMS,
341 .length = sizeof(mock_cedt.cxims0),
346 .xormap_list = { 0x404100, 0x808200, },
350 struct acpi_cedt_cfmws *mock_cfmws[] = {
351 [0] = &mock_cedt.cfmws0.cfmws,
352 [1] = &mock_cedt.cfmws1.cfmws,
353 [2] = &mock_cedt.cfmws2.cfmws,
354 [3] = &mock_cedt.cfmws3.cfmws,
355 [4] = &mock_cedt.cfmws4.cfmws,
356 [5] = &mock_cedt.cfmws5.cfmws,
357 /* Modulo Math above, XOR Math below */
358 [6] = &mock_cedt.cfmws6.cfmws,
359 [7] = &mock_cedt.cfmws7.cfmws,
360 [8] = &mock_cedt.cfmws8.cfmws,
363 static int cfmws_start;
364 static int cfmws_end;
365 #define CFMWS_MOD_ARRAY_START 0
366 #define CFMWS_MOD_ARRAY_END 5
367 #define CFMWS_XOR_ARRAY_START 6
368 #define CFMWS_XOR_ARRAY_END 8
370 struct acpi_cedt_cxims *mock_cxims[1] = {
371 [0] = &mock_cedt.cxims0.cxims,
374 struct cxl_mock_res {
375 struct list_head list;
379 static LIST_HEAD(mock_res);
380 static DEFINE_MUTEX(mock_res_lock);
381 static struct gen_pool *cxl_mock_pool;
383 static void depopulate_all_mock_resources(void)
385 struct cxl_mock_res *res, *_res;
387 mutex_lock(&mock_res_lock);
388 list_for_each_entry_safe(res, _res, &mock_res, list) {
389 gen_pool_free(cxl_mock_pool, res->range.start,
390 range_len(&res->range));
391 list_del(&res->list);
394 mutex_unlock(&mock_res_lock);
397 static struct cxl_mock_res *alloc_mock_res(resource_size_t size, int align)
399 struct cxl_mock_res *res = kzalloc(sizeof(*res), GFP_KERNEL);
400 struct genpool_data_align data = {
405 INIT_LIST_HEAD(&res->list);
406 phys = gen_pool_alloc_algo(cxl_mock_pool, size,
407 gen_pool_first_fit_align, &data);
411 res->range = (struct range) {
413 .end = phys + size - 1,
415 mutex_lock(&mock_res_lock);
416 list_add(&res->list, &mock_res);
417 mutex_unlock(&mock_res_lock);
422 static int populate_cedt(void)
424 struct cxl_mock_res *res;
427 for (i = 0; i < ARRAY_SIZE(mock_cedt.chbs); i++) {
428 struct acpi_cedt_chbs *chbs = &mock_cedt.chbs[i];
429 resource_size_t size;
431 if (chbs->cxl_version == ACPI_CEDT_CHBS_VERSION_CXL20)
432 size = ACPI_CEDT_CHBS_LENGTH_CXL20;
434 size = ACPI_CEDT_CHBS_LENGTH_CXL11;
436 res = alloc_mock_res(size, size);
439 chbs->base = res->range.start;
443 for (i = cfmws_start; i <= cfmws_end; i++) {
444 struct acpi_cedt_cfmws *window = mock_cfmws[i];
446 res = alloc_mock_res(window->window_size, SZ_256M);
449 window->base_hpa = res->range.start;
455 static bool is_mock_port(struct device *dev);
458 * WARNING, this hack assumes the format of 'struct cxl_cfmws_context'
459 * and 'struct cxl_chbs_context' share the property that the first
460 * struct member is a cxl_test device being probed by the cxl_acpi
463 struct cxl_cedt_context {
467 static int mock_acpi_table_parse_cedt(enum acpi_cedt_type id,
468 acpi_tbl_entry_handler_arg handler_arg,
471 struct cxl_cedt_context *ctx = arg;
472 struct device *dev = ctx->dev;
473 union acpi_subtable_headers *h;
477 if (!is_mock_port(dev) && !is_mock_dev(dev))
478 return acpi_table_parse_cedt(id, handler_arg, arg);
480 if (id == ACPI_CEDT_TYPE_CHBS)
481 for (i = 0; i < ARRAY_SIZE(mock_cedt.chbs); i++) {
482 h = (union acpi_subtable_headers *)&mock_cedt.chbs[i];
483 end = (unsigned long)&mock_cedt.chbs[i + 1];
484 handler_arg(h, arg, end);
487 if (id == ACPI_CEDT_TYPE_CFMWS)
488 for (i = cfmws_start; i <= cfmws_end; i++) {
489 h = (union acpi_subtable_headers *) mock_cfmws[i];
490 end = (unsigned long) h + mock_cfmws[i]->header.length;
491 handler_arg(h, arg, end);
494 if (id == ACPI_CEDT_TYPE_CXIMS)
495 for (i = 0; i < ARRAY_SIZE(mock_cxims); i++) {
496 h = (union acpi_subtable_headers *)mock_cxims[i];
497 end = (unsigned long)h + mock_cxims[i]->header.length;
498 handler_arg(h, arg, end);
504 static bool is_mock_bridge(struct device *dev)
508 for (i = 0; i < ARRAY_SIZE(cxl_host_bridge); i++)
509 if (dev == &cxl_host_bridge[i]->dev)
511 for (i = 0; i < ARRAY_SIZE(cxl_hb_single); i++)
512 if (dev == &cxl_hb_single[i]->dev)
514 for (i = 0; i < ARRAY_SIZE(cxl_rch); i++)
515 if (dev == &cxl_rch[i]->dev)
521 static bool is_mock_port(struct device *dev)
525 if (is_mock_bridge(dev))
528 for (i = 0; i < ARRAY_SIZE(cxl_root_port); i++)
529 if (dev == &cxl_root_port[i]->dev)
532 for (i = 0; i < ARRAY_SIZE(cxl_switch_uport); i++)
533 if (dev == &cxl_switch_uport[i]->dev)
536 for (i = 0; i < ARRAY_SIZE(cxl_switch_dport); i++)
537 if (dev == &cxl_switch_dport[i]->dev)
540 for (i = 0; i < ARRAY_SIZE(cxl_root_single); i++)
541 if (dev == &cxl_root_single[i]->dev)
544 for (i = 0; i < ARRAY_SIZE(cxl_swu_single); i++)
545 if (dev == &cxl_swu_single[i]->dev)
548 for (i = 0; i < ARRAY_SIZE(cxl_swd_single); i++)
549 if (dev == &cxl_swd_single[i]->dev)
552 if (is_cxl_memdev(dev))
553 return is_mock_dev(dev->parent);
558 static int host_bridge_index(struct acpi_device *adev)
560 return adev - host_bridge;
563 static struct acpi_device *find_host_bridge(acpi_handle handle)
567 for (i = 0; i < ARRAY_SIZE(host_bridge); i++)
568 if (handle == host_bridge[i].handle)
569 return &host_bridge[i];
574 mock_acpi_evaluate_integer(acpi_handle handle, acpi_string pathname,
575 struct acpi_object_list *arguments,
576 unsigned long long *data)
578 struct acpi_device *adev = find_host_bridge(handle);
580 if (!adev || strcmp(pathname, METHOD_NAME__UID) != 0)
581 return acpi_evaluate_integer(handle, pathname, arguments, data);
583 *data = host_bridge_index(adev);
587 static struct pci_bus mock_pci_bus[NR_BRIDGES];
588 static struct acpi_pci_root mock_pci_root[ARRAY_SIZE(mock_pci_bus)] = {
590 .bus = &mock_pci_bus[0],
593 .bus = &mock_pci_bus[1],
596 .bus = &mock_pci_bus[2],
599 .bus = &mock_pci_bus[3],
604 static bool is_mock_bus(struct pci_bus *bus)
608 for (i = 0; i < ARRAY_SIZE(mock_pci_bus); i++)
609 if (bus == &mock_pci_bus[i])
614 static struct acpi_pci_root *mock_acpi_pci_find_root(acpi_handle handle)
616 struct acpi_device *adev = find_host_bridge(handle);
619 return acpi_pci_find_root(handle);
620 return &mock_pci_root[host_bridge_index(adev)];
623 static struct cxl_hdm *mock_cxl_setup_hdm(struct cxl_port *port,
624 struct cxl_endpoint_dvsec_info *info)
626 struct cxl_hdm *cxlhdm = devm_kzalloc(&port->dev, sizeof(*cxlhdm), GFP_KERNEL);
629 return ERR_PTR(-ENOMEM);
635 static int mock_cxl_add_passthrough_decoder(struct cxl_port *port)
637 dev_err(&port->dev, "unexpected passthrough decoder for cxl_test\n");
642 struct target_map_ctx {
648 static int map_targets(struct device *dev, void *data)
650 struct platform_device *pdev = to_platform_device(dev);
651 struct target_map_ctx *ctx = data;
653 ctx->target_map[ctx->index++] = pdev->id;
655 if (ctx->index > ctx->target_count) {
656 dev_WARN_ONCE(dev, 1, "too many targets found?\n");
663 static int mock_decoder_commit(struct cxl_decoder *cxld)
665 struct cxl_port *port = to_cxl_port(cxld->dev.parent);
668 if (cxld->flags & CXL_DECODER_F_ENABLE)
671 dev_dbg(&port->dev, "%s commit\n", dev_name(&cxld->dev));
672 if (cxl_num_decoders_committed(port) != id) {
674 "%s: out of order commit, expected decoder%d.%d\n",
675 dev_name(&cxld->dev), port->id,
676 cxl_num_decoders_committed(port));
681 cxld->flags |= CXL_DECODER_F_ENABLE;
686 static int mock_decoder_reset(struct cxl_decoder *cxld)
688 struct cxl_port *port = to_cxl_port(cxld->dev.parent);
691 if ((cxld->flags & CXL_DECODER_F_ENABLE) == 0)
694 dev_dbg(&port->dev, "%s reset\n", dev_name(&cxld->dev));
695 if (port->commit_end != id) {
697 "%s: out of order reset, expected decoder%d.%d\n",
698 dev_name(&cxld->dev), port->id, port->commit_end);
703 cxld->flags &= ~CXL_DECODER_F_ENABLE;
708 static void default_mock_decoder(struct cxl_decoder *cxld)
710 cxld->hpa_range = (struct range){
715 cxld->interleave_ways = 1;
716 cxld->interleave_granularity = 256;
717 cxld->target_type = CXL_DECODER_HOSTONLYMEM;
718 cxld->commit = mock_decoder_commit;
719 cxld->reset = mock_decoder_reset;
722 static int first_decoder(struct device *dev, void *data)
724 struct cxl_decoder *cxld;
726 if (!is_switch_decoder(dev))
728 cxld = to_cxl_decoder(dev);
734 static void mock_init_hdm_decoder(struct cxl_decoder *cxld)
736 struct acpi_cedt_cfmws *window = mock_cfmws[0];
737 struct platform_device *pdev = NULL;
738 struct cxl_endpoint_decoder *cxled;
739 struct cxl_switch_decoder *cxlsd;
740 struct cxl_port *port, *iter;
741 const int size = SZ_512M;
742 struct cxl_memdev *cxlmd;
743 struct cxl_dport *dport;
749 if (is_endpoint_decoder(&cxld->dev)) {
750 cxled = to_cxl_endpoint_decoder(&cxld->dev);
751 cxlmd = cxled_to_memdev(cxled);
752 WARN_ON(!dev_is_platform(cxlmd->dev.parent));
753 pdev = to_platform_device(cxlmd->dev.parent);
755 /* check is endpoint is attach to host-bridge0 */
756 port = cxled_to_port(cxled);
758 if (port->uport_dev == &cxl_host_bridge[0]->dev) {
762 if (is_cxl_port(port->dev.parent))
763 port = to_cxl_port(port->dev.parent);
767 port = cxled_to_port(cxled);
771 * The first decoder on the first 2 devices on the first switch
772 * attached to host-bridge0 mock a fake / static RAM region. All
773 * other decoders are default disabled. Given the round robin
774 * assignment those devices are named cxl_mem.0, and cxl_mem.4.
776 * See 'cxl list -BMPu -m cxl_mem.0,cxl_mem.4'
778 if (!hb0 || pdev->id % 4 || pdev->id > 4 || cxld->id > 0) {
779 default_mock_decoder(cxld);
783 base = window->base_hpa;
784 cxld->hpa_range = (struct range) {
786 .end = base + size - 1,
789 cxld->interleave_ways = 2;
790 eig_to_granularity(window->granularity, &cxld->interleave_granularity);
791 cxld->target_type = CXL_DECODER_HOSTONLYMEM;
792 cxld->flags = CXL_DECODER_F_ENABLE;
793 cxled->state = CXL_DECODER_STATE_AUTO;
794 port->commit_end = cxld->id;
795 devm_cxl_dpa_reserve(cxled, 0, size / cxld->interleave_ways, 0);
796 cxld->commit = mock_decoder_commit;
797 cxld->reset = mock_decoder_reset;
800 * Now that endpoint decoder is set up, walk up the hierarchy
801 * and setup the switch and root port decoders targeting @cxlmd.
804 for (i = 0; i < 2; i++) {
805 dport = iter->parent_dport;
807 dev = device_find_child(&iter->dev, NULL, first_decoder);
809 * Ancestor ports are guaranteed to be enumerated before
810 * @port, and all ports have at least one decoder.
814 cxlsd = to_cxl_switch_decoder(dev);
816 /* put cxl_mem.4 second in the decode order */
818 cxlsd->target[1] = dport;
820 cxlsd->target[0] = dport;
822 cxlsd->target[0] = dport;
824 cxld->target_type = CXL_DECODER_HOSTONLYMEM;
825 cxld->flags = CXL_DECODER_F_ENABLE;
826 iter->commit_end = 0;
828 * Switch targets 2 endpoints, while host bridge targets
832 cxld->interleave_ways = 2;
834 cxld->interleave_ways = 1;
835 cxld->interleave_granularity = 4096;
836 cxld->hpa_range = (struct range) {
838 .end = base + size - 1,
844 static int mock_cxl_enumerate_decoders(struct cxl_hdm *cxlhdm,
845 struct cxl_endpoint_dvsec_info *info)
847 struct cxl_port *port = cxlhdm->port;
848 struct cxl_port *parent_port = to_cxl_port(port->dev.parent);
851 if (is_cxl_endpoint(port))
853 else if (is_cxl_root(parent_port))
854 target_count = NR_CXL_ROOT_PORTS;
856 target_count = NR_CXL_SWITCH_PORTS;
858 for (i = 0; i < NR_CXL_PORT_DECODERS; i++) {
859 int target_map[CXL_DECODER_MAX_INTERLEAVE] = { 0 };
860 struct target_map_ctx ctx = {
861 .target_map = target_map,
862 .target_count = target_count,
864 struct cxl_decoder *cxld;
868 struct cxl_switch_decoder *cxlsd;
870 cxlsd = cxl_switch_decoder_alloc(port, target_count);
873 "Failed to allocate the decoder\n");
874 return PTR_ERR(cxlsd);
878 struct cxl_endpoint_decoder *cxled;
880 cxled = cxl_endpoint_decoder_alloc(port);
884 "Failed to allocate the decoder\n");
885 return PTR_ERR(cxled);
890 mock_init_hdm_decoder(cxld);
893 rc = device_for_each_child(port->uport_dev, &ctx,
896 put_device(&cxld->dev);
901 rc = cxl_decoder_add_locked(cxld, target_map);
903 put_device(&cxld->dev);
904 dev_err(&port->dev, "Failed to add decoder\n");
908 rc = cxl_decoder_autoremove(&port->dev, cxld);
911 dev_dbg(&cxld->dev, "Added to port %s\n", dev_name(&port->dev));
917 static int mock_cxl_port_enumerate_dports(struct cxl_port *port)
919 struct platform_device **array;
922 if (port->depth == 1) {
923 if (is_multi_bridge(port->uport_dev)) {
924 array_size = ARRAY_SIZE(cxl_root_port);
925 array = cxl_root_port;
926 } else if (is_single_bridge(port->uport_dev)) {
927 array_size = ARRAY_SIZE(cxl_root_single);
928 array = cxl_root_single;
930 dev_dbg(&port->dev, "%s: unknown bridge type\n",
931 dev_name(port->uport_dev));
934 } else if (port->depth == 2) {
935 struct cxl_port *parent = to_cxl_port(port->dev.parent);
937 if (is_multi_bridge(parent->uport_dev)) {
938 array_size = ARRAY_SIZE(cxl_switch_dport);
939 array = cxl_switch_dport;
940 } else if (is_single_bridge(parent->uport_dev)) {
941 array_size = ARRAY_SIZE(cxl_swd_single);
942 array = cxl_swd_single;
944 dev_dbg(&port->dev, "%s: unknown bridge type\n",
945 dev_name(port->uport_dev));
949 dev_WARN_ONCE(&port->dev, 1, "unexpected depth %d\n",
954 for (i = 0; i < array_size; i++) {
955 struct platform_device *pdev = array[i];
956 struct cxl_dport *dport;
958 if (pdev->dev.parent != port->uport_dev) {
959 dev_dbg(&port->dev, "%s: mismatch parent %s\n",
960 dev_name(port->uport_dev),
961 dev_name(pdev->dev.parent));
965 dport = devm_cxl_add_dport(port, &pdev->dev, pdev->id,
969 return PTR_ERR(dport);
975 static struct cxl_mock_ops cxl_mock_ops = {
976 .is_mock_adev = is_mock_adev,
977 .is_mock_bridge = is_mock_bridge,
978 .is_mock_bus = is_mock_bus,
979 .is_mock_port = is_mock_port,
980 .is_mock_dev = is_mock_dev,
981 .acpi_table_parse_cedt = mock_acpi_table_parse_cedt,
982 .acpi_evaluate_integer = mock_acpi_evaluate_integer,
983 .acpi_pci_find_root = mock_acpi_pci_find_root,
984 .devm_cxl_port_enumerate_dports = mock_cxl_port_enumerate_dports,
985 .devm_cxl_setup_hdm = mock_cxl_setup_hdm,
986 .devm_cxl_add_passthrough_decoder = mock_cxl_add_passthrough_decoder,
987 .devm_cxl_enumerate_decoders = mock_cxl_enumerate_decoders,
988 .list = LIST_HEAD_INIT(cxl_mock_ops.list),
991 static void mock_companion(struct acpi_device *adev, struct device *dev)
993 device_initialize(&adev->dev);
994 fwnode_init(&adev->fwnode, NULL);
995 dev->fwnode = &adev->fwnode;
996 adev->fwnode.dev = dev;
1000 #define SZ_64G (SZ_32G * 2)
1003 static __init int cxl_rch_init(void)
1007 for (i = 0; i < ARRAY_SIZE(cxl_rch); i++) {
1008 int idx = NR_CXL_HOST_BRIDGES + NR_CXL_SINGLE_HOST + i;
1009 struct acpi_device *adev = &host_bridge[idx];
1010 struct platform_device *pdev;
1012 pdev = platform_device_alloc("cxl_host_bridge", idx);
1016 mock_companion(adev, &pdev->dev);
1017 rc = platform_device_add(pdev);
1019 platform_device_put(pdev);
1024 mock_pci_bus[idx].bridge = &pdev->dev;
1025 rc = sysfs_create_link(&pdev->dev.kobj, &pdev->dev.kobj,
1031 for (i = 0; i < ARRAY_SIZE(cxl_rcd); i++) {
1032 int idx = NR_MEM_MULTI + NR_MEM_SINGLE + i;
1033 struct platform_device *rch = cxl_rch[i];
1034 struct platform_device *pdev;
1036 pdev = platform_device_alloc("cxl_rcd", idx);
1039 pdev->dev.parent = &rch->dev;
1040 set_dev_node(&pdev->dev, i % 2);
1042 rc = platform_device_add(pdev);
1044 platform_device_put(pdev);
1053 for (i = ARRAY_SIZE(cxl_rcd) - 1; i >= 0; i--)
1054 platform_device_unregister(cxl_rcd[i]);
1056 for (i = ARRAY_SIZE(cxl_rch) - 1; i >= 0; i--) {
1057 struct platform_device *pdev = cxl_rch[i];
1061 sysfs_remove_link(&pdev->dev.kobj, "firmware_node");
1062 platform_device_unregister(cxl_rch[i]);
1068 static void cxl_rch_exit(void)
1072 for (i = ARRAY_SIZE(cxl_rcd) - 1; i >= 0; i--)
1073 platform_device_unregister(cxl_rcd[i]);
1074 for (i = ARRAY_SIZE(cxl_rch) - 1; i >= 0; i--) {
1075 struct platform_device *pdev = cxl_rch[i];
1079 sysfs_remove_link(&pdev->dev.kobj, "firmware_node");
1080 platform_device_unregister(cxl_rch[i]);
1084 static __init int cxl_single_init(void)
1088 for (i = 0; i < ARRAY_SIZE(cxl_hb_single); i++) {
1089 struct acpi_device *adev =
1090 &host_bridge[NR_CXL_HOST_BRIDGES + i];
1091 struct platform_device *pdev;
1093 pdev = platform_device_alloc("cxl_host_bridge",
1094 NR_CXL_HOST_BRIDGES + i);
1098 mock_companion(adev, &pdev->dev);
1099 rc = platform_device_add(pdev);
1101 platform_device_put(pdev);
1105 cxl_hb_single[i] = pdev;
1106 mock_pci_bus[i + NR_CXL_HOST_BRIDGES].bridge = &pdev->dev;
1107 rc = sysfs_create_link(&pdev->dev.kobj, &pdev->dev.kobj,
1113 for (i = 0; i < ARRAY_SIZE(cxl_root_single); i++) {
1114 struct platform_device *bridge =
1115 cxl_hb_single[i % ARRAY_SIZE(cxl_hb_single)];
1116 struct platform_device *pdev;
1118 pdev = platform_device_alloc("cxl_root_port",
1122 pdev->dev.parent = &bridge->dev;
1124 rc = platform_device_add(pdev);
1126 platform_device_put(pdev);
1129 cxl_root_single[i] = pdev;
1132 for (i = 0; i < ARRAY_SIZE(cxl_swu_single); i++) {
1133 struct platform_device *root_port = cxl_root_single[i];
1134 struct platform_device *pdev;
1136 pdev = platform_device_alloc("cxl_switch_uport",
1140 pdev->dev.parent = &root_port->dev;
1142 rc = platform_device_add(pdev);
1144 platform_device_put(pdev);
1147 cxl_swu_single[i] = pdev;
1150 for (i = 0; i < ARRAY_SIZE(cxl_swd_single); i++) {
1151 struct platform_device *uport =
1152 cxl_swu_single[i % ARRAY_SIZE(cxl_swu_single)];
1153 struct platform_device *pdev;
1155 pdev = platform_device_alloc("cxl_switch_dport",
1159 pdev->dev.parent = &uport->dev;
1161 rc = platform_device_add(pdev);
1163 platform_device_put(pdev);
1166 cxl_swd_single[i] = pdev;
1169 for (i = 0; i < ARRAY_SIZE(cxl_mem_single); i++) {
1170 struct platform_device *dport = cxl_swd_single[i];
1171 struct platform_device *pdev;
1173 pdev = platform_device_alloc("cxl_mem", NR_MEM_MULTI + i);
1176 pdev->dev.parent = &dport->dev;
1177 set_dev_node(&pdev->dev, i % 2);
1179 rc = platform_device_add(pdev);
1181 platform_device_put(pdev);
1184 cxl_mem_single[i] = pdev;
1190 for (i = ARRAY_SIZE(cxl_mem_single) - 1; i >= 0; i--)
1191 platform_device_unregister(cxl_mem_single[i]);
1193 for (i = ARRAY_SIZE(cxl_swd_single) - 1; i >= 0; i--)
1194 platform_device_unregister(cxl_swd_single[i]);
1196 for (i = ARRAY_SIZE(cxl_swu_single) - 1; i >= 0; i--)
1197 platform_device_unregister(cxl_swu_single[i]);
1199 for (i = ARRAY_SIZE(cxl_root_single) - 1; i >= 0; i--)
1200 platform_device_unregister(cxl_root_single[i]);
1202 for (i = ARRAY_SIZE(cxl_hb_single) - 1; i >= 0; i--) {
1203 struct platform_device *pdev = cxl_hb_single[i];
1207 sysfs_remove_link(&pdev->dev.kobj, "physical_node");
1208 platform_device_unregister(cxl_hb_single[i]);
1214 static void cxl_single_exit(void)
1218 for (i = ARRAY_SIZE(cxl_mem_single) - 1; i >= 0; i--)
1219 platform_device_unregister(cxl_mem_single[i]);
1220 for (i = ARRAY_SIZE(cxl_swd_single) - 1; i >= 0; i--)
1221 platform_device_unregister(cxl_swd_single[i]);
1222 for (i = ARRAY_SIZE(cxl_swu_single) - 1; i >= 0; i--)
1223 platform_device_unregister(cxl_swu_single[i]);
1224 for (i = ARRAY_SIZE(cxl_root_single) - 1; i >= 0; i--)
1225 platform_device_unregister(cxl_root_single[i]);
1226 for (i = ARRAY_SIZE(cxl_hb_single) - 1; i >= 0; i--) {
1227 struct platform_device *pdev = cxl_hb_single[i];
1231 sysfs_remove_link(&pdev->dev.kobj, "physical_node");
1232 platform_device_unregister(cxl_hb_single[i]);
1236 static __init int cxl_test_init(void)
1246 register_cxl_mock_ops(&cxl_mock_ops);
1248 cxl_mock_pool = gen_pool_create(ilog2(SZ_2M), NUMA_NO_NODE);
1249 if (!cxl_mock_pool) {
1251 goto err_gen_pool_create;
1254 rc = gen_pool_add(cxl_mock_pool, iomem_resource.end + 1 - SZ_64G,
1255 SZ_64G, NUMA_NO_NODE);
1257 goto err_gen_pool_add;
1259 if (interleave_arithmetic == 1) {
1260 cfmws_start = CFMWS_XOR_ARRAY_START;
1261 cfmws_end = CFMWS_XOR_ARRAY_END;
1263 cfmws_start = CFMWS_MOD_ARRAY_START;
1264 cfmws_end = CFMWS_MOD_ARRAY_END;
1267 rc = populate_cedt();
1271 for (i = 0; i < ARRAY_SIZE(cxl_host_bridge); i++) {
1272 struct acpi_device *adev = &host_bridge[i];
1273 struct platform_device *pdev;
1275 pdev = platform_device_alloc("cxl_host_bridge", i);
1279 mock_companion(adev, &pdev->dev);
1280 rc = platform_device_add(pdev);
1282 platform_device_put(pdev);
1286 cxl_host_bridge[i] = pdev;
1287 mock_pci_bus[i].bridge = &pdev->dev;
1288 rc = sysfs_create_link(&pdev->dev.kobj, &pdev->dev.kobj,
1294 for (i = 0; i < ARRAY_SIZE(cxl_root_port); i++) {
1295 struct platform_device *bridge =
1296 cxl_host_bridge[i % ARRAY_SIZE(cxl_host_bridge)];
1297 struct platform_device *pdev;
1299 pdev = platform_device_alloc("cxl_root_port", i);
1302 pdev->dev.parent = &bridge->dev;
1304 rc = platform_device_add(pdev);
1306 platform_device_put(pdev);
1309 cxl_root_port[i] = pdev;
1312 BUILD_BUG_ON(ARRAY_SIZE(cxl_switch_uport) != ARRAY_SIZE(cxl_root_port));
1313 for (i = 0; i < ARRAY_SIZE(cxl_switch_uport); i++) {
1314 struct platform_device *root_port = cxl_root_port[i];
1315 struct platform_device *pdev;
1317 pdev = platform_device_alloc("cxl_switch_uport", i);
1320 pdev->dev.parent = &root_port->dev;
1322 rc = platform_device_add(pdev);
1324 platform_device_put(pdev);
1327 cxl_switch_uport[i] = pdev;
1330 for (i = 0; i < ARRAY_SIZE(cxl_switch_dport); i++) {
1331 struct platform_device *uport =
1332 cxl_switch_uport[i % ARRAY_SIZE(cxl_switch_uport)];
1333 struct platform_device *pdev;
1335 pdev = platform_device_alloc("cxl_switch_dport", i);
1338 pdev->dev.parent = &uport->dev;
1340 rc = platform_device_add(pdev);
1342 platform_device_put(pdev);
1345 cxl_switch_dport[i] = pdev;
1348 for (i = 0; i < ARRAY_SIZE(cxl_mem); i++) {
1349 struct platform_device *dport = cxl_switch_dport[i];
1350 struct platform_device *pdev;
1352 pdev = platform_device_alloc("cxl_mem", i);
1355 pdev->dev.parent = &dport->dev;
1356 set_dev_node(&pdev->dev, i % 2);
1358 rc = platform_device_add(pdev);
1360 platform_device_put(pdev);
1366 rc = cxl_single_init();
1370 rc = cxl_rch_init();
1374 cxl_acpi = platform_device_alloc("cxl_acpi", 0);
1378 mock_companion(&acpi0017_mock, &cxl_acpi->dev);
1379 acpi0017_mock.dev.bus = &platform_bus_type;
1381 rc = platform_device_add(cxl_acpi);
1388 platform_device_put(cxl_acpi);
1394 for (i = ARRAY_SIZE(cxl_mem) - 1; i >= 0; i--)
1395 platform_device_unregister(cxl_mem[i]);
1397 for (i = ARRAY_SIZE(cxl_switch_dport) - 1; i >= 0; i--)
1398 platform_device_unregister(cxl_switch_dport[i]);
1400 for (i = ARRAY_SIZE(cxl_switch_uport) - 1; i >= 0; i--)
1401 platform_device_unregister(cxl_switch_uport[i]);
1403 for (i = ARRAY_SIZE(cxl_root_port) - 1; i >= 0; i--)
1404 platform_device_unregister(cxl_root_port[i]);
1406 for (i = ARRAY_SIZE(cxl_host_bridge) - 1; i >= 0; i--) {
1407 struct platform_device *pdev = cxl_host_bridge[i];
1411 sysfs_remove_link(&pdev->dev.kobj, "physical_node");
1412 platform_device_unregister(cxl_host_bridge[i]);
1415 depopulate_all_mock_resources();
1417 gen_pool_destroy(cxl_mock_pool);
1418 err_gen_pool_create:
1419 unregister_cxl_mock_ops(&cxl_mock_ops);
1423 static __exit void cxl_test_exit(void)
1427 platform_device_unregister(cxl_acpi);
1430 for (i = ARRAY_SIZE(cxl_mem) - 1; i >= 0; i--)
1431 platform_device_unregister(cxl_mem[i]);
1432 for (i = ARRAY_SIZE(cxl_switch_dport) - 1; i >= 0; i--)
1433 platform_device_unregister(cxl_switch_dport[i]);
1434 for (i = ARRAY_SIZE(cxl_switch_uport) - 1; i >= 0; i--)
1435 platform_device_unregister(cxl_switch_uport[i]);
1436 for (i = ARRAY_SIZE(cxl_root_port) - 1; i >= 0; i--)
1437 platform_device_unregister(cxl_root_port[i]);
1438 for (i = ARRAY_SIZE(cxl_host_bridge) - 1; i >= 0; i--) {
1439 struct platform_device *pdev = cxl_host_bridge[i];
1443 sysfs_remove_link(&pdev->dev.kobj, "physical_node");
1444 platform_device_unregister(cxl_host_bridge[i]);
1446 depopulate_all_mock_resources();
1447 gen_pool_destroy(cxl_mock_pool);
1448 unregister_cxl_mock_ops(&cxl_mock_ops);
1451 module_param(interleave_arithmetic, int, 0444);
1452 MODULE_PARM_DESC(interleave_arithmetic, "Modulo:0, XOR:1");
1453 module_init(cxl_test_init);
1454 module_exit(cxl_test_exit);
1455 MODULE_LICENSE("GPL v2");
1456 MODULE_IMPORT_NS(ACPI);
1457 MODULE_IMPORT_NS(CXL);