tools/perf/pmu-events/arch/x86/skylake/memory.json

   1 [
   2     {
   3         "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.",
   4         "Counter": "0,1,2,3",
   5         "CounterHTOff": "0,1,2,3,4,5,6,7",
   6         "CounterMask": "2",
   7         "EventCode": "0xA3",
   8         "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS",
   9         "SampleAfterValue": "2000003",
  10         "UMask": "0x2"
  11     },
  12     {
  13         "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
  14         "Counter": "0,1,2,3",
  15         "CounterHTOff": "0,1,2,3,4,5,6,7",
  16         "CounterMask": "6",
  17         "EventCode": "0xA3",
  18         "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
  19         "SampleAfterValue": "2000003",
  20         "UMask": "0x6"
  21     },
  22     {
  23         "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).",
  24         "Counter": "0,1,2,3",
  25         "CounterHTOff": "0,1,2,3,4,5,6,7",
  26         "EventCode": "0xC8",
  27         "EventName": "HLE_RETIRED.ABORTED",
  28         "PEBS": "1",
  29         "PublicDescription": "Number of times HLE abort was triggered.",
  30         "SampleAfterValue": "2000003",
  31         "UMask": "0x4"
  32     },
  33     {
  34         "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).",
  35         "Counter": "0,1,2,3",
  36         "CounterHTOff": "0,1,2,3,4,5,6,7",
  37         "EventCode": "0xC8",
  38         "EventName": "HLE_RETIRED.ABORTED_EVENTS",
  39         "SampleAfterValue": "2000003",
  40         "UMask": "0x80"
  41     },
  42     {
  43         "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
  44         "Counter": "0,1,2,3",
  45         "CounterHTOff": "0,1,2,3,4,5,6,7",
  46         "EventCode": "0xC8",
  47         "EventName": "HLE_RETIRED.ABORTED_MEM",
  48         "SampleAfterValue": "2000003",
  49         "UMask": "0x8"
  50     },
  51     {
  52         "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
  53         "Counter": "0,1,2,3",
  54         "CounterHTOff": "0,1,2,3,4,5,6,7",
  55         "EventCode": "0xC8",
  56         "EventName": "HLE_RETIRED.ABORTED_MEMTYPE",
  57         "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.",
  58         "SampleAfterValue": "2000003",
  59         "UMask": "0x40"
  60     },
  61     {
  62         "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.",
  63         "Counter": "0,1,2,3",
  64         "CounterHTOff": "0,1,2,3,4,5,6,7",
  65         "EventCode": "0xC8",
  66         "EventName": "HLE_RETIRED.ABORTED_TIMER",
  67         "SampleAfterValue": "2000003",
  68         "UMask": "0x10"
  69     },
  70     {
  71         "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).",
  72         "Counter": "0,1,2,3",
  73         "CounterHTOff": "0,1,2,3,4,5,6,7",
  74         "EventCode": "0xC8",
  75         "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY",
  76         "SampleAfterValue": "2000003",
  77         "UMask": "0x20"
  78     },
  79     {
  80         "BriefDescription": "Number of times an HLE execution successfully committed",
  81         "Counter": "0,1,2,3",
  82         "CounterHTOff": "0,1,2,3,4,5,6,7",
  83         "EventCode": "0xC8",
  84         "EventName": "HLE_RETIRED.COMMIT",
  85         "PublicDescription": "Number of times HLE commit succeeded.",
  86         "SampleAfterValue": "2000003",
  87         "UMask": "0x2"
  88     },
  89     {
  90         "BriefDescription": "Number of times an HLE execution started.",
  91         "Counter": "0,1,2,3",
  92         "CounterHTOff": "0,1,2,3,4,5,6,7",
  93         "EventCode": "0xC8",
  94         "EventName": "HLE_RETIRED.START",
  95         "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.",
  96         "SampleAfterValue": "2000003",
  97         "UMask": "0x1"
  98     },
  99     {
 100         "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
 101         "Counter": "0,1,2,3",
 102         "CounterHTOff": "0,1,2,3,4,5,6,7",
 103         "Errata": "SKL089",
 104         "EventCode": "0xC3",
 105         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
 106         "PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.",
 107         "SampleAfterValue": "100003",
 108         "UMask": "0x2"
 109     },
 110     {
 111         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
 112         "Counter": "0,1,2,3",
 113         "CounterHTOff": "0,1,2,3",
 114         "Data_LA": "1",
 115         "EventCode": "0xcd",
 116         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
 117         "MSRIndex": "0x3F6",
 118         "MSRValue": "0x80",
 119         "PEBS": "2",
 120         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency.",
 121         "SampleAfterValue": "1009",
 122         "TakenAlone": "1",
 123         "UMask": "0x1"
 124     },
 125     {
 126         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
 127         "Counter": "0,1,2,3",
 128         "CounterHTOff": "0,1,2,3",
 129         "Data_LA": "1",
 130         "EventCode": "0xcd",
 131         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
 132         "MSRIndex": "0x3F6",
 133         "MSRValue": "0x10",
 134         "PEBS": "2",
 135         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency.",
 136         "SampleAfterValue": "20011",
 137         "TakenAlone": "1",
 138         "UMask": "0x1"
 139     },
 140     {
 141         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
 142         "Counter": "0,1,2,3",
 143         "CounterHTOff": "0,1,2,3",
 144         "Data_LA": "1",
 145         "EventCode": "0xcd",
 146         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
 147         "MSRIndex": "0x3F6",
 148         "MSRValue": "0x100",
 149         "PEBS": "2",
 150         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency.",
 151         "SampleAfterValue": "503",
 152         "TakenAlone": "1",
 153         "UMask": "0x1"
 154     },
 155     {
 156         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
 157         "Counter": "0,1,2,3",
 158         "CounterHTOff": "0,1,2,3",
 159         "Data_LA": "1",
 160         "EventCode": "0xcd",
 161         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
 162         "MSRIndex": "0x3F6",
 163         "MSRValue": "0x20",
 164         "PEBS": "2",
 165         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency.",
 166         "SampleAfterValue": "100007",
 167         "TakenAlone": "1",
 168         "UMask": "0x1"
 169     },
 170     {
 171         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
 172         "Counter": "0,1,2,3",
 173         "CounterHTOff": "0,1,2,3",
 174         "Data_LA": "1",
 175         "EventCode": "0xcd",
 176         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
 177         "MSRIndex": "0x3F6",
 178         "MSRValue": "0x4",
 179         "PEBS": "2",
 180         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency.",
 181         "SampleAfterValue": "100003",
 182         "TakenAlone": "1",
 183         "UMask": "0x1"
 184     },
 185     {
 186         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
 187         "Counter": "0,1,2,3",
 188         "CounterHTOff": "0,1,2,3",
 189         "Data_LA": "1",
 190         "EventCode": "0xcd",
 191         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
 192         "MSRIndex": "0x3F6",
 193         "MSRValue": "0x200",
 194         "PEBS": "2",
 195         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency.",
 196         "SampleAfterValue": "101",
 197         "TakenAlone": "1",
 198         "UMask": "0x1"
 199     },
 200     {
 201         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
 202         "Counter": "0,1,2,3",
 203         "CounterHTOff": "0,1,2,3",
 204         "Data_LA": "1",
 205         "EventCode": "0xcd",
 206         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
 207         "MSRIndex": "0x3F6",
 208         "MSRValue": "0x40",
 209         "PEBS": "2",
 210         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency.",
 211         "SampleAfterValue": "2003",
 212         "TakenAlone": "1",
 213         "UMask": "0x1"
 214     },
 215     {
 216         "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
 217         "Counter": "0,1,2,3",
 218         "CounterHTOff": "0,1,2,3",
 219         "Data_LA": "1",
 220         "EventCode": "0xcd",
 221         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
 222         "MSRIndex": "0x3F6",
 223         "MSRValue": "0x8",
 224         "PEBS": "2",
 225         "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency.",
 226         "SampleAfterValue": "50021",
 227         "TakenAlone": "1",
 228         "UMask": "0x1"
 229     },
 230     {
 231         "BriefDescription": "Demand Data Read requests who miss L3 cache",
 232         "Counter": "0,1,2,3",
 233         "CounterHTOff": "0,1,2,3,4,5,6,7",
 234         "EventCode": "0xB0",
 235         "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
 236         "PublicDescription": "Demand Data Read requests who miss L3 cache.",
 237         "SampleAfterValue": "100003",
 238         "UMask": "0x10"
 239     },
 240     {
 241         "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.",
 242         "Counter": "0,1,2,3",
 243         "CounterHTOff": "0,1,2,3,4,5,6,7",
 244         "CounterMask": "1",
 245         "EventCode": "0x60",
 246         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD",
 247         "SampleAfterValue": "2000003",
 248         "UMask": "0x10"
 249     },
 250     {
 251         "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.",
 252         "Counter": "0,1,2,3",
 253         "CounterHTOff": "0,1,2,3,4,5,6,7",
 254         "EventCode": "0x60",
 255         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD",
 256         "SampleAfterValue": "2000003",
 257         "UMask": "0x10"
 258     },
 259     {
 260         "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.",
 261         "Counter": "0,1,2,3",
 262         "CounterHTOff": "0,1,2,3,4,5,6,7",
 263         "CounterMask": "6",
 264         "EventCode": "0x60",
 265         "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6",
 266         "SampleAfterValue": "2000003",
 267         "UMask": "0x10"
 268     },
 269     {
 270         "BriefDescription": "Counts all demand code reads",
 271         "Counter": "0,1,2,3",
 272         "CounterHTOff": "0,1,2,3",
 273         "EventCode": "0xB7, 0xBB",
 274         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NON_DRAM",
 275         "MSRIndex": "0x1a6,0x1a7",
 276         "MSRValue": "0x20001C0004",
 277         "Offcore": "1",
 278         "SampleAfterValue": "100003",
 279         "UMask": "0x1"
 280     },
 281     {
 282         "BriefDescription": "Counts all demand code reads",
 283         "Counter": "0,1,2,3",
 284         "CounterHTOff": "0,1,2,3",
 285         "EventCode": "0xB7, 0xBB",
 286         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NON_DRAM",
 287         "MSRIndex": "0x1a6,0x1a7",
 288         "MSRValue": "0x2000080004",
 289         "Offcore": "1",
 290         "SampleAfterValue": "100003",
 291         "UMask": "0x1"
 292     },
 293     {
 294         "BriefDescription": "Counts all demand code reads",
 295         "Counter": "0,1,2,3",
 296         "CounterHTOff": "0,1,2,3",
 297         "EventCode": "0xB7, 0xBB",
 298         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NON_DRAM",
 299         "MSRIndex": "0x1a6,0x1a7",
 300         "MSRValue": "0x2000040004",
 301         "Offcore": "1",
 302         "SampleAfterValue": "100003",
 303         "UMask": "0x1"
 304     },
 305     {
 306         "BriefDescription": "Counts all demand code reads",
 307         "Counter": "0,1,2,3",
 308         "CounterHTOff": "0,1,2,3",
 309         "EventCode": "0xB7, 0xBB",
 310         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NON_DRAM",
 311         "MSRIndex": "0x1a6,0x1a7",
 312         "MSRValue": "0x2000100004",
 313         "Offcore": "1",
 314         "SampleAfterValue": "100003",
 315         "UMask": "0x1"
 316     },
 317     {
 318         "BriefDescription": "Counts all demand code reads",
 319         "Counter": "0,1,2,3",
 320         "CounterHTOff": "0,1,2,3",
 321         "EventCode": "0xB7, 0xBB",
 322         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP",
 323         "MSRIndex": "0x1a6,0x1a7",
 324         "MSRValue": "0x3FFC400004",
 325         "Offcore": "1",
 326         "SampleAfterValue": "100003",
 327         "UMask": "0x1"
 328     },
 329     {
 330         "BriefDescription": "Counts all demand code reads",
 331         "Counter": "0,1,2,3",
 332         "CounterHTOff": "0,1,2,3",
 333         "EventCode": "0xB7, 0xBB",
 334         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HITM",
 335         "MSRIndex": "0x1a6,0x1a7",
 336         "MSRValue": "0x103C400004",
 337         "Offcore": "1",
 338         "SampleAfterValue": "100003",
 339         "UMask": "0x1"
 340     },
 341     {
 342         "BriefDescription": "Counts all demand code reads",
 343         "Counter": "0,1,2,3",
 344         "CounterHTOff": "0,1,2,3",
 345         "EventCode": "0xB7, 0xBB",
 346         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD",
 347         "MSRIndex": "0x1a6,0x1a7",
 348         "MSRValue": "0x43C400004",
 349         "Offcore": "1",
 350         "SampleAfterValue": "100003",
 351         "UMask": "0x1"
 352     },
 353     {
 354         "BriefDescription": "Counts all demand code reads",
 355         "Counter": "0,1,2,3",
 356         "CounterHTOff": "0,1,2,3",
 357         "EventCode": "0xB7, 0xBB",
 358         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS",
 359         "MSRIndex": "0x1a6,0x1a7",
 360         "MSRValue": "0x23C400004",
 361         "Offcore": "1",
 362         "SampleAfterValue": "100003",
 363         "UMask": "0x1"
 364     },
 365     {
 366         "BriefDescription": "Counts all demand code reads",
 367         "Counter": "0,1,2,3",
 368         "CounterHTOff": "0,1,2,3",
 369         "EventCode": "0xB7, 0xBB",
 370         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE",
 371         "MSRIndex": "0x1a6,0x1a7",
 372         "MSRValue": "0xBC400004",
 373         "Offcore": "1",
 374         "SampleAfterValue": "100003",
 375         "UMask": "0x1"
 376     },
 377     {
 378         "BriefDescription": "Counts all demand code reads",
 379         "Counter": "0,1,2,3",
 380         "CounterHTOff": "0,1,2,3",
 381         "EventCode": "0xB7, 0xBB",
 382         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NON_DRAM",
 383         "MSRIndex": "0x1a6,0x1a7",
 384         "MSRValue": "0x203C400004",
 385         "Offcore": "1",
 386         "SampleAfterValue": "100003",
 387         "UMask": "0x1"
 388     },
 389     {
 390         "BriefDescription": "Counts all demand code reads",
 391         "Counter": "0,1,2,3",
 392         "CounterHTOff": "0,1,2,3",
 393         "EventCode": "0xB7, 0xBB",
 394         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED",
 395         "MSRIndex": "0x1a6,0x1a7",
 396         "MSRValue": "0x13C400004",
 397         "Offcore": "1",
 398         "SampleAfterValue": "100003",
 399         "UMask": "0x1"
 400     },
 401     {
 402         "BriefDescription": "Counts all demand code reads",
 403         "Counter": "0,1,2,3",
 404         "CounterHTOff": "0,1,2,3",
 405         "EventCode": "0xB7, 0xBB",
 406         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SPL_HIT",
 407         "MSRIndex": "0x1a6,0x1a7",
 408         "MSRValue": "0x7C400004",
 409         "Offcore": "1",
 410         "SampleAfterValue": "100003",
 411         "UMask": "0x1"
 412     },
 413     {
 414         "BriefDescription": "Counts all demand code reads",
 415         "Counter": "0,1,2,3",
 416         "CounterHTOff": "0,1,2,3",
 417         "EventCode": "0xB7, 0xBB",
 418         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
 419         "MSRIndex": "0x1a6,0x1a7",
 420         "MSRValue": "0x3FC4000004",
 421         "Offcore": "1",
 422         "SampleAfterValue": "100003",
 423         "UMask": "0x1"
 424     },
 425     {
 426         "BriefDescription": "Counts all demand code reads",
 427         "Counter": "0,1,2,3",
 428         "CounterHTOff": "0,1,2,3",
 429         "EventCode": "0xB7, 0xBB",
 430         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
 431         "MSRIndex": "0x1a6,0x1a7",
 432         "MSRValue": "0x1004000004",
 433         "Offcore": "1",
 434         "SampleAfterValue": "100003",
 435         "UMask": "0x1"
 436     },
 437     {
 438         "BriefDescription": "Counts all demand code reads",
 439         "Counter": "0,1,2,3",
 440         "CounterHTOff": "0,1,2,3",
 441         "EventCode": "0xB7, 0xBB",
 442         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
 443         "MSRIndex": "0x1a6,0x1a7",
 444         "MSRValue": "0x404000004",
 445         "Offcore": "1",
 446         "SampleAfterValue": "100003",
 447         "UMask": "0x1"
 448     },
 449     {
 450         "BriefDescription": "Counts all demand code reads",
 451         "Counter": "0,1,2,3",
 452         "CounterHTOff": "0,1,2,3",
 453         "EventCode": "0xB7, 0xBB",
 454         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
 455         "MSRIndex": "0x1a6,0x1a7",
 456         "MSRValue": "0x204000004",
 457         "Offcore": "1",
 458         "SampleAfterValue": "100003",
 459         "UMask": "0x1"
 460     },
 461     {
 462         "BriefDescription": "Counts all demand code reads",
 463         "Counter": "0,1,2,3",
 464         "CounterHTOff": "0,1,2,3",
 465         "EventCode": "0xB7, 0xBB",
 466         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
 467         "MSRIndex": "0x1a6,0x1a7",
 468         "MSRValue": "0x84000004",
 469         "Offcore": "1",
 470         "SampleAfterValue": "100003",
 471         "UMask": "0x1"
 472     },
 473     {
 474         "BriefDescription": "Counts all demand code reads",
 475         "Counter": "0,1,2,3",
 476         "CounterHTOff": "0,1,2,3",
 477         "EventCode": "0xB7, 0xBB",
 478         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
 479         "MSRIndex": "0x1a6,0x1a7",
 480         "MSRValue": "0x2004000004",
 481         "Offcore": "1",
 482         "SampleAfterValue": "100003",
 483         "UMask": "0x1"
 484     },
 485     {
 486         "BriefDescription": "Counts all demand code reads",
 487         "Counter": "0,1,2,3",
 488         "CounterHTOff": "0,1,2,3",
 489         "EventCode": "0xB7, 0xBB",
 490         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
 491         "MSRIndex": "0x1a6,0x1a7",
 492         "MSRValue": "0x104000004",
 493         "Offcore": "1",
 494         "SampleAfterValue": "100003",
 495         "UMask": "0x1"
 496     },
 497     {
 498         "BriefDescription": "Counts all demand code reads",
 499         "Counter": "0,1,2,3",
 500         "CounterHTOff": "0,1,2,3",
 501         "EventCode": "0xB7, 0xBB",
 502         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SPL_HIT",
 503         "MSRIndex": "0x1a6,0x1a7",
 504         "MSRValue": "0x44000004",
 505         "Offcore": "1",
 506         "SampleAfterValue": "100003",
 507         "UMask": "0x1"
 508     },
 509     {
 510         "BriefDescription": "Counts all demand code reads",
 511         "Counter": "0,1,2,3",
 512         "CounterHTOff": "0,1,2,3",
 513         "EventCode": "0xB7, 0xBB",
 514         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
 515         "MSRIndex": "0x1a6,0x1a7",
 516         "MSRValue": "0x2000400004",
 517         "Offcore": "1",
 518         "SampleAfterValue": "100003",
 519         "UMask": "0x1"
 520     },
 521     {
 522         "BriefDescription": "Counts all demand code reads",
 523         "Counter": "0,1,2,3",
 524         "CounterHTOff": "0,1,2,3",
 525         "EventCode": "0xB7, 0xBB",
 526         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
 527         "MSRIndex": "0x1a6,0x1a7",
 528         "MSRValue": "0x2000020004",
 529         "Offcore": "1",
 530         "SampleAfterValue": "100003",
 531         "UMask": "0x1"
 532     },
 533     {
 534         "BriefDescription": "Counts demand data reads",
 535         "Counter": "0,1,2,3",
 536         "CounterHTOff": "0,1,2,3",
 537         "EventCode": "0xB7, 0xBB",
 538         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NON_DRAM",
 539         "MSRIndex": "0x1a6,0x1a7",
 540         "MSRValue": "0x20001C0001",
 541         "Offcore": "1",
 542         "SampleAfterValue": "100003",
 543         "UMask": "0x1"
 544     },
 545     {
 546         "BriefDescription": "Counts demand data reads",
 547         "Counter": "0,1,2,3",
 548         "CounterHTOff": "0,1,2,3",
 549         "EventCode": "0xB7, 0xBB",
 550         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NON_DRAM",
 551         "MSRIndex": "0x1a6,0x1a7",
 552         "MSRValue": "0x2000080001",
 553         "Offcore": "1",
 554         "SampleAfterValue": "100003",
 555         "UMask": "0x1"
 556     },
 557     {
 558         "BriefDescription": "Counts demand data reads",
 559         "Counter": "0,1,2,3",
 560         "CounterHTOff": "0,1,2,3",
 561         "EventCode": "0xB7, 0xBB",
 562         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NON_DRAM",
 563         "MSRIndex": "0x1a6,0x1a7",
 564         "MSRValue": "0x2000040001",
 565         "Offcore": "1",
 566         "SampleAfterValue": "100003",
 567         "UMask": "0x1"
 568     },
 569     {
 570         "BriefDescription": "Counts demand data reads",
 571         "Counter": "0,1,2,3",
 572         "CounterHTOff": "0,1,2,3",
 573         "EventCode": "0xB7, 0xBB",
 574         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NON_DRAM",
 575         "MSRIndex": "0x1a6,0x1a7",
 576         "MSRValue": "0x2000100001",
 577         "Offcore": "1",
 578         "SampleAfterValue": "100003",
 579         "UMask": "0x1"
 580     },
 581     {
 582         "BriefDescription": "Counts demand data reads",
 583         "Counter": "0,1,2,3",
 584         "CounterHTOff": "0,1,2,3",
 585         "EventCode": "0xB7, 0xBB",
 586         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP",
 587         "MSRIndex": "0x1a6,0x1a7",
 588         "MSRValue": "0x3FFC400001",
 589         "Offcore": "1",
 590         "SampleAfterValue": "100003",
 591         "UMask": "0x1"
 592     },
 593     {
 594         "BriefDescription": "Counts demand data reads",
 595         "Counter": "0,1,2,3",
 596         "CounterHTOff": "0,1,2,3",
 597         "EventCode": "0xB7, 0xBB",
 598         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HITM",
 599         "MSRIndex": "0x1a6,0x1a7",
 600         "MSRValue": "0x103C400001",
 601         "Offcore": "1",
 602         "SampleAfterValue": "100003",
 603         "UMask": "0x1"
 604     },
 605     {
 606         "BriefDescription": "Counts demand data reads",
 607         "Counter": "0,1,2,3",
 608         "CounterHTOff": "0,1,2,3",
 609         "EventCode": "0xB7, 0xBB",
 610         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD",
 611         "MSRIndex": "0x1a6,0x1a7",
 612         "MSRValue": "0x43C400001",
 613         "Offcore": "1",
 614         "SampleAfterValue": "100003",
 615         "UMask": "0x1"
 616     },
 617     {
 618         "BriefDescription": "Counts demand data reads",
 619         "Counter": "0,1,2,3",
 620         "CounterHTOff": "0,1,2,3",
 621         "EventCode": "0xB7, 0xBB",
 622         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS",
 623         "MSRIndex": "0x1a6,0x1a7",
 624         "MSRValue": "0x23C400001",
 625         "Offcore": "1",
 626         "SampleAfterValue": "100003",
 627         "UMask": "0x1"
 628     },
 629     {
 630         "BriefDescription": "Counts demand data reads",
 631         "Counter": "0,1,2,3",
 632         "CounterHTOff": "0,1,2,3",
 633         "EventCode": "0xB7, 0xBB",
 634         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE",
 635         "MSRIndex": "0x1a6,0x1a7",
 636         "MSRValue": "0xBC400001",
 637         "Offcore": "1",
 638         "SampleAfterValue": "100003",
 639         "UMask": "0x1"
 640     },
 641     {
 642         "BriefDescription": "Counts demand data reads",
 643         "Counter": "0,1,2,3",
 644         "CounterHTOff": "0,1,2,3",
 645         "EventCode": "0xB7, 0xBB",
 646         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NON_DRAM",
 647         "MSRIndex": "0x1a6,0x1a7",
 648         "MSRValue": "0x203C400001",
 649         "Offcore": "1",
 650         "SampleAfterValue": "100003",
 651         "UMask": "0x1"
 652     },
 653     {
 654         "BriefDescription": "Counts demand data reads",
 655         "Counter": "0,1,2,3",
 656         "CounterHTOff": "0,1,2,3",
 657         "EventCode": "0xB7, 0xBB",
 658         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED",
 659         "MSRIndex": "0x1a6,0x1a7",
 660         "MSRValue": "0x13C400001",
 661         "Offcore": "1",
 662         "SampleAfterValue": "100003",
 663         "UMask": "0x1"
 664     },
 665     {
 666         "BriefDescription": "Counts demand data reads",
 667         "Counter": "0,1,2,3",
 668         "CounterHTOff": "0,1,2,3",
 669         "EventCode": "0xB7, 0xBB",
 670         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SPL_HIT",
 671         "MSRIndex": "0x1a6,0x1a7",
 672         "MSRValue": "0x7C400001",
 673         "Offcore": "1",
 674         "SampleAfterValue": "100003",
 675         "UMask": "0x1"
 676     },
 677     {
 678         "BriefDescription": "Counts demand data reads",
 679         "Counter": "0,1,2,3",
 680         "CounterHTOff": "0,1,2,3",
 681         "EventCode": "0xB7, 0xBB",
 682         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
 683         "MSRIndex": "0x1a6,0x1a7",
 684         "MSRValue": "0x3FC4000001",
 685         "Offcore": "1",
 686         "SampleAfterValue": "100003",
 687         "UMask": "0x1"
 688     },
 689     {
 690         "BriefDescription": "Counts demand data reads",
 691         "Counter": "0,1,2,3",
 692         "CounterHTOff": "0,1,2,3",
 693         "EventCode": "0xB7, 0xBB",
 694         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
 695         "MSRIndex": "0x1a6,0x1a7",
 696         "MSRValue": "0x1004000001",
 697         "Offcore": "1",
 698         "SampleAfterValue": "100003",
 699         "UMask": "0x1"
 700     },
 701     {
 702         "BriefDescription": "Counts demand data reads",
 703         "Counter": "0,1,2,3",
 704         "CounterHTOff": "0,1,2,3",
 705         "EventCode": "0xB7, 0xBB",
 706         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
 707         "MSRIndex": "0x1a6,0x1a7",
 708         "MSRValue": "0x404000001",
 709         "Offcore": "1",
 710         "SampleAfterValue": "100003",
 711         "UMask": "0x1"
 712     },
 713     {
 714         "BriefDescription": "Counts demand data reads",
 715         "Counter": "0,1,2,3",
 716         "CounterHTOff": "0,1,2,3",
 717         "EventCode": "0xB7, 0xBB",
 718         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
 719         "MSRIndex": "0x1a6,0x1a7",
 720         "MSRValue": "0x204000001",
 721         "Offcore": "1",
 722         "SampleAfterValue": "100003",
 723         "UMask": "0x1"
 724     },
 725     {
 726         "BriefDescription": "Counts demand data reads",
 727         "Counter": "0,1,2,3",
 728         "CounterHTOff": "0,1,2,3",
 729         "EventCode": "0xB7, 0xBB",
 730         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
 731         "MSRIndex": "0x1a6,0x1a7",
 732         "MSRValue": "0x84000001",
 733         "Offcore": "1",
 734         "SampleAfterValue": "100003",
 735         "UMask": "0x1"
 736     },
 737     {
 738         "BriefDescription": "Counts demand data reads",
 739         "Counter": "0,1,2,3",
 740         "CounterHTOff": "0,1,2,3",
 741         "EventCode": "0xB7, 0xBB",
 742         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
 743         "MSRIndex": "0x1a6,0x1a7",
 744         "MSRValue": "0x2004000001",
 745         "Offcore": "1",
 746         "SampleAfterValue": "100003",
 747         "UMask": "0x1"
 748     },
 749     {
 750         "BriefDescription": "Counts demand data reads",
 751         "Counter": "0,1,2,3",
 752         "CounterHTOff": "0,1,2,3",
 753         "EventCode": "0xB7, 0xBB",
 754         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
 755         "MSRIndex": "0x1a6,0x1a7",
 756         "MSRValue": "0x104000001",
 757         "Offcore": "1",
 758         "SampleAfterValue": "100003",
 759         "UMask": "0x1"
 760     },
 761     {
 762         "BriefDescription": "Counts demand data reads",
 763         "Counter": "0,1,2,3",
 764         "CounterHTOff": "0,1,2,3",
 765         "EventCode": "0xB7, 0xBB",
 766         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SPL_HIT",
 767         "MSRIndex": "0x1a6,0x1a7",
 768         "MSRValue": "0x44000001",
 769         "Offcore": "1",
 770         "SampleAfterValue": "100003",
 771         "UMask": "0x1"
 772     },
 773     {
 774         "BriefDescription": "Counts demand data reads",
 775         "Counter": "0,1,2,3",
 776         "CounterHTOff": "0,1,2,3",
 777         "EventCode": "0xB7, 0xBB",
 778         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
 779         "MSRIndex": "0x1a6,0x1a7",
 780         "MSRValue": "0x2000400001",
 781         "Offcore": "1",
 782         "SampleAfterValue": "100003",
 783         "UMask": "0x1"
 784     },
 785     {
 786         "BriefDescription": "Counts demand data reads",
 787         "Counter": "0,1,2,3",
 788         "CounterHTOff": "0,1,2,3",
 789         "EventCode": "0xB7, 0xBB",
 790         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM",
 791         "MSRIndex": "0x1a6,0x1a7",
 792         "MSRValue": "0x2000020001",
 793         "Offcore": "1",
 794         "SampleAfterValue": "100003",
 795         "UMask": "0x1"
 796     },
 797     {
 798         "BriefDescription": "Counts all demand data writes (RFOs)",
 799         "Counter": "0,1,2,3",
 800         "CounterHTOff": "0,1,2,3",
 801         "EventCode": "0xB7, 0xBB",
 802         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NON_DRAM",
 803         "MSRIndex": "0x1a6,0x1a7",
 804         "MSRValue": "0x20001C0002",
 805         "Offcore": "1",
 806         "SampleAfterValue": "100003",
 807         "UMask": "0x1"
 808     },
 809     {
 810         "BriefDescription": "Counts all demand data writes (RFOs)",
 811         "Counter": "0,1,2,3",
 812         "CounterHTOff": "0,1,2,3",
 813         "EventCode": "0xB7, 0xBB",
 814         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NON_DRAM",
 815         "MSRIndex": "0x1a6,0x1a7",
 816         "MSRValue": "0x2000080002",
 817         "Offcore": "1",
 818         "SampleAfterValue": "100003",
 819         "UMask": "0x1"
 820     },
 821     {
 822         "BriefDescription": "Counts all demand data writes (RFOs)",
 823         "Counter": "0,1,2,3",
 824         "CounterHTOff": "0,1,2,3",
 825         "EventCode": "0xB7, 0xBB",
 826         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NON_DRAM",
 827         "MSRIndex": "0x1a6,0x1a7",
 828         "MSRValue": "0x2000040002",
 829         "Offcore": "1",
 830         "SampleAfterValue": "100003",
 831         "UMask": "0x1"
 832     },
 833     {
 834         "BriefDescription": "Counts all demand data writes (RFOs)",
 835         "Counter": "0,1,2,3",
 836         "CounterHTOff": "0,1,2,3",
 837         "EventCode": "0xB7, 0xBB",
 838         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NON_DRAM",
 839         "MSRIndex": "0x1a6,0x1a7",
 840         "MSRValue": "0x2000100002",
 841         "Offcore": "1",
 842         "SampleAfterValue": "100003",
 843         "UMask": "0x1"
 844     },
 845     {
 846         "BriefDescription": "Counts all demand data writes (RFOs)",
 847         "Counter": "0,1,2,3",
 848         "CounterHTOff": "0,1,2,3",
 849         "EventCode": "0xB7, 0xBB",
 850         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP",
 851         "MSRIndex": "0x1a6,0x1a7",
 852         "MSRValue": "0x3FFC400002",
 853         "Offcore": "1",
 854         "SampleAfterValue": "100003",
 855         "UMask": "0x1"
 856     },
 857     {
 858         "BriefDescription": "Counts all demand data writes (RFOs)",
 859         "Counter": "0,1,2,3",
 860         "CounterHTOff": "0,1,2,3",
 861         "EventCode": "0xB7, 0xBB",
 862         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HITM",
 863         "MSRIndex": "0x1a6,0x1a7",
 864         "MSRValue": "0x103C400002",
 865         "Offcore": "1",
 866         "SampleAfterValue": "100003",
 867         "UMask": "0x1"
 868     },
 869     {
 870         "BriefDescription": "Counts all demand data writes (RFOs)",
 871         "Counter": "0,1,2,3",
 872         "CounterHTOff": "0,1,2,3",
 873         "EventCode": "0xB7, 0xBB",
 874         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HIT_NO_FWD",
 875         "MSRIndex": "0x1a6,0x1a7",
 876         "MSRValue": "0x43C400002",
 877         "Offcore": "1",
 878         "SampleAfterValue": "100003",
 879         "UMask": "0x1"
 880     },
 881     {
 882         "BriefDescription": "Counts all demand data writes (RFOs)",
 883         "Counter": "0,1,2,3",
 884         "CounterHTOff": "0,1,2,3",
 885         "EventCode": "0xB7, 0xBB",
 886         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS",
 887         "MSRIndex": "0x1a6,0x1a7",
 888         "MSRValue": "0x23C400002",
 889         "Offcore": "1",
 890         "SampleAfterValue": "100003",
 891         "UMask": "0x1"
 892     },
 893     {
 894         "BriefDescription": "Counts all demand data writes (RFOs)",
 895         "Counter": "0,1,2,3",
 896         "CounterHTOff": "0,1,2,3",
 897         "EventCode": "0xB7, 0xBB",
 898         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE",
 899         "MSRIndex": "0x1a6,0x1a7",
 900         "MSRValue": "0xBC400002",
 901         "Offcore": "1",
 902         "SampleAfterValue": "100003",
 903         "UMask": "0x1"
 904     },
 905     {
 906         "BriefDescription": "Counts all demand data writes (RFOs)",
 907         "Counter": "0,1,2,3",
 908         "CounterHTOff": "0,1,2,3",
 909         "EventCode": "0xB7, 0xBB",
 910         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NON_DRAM",
 911         "MSRIndex": "0x1a6,0x1a7",
 912         "MSRValue": "0x203C400002",
 913         "Offcore": "1",
 914         "SampleAfterValue": "100003",
 915         "UMask": "0x1"
 916     },
 917     {
 918         "BriefDescription": "Counts all demand data writes (RFOs)",
 919         "Counter": "0,1,2,3",
 920         "CounterHTOff": "0,1,2,3",
 921         "EventCode": "0xB7, 0xBB",
 922         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NOT_NEEDED",
 923         "MSRIndex": "0x1a6,0x1a7",
 924         "MSRValue": "0x13C400002",
 925         "Offcore": "1",
 926         "SampleAfterValue": "100003",
 927         "UMask": "0x1"
 928     },
 929     {
 930         "BriefDescription": "Counts all demand data writes (RFOs)",
 931         "Counter": "0,1,2,3",
 932         "CounterHTOff": "0,1,2,3",
 933         "EventCode": "0xB7, 0xBB",
 934         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SPL_HIT",
 935         "MSRIndex": "0x1a6,0x1a7",
 936         "MSRValue": "0x7C400002",
 937         "Offcore": "1",
 938         "SampleAfterValue": "100003",
 939         "UMask": "0x1"
 940     },
 941     {
 942         "BriefDescription": "Counts all demand data writes (RFOs)",
 943         "Counter": "0,1,2,3",
 944         "CounterHTOff": "0,1,2,3",
 945         "EventCode": "0xB7, 0xBB",
 946         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
 947         "MSRIndex": "0x1a6,0x1a7",
 948         "MSRValue": "0x3FC4000002",
 949         "Offcore": "1",
 950         "SampleAfterValue": "100003",
 951         "UMask": "0x1"
 952     },
 953     {
 954         "BriefDescription": "Counts all demand data writes (RFOs)",
 955         "Counter": "0,1,2,3",
 956         "CounterHTOff": "0,1,2,3",
 957         "EventCode": "0xB7, 0xBB",
 958         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
 959         "MSRIndex": "0x1a6,0x1a7",
 960         "MSRValue": "0x1004000002",
 961         "Offcore": "1",
 962         "SampleAfterValue": "100003",
 963         "UMask": "0x1"
 964     },
 965     {
 966         "BriefDescription": "Counts all demand data writes (RFOs)",
 967         "Counter": "0,1,2,3",
 968         "CounterHTOff": "0,1,2,3",
 969         "EventCode": "0xB7, 0xBB",
 970         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
 971         "MSRIndex": "0x1a6,0x1a7",
 972         "MSRValue": "0x404000002",
 973         "Offcore": "1",
 974         "SampleAfterValue": "100003",
 975         "UMask": "0x1"
 976     },
 977     {
 978         "BriefDescription": "Counts all demand data writes (RFOs)",
 979         "Counter": "0,1,2,3",
 980         "CounterHTOff": "0,1,2,3",
 981         "EventCode": "0xB7, 0xBB",
 982         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
 983         "MSRIndex": "0x1a6,0x1a7",
 984         "MSRValue": "0x204000002",
 985         "Offcore": "1",
 986         "SampleAfterValue": "100003",
 987         "UMask": "0x1"
 988     },
 989     {
 990         "BriefDescription": "Counts all demand data writes (RFOs)",
 991         "Counter": "0,1,2,3",
 992         "CounterHTOff": "0,1,2,3",
 993         "EventCode": "0xB7, 0xBB",
 994         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
 995         "MSRIndex": "0x1a6,0x1a7",
 996         "MSRValue": "0x84000002",
 997         "Offcore": "1",
 998         "SampleAfterValue": "100003",
 999         "UMask": "0x1"
1000     },
1001     {
1002         "BriefDescription": "Counts all demand data writes (RFOs)",
1003         "Counter": "0,1,2,3",
1004         "CounterHTOff": "0,1,2,3",
1005         "EventCode": "0xB7, 0xBB",
1006         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
1007         "MSRIndex": "0x1a6,0x1a7",
1008         "MSRValue": "0x2004000002",
1009         "Offcore": "1",
1010         "SampleAfterValue": "100003",
1011         "UMask": "0x1"
1012     },
1013     {
1014         "BriefDescription": "Counts all demand data writes (RFOs)",
1015         "Counter": "0,1,2,3",
1016         "CounterHTOff": "0,1,2,3",
1017         "EventCode": "0xB7, 0xBB",
1018         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
1019         "MSRIndex": "0x1a6,0x1a7",
1020         "MSRValue": "0x104000002",
1021         "Offcore": "1",
1022         "SampleAfterValue": "100003",
1023         "UMask": "0x1"
1024     },
1025     {
1026         "BriefDescription": "Counts all demand data writes (RFOs)",
1027         "Counter": "0,1,2,3",
1028         "CounterHTOff": "0,1,2,3",
1029         "EventCode": "0xB7, 0xBB",
1030         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SPL_HIT",
1031         "MSRIndex": "0x1a6,0x1a7",
1032         "MSRValue": "0x44000002",
1033         "Offcore": "1",
1034         "SampleAfterValue": "100003",
1035         "UMask": "0x1"
1036     },
1037     {
1038         "BriefDescription": "Counts all demand data writes (RFOs)",
1039         "Counter": "0,1,2,3",
1040         "CounterHTOff": "0,1,2,3",
1041         "EventCode": "0xB7, 0xBB",
1042         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
1043         "MSRIndex": "0x1a6,0x1a7",
1044         "MSRValue": "0x2000400002",
1045         "Offcore": "1",
1046         "SampleAfterValue": "100003",
1047         "UMask": "0x1"
1048     },
1049     {
1050         "BriefDescription": "Counts all demand data writes (RFOs)",
1051         "Counter": "0,1,2,3",
1052         "CounterHTOff": "0,1,2,3",
1053         "EventCode": "0xB7, 0xBB",
1054         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM",
1055         "MSRIndex": "0x1a6,0x1a7",
1056         "MSRValue": "0x2000020002",
1057         "Offcore": "1",
1058         "SampleAfterValue": "100003",
1059         "UMask": "0x1"
1060     },
1061     {
1062         "BriefDescription": "Counts any other requests",
1063         "Counter": "0,1,2,3",
1064         "CounterHTOff": "0,1,2,3",
1065         "EventCode": "0xB7, 0xBB",
1066         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NON_DRAM",
1067         "MSRIndex": "0x1a6,0x1a7",
1068         "MSRValue": "0x20001C8000",
1069         "Offcore": "1",
1070         "SampleAfterValue": "100003",
1071         "UMask": "0x1"
1072     },
1073     {
1074         "BriefDescription": "Counts any other requests",
1075         "Counter": "0,1,2,3",
1076         "CounterHTOff": "0,1,2,3",
1077         "EventCode": "0xB7, 0xBB",
1078         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NON_DRAM",
1079         "MSRIndex": "0x1a6,0x1a7",
1080         "MSRValue": "0x2000088000",
1081         "Offcore": "1",
1082         "SampleAfterValue": "100003",
1083         "UMask": "0x1"
1084     },
1085     {
1086         "BriefDescription": "Counts any other requests",
1087         "Counter": "0,1,2,3",
1088         "CounterHTOff": "0,1,2,3",
1089         "EventCode": "0xB7, 0xBB",
1090         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NON_DRAM",
1091         "MSRIndex": "0x1a6,0x1a7",
1092         "MSRValue": "0x2000048000",
1093         "Offcore": "1",
1094         "SampleAfterValue": "100003",
1095         "UMask": "0x1"
1096     },
1097     {
1098         "BriefDescription": "Counts any other requests",
1099         "Counter": "0,1,2,3",
1100         "CounterHTOff": "0,1,2,3",
1101         "EventCode": "0xB7, 0xBB",
1102         "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NON_DRAM",
1103         "MSRIndex": "0x1a6,0x1a7",
1104         "MSRValue": "0x2000108000",
1105         "Offcore": "1",
1106         "SampleAfterValue": "100003",
1107         "UMask": "0x1"
1108     },
1109     {
1110         "BriefDescription": "Counts any other requests",
1111         "Counter": "0,1,2,3",
1112         "CounterHTOff": "0,1,2,3",
1113         "EventCode": "0xB7, 0xBB",
1114         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.ANY_SNOOP",
1115         "MSRIndex": "0x1a6,0x1a7",
1116         "MSRValue": "0x3FFC408000",
1117         "Offcore": "1",
1118         "SampleAfterValue": "100003",
1119         "UMask": "0x1"
1120     },
1121     {
1122         "BriefDescription": "Counts any other requests",
1123         "Counter": "0,1,2,3",
1124         "CounterHTOff": "0,1,2,3",
1125         "EventCode": "0xB7, 0xBB",
1126         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HITM",
1127         "MSRIndex": "0x1a6,0x1a7",
1128         "MSRValue": "0x103C408000",
1129         "Offcore": "1",
1130         "SampleAfterValue": "100003",
1131         "UMask": "0x1"
1132     },
1133     {
1134         "BriefDescription": "Counts any other requests",
1135         "Counter": "0,1,2,3",
1136         "CounterHTOff": "0,1,2,3",
1137         "EventCode": "0xB7, 0xBB",
1138         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD",
1139         "MSRIndex": "0x1a6,0x1a7",
1140         "MSRValue": "0x43C408000",
1141         "Offcore": "1",
1142         "SampleAfterValue": "100003",
1143         "UMask": "0x1"
1144     },
1145     {
1146         "BriefDescription": "Counts any other requests",
1147         "Counter": "0,1,2,3",
1148         "CounterHTOff": "0,1,2,3",
1149         "EventCode": "0xB7, 0xBB",
1150         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS",
1151         "MSRIndex": "0x1a6,0x1a7",
1152         "MSRValue": "0x23C408000",
1153         "Offcore": "1",
1154         "SampleAfterValue": "100003",
1155         "UMask": "0x1"
1156     },
1157     {
1158         "BriefDescription": "Counts any other requests",
1159         "Counter": "0,1,2,3",
1160         "CounterHTOff": "0,1,2,3",
1161         "EventCode": "0xB7, 0xBB",
1162         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE",
1163         "MSRIndex": "0x1a6,0x1a7",
1164         "MSRValue": "0xBC408000",
1165         "Offcore": "1",
1166         "SampleAfterValue": "100003",
1167         "UMask": "0x1"
1168     },
1169     {
1170         "BriefDescription": "Counts any other requests",
1171         "Counter": "0,1,2,3",
1172         "CounterHTOff": "0,1,2,3",
1173         "EventCode": "0xB7, 0xBB",
1174         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NON_DRAM",
1175         "MSRIndex": "0x1a6,0x1a7",
1176         "MSRValue": "0x203C408000",
1177         "Offcore": "1",
1178         "SampleAfterValue": "100003",
1179         "UMask": "0x1"
1180     },
1181     {
1182         "BriefDescription": "Counts any other requests",
1183         "Counter": "0,1,2,3",
1184         "CounterHTOff": "0,1,2,3",
1185         "EventCode": "0xB7, 0xBB",
1186         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED",
1187         "MSRIndex": "0x1a6,0x1a7",
1188         "MSRValue": "0x13C408000",
1189         "Offcore": "1",
1190         "SampleAfterValue": "100003",
1191         "UMask": "0x1"
1192     },
1193     {
1194         "BriefDescription": "Counts any other requests",
1195         "Counter": "0,1,2,3",
1196         "CounterHTOff": "0,1,2,3",
1197         "EventCode": "0xB7, 0xBB",
1198         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SPL_HIT",
1199         "MSRIndex": "0x1a6,0x1a7",
1200         "MSRValue": "0x7C408000",
1201         "Offcore": "1",
1202         "SampleAfterValue": "100003",
1203         "UMask": "0x1"
1204     },
1205     {
1206         "BriefDescription": "Counts any other requests",
1207         "Counter": "0,1,2,3",
1208         "CounterHTOff": "0,1,2,3",
1209         "EventCode": "0xB7, 0xBB",
1210         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP",
1211         "MSRIndex": "0x1a6,0x1a7",
1212         "MSRValue": "0x3FC4008000",
1213         "Offcore": "1",
1214         "SampleAfterValue": "100003",
1215         "UMask": "0x1"
1216     },
1217     {
1218         "BriefDescription": "Counts any other requests",
1219         "Counter": "0,1,2,3",
1220         "CounterHTOff": "0,1,2,3",
1221         "EventCode": "0xB7, 0xBB",
1222         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM",
1223         "MSRIndex": "0x1a6,0x1a7",
1224         "MSRValue": "0x1004008000",
1225         "Offcore": "1",
1226         "SampleAfterValue": "100003",
1227         "UMask": "0x1"
1228     },
1229     {
1230         "BriefDescription": "Counts any other requests",
1231         "Counter": "0,1,2,3",
1232         "CounterHTOff": "0,1,2,3",
1233         "EventCode": "0xB7, 0xBB",
1234         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD",
1235         "MSRIndex": "0x1a6,0x1a7",
1236         "MSRValue": "0x404008000",
1237         "Offcore": "1",
1238         "SampleAfterValue": "100003",
1239         "UMask": "0x1"
1240     },
1241     {
1242         "BriefDescription": "Counts any other requests",
1243         "Counter": "0,1,2,3",
1244         "CounterHTOff": "0,1,2,3",
1245         "EventCode": "0xB7, 0xBB",
1246         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS",
1247         "MSRIndex": "0x1a6,0x1a7",
1248         "MSRValue": "0x204008000",
1249         "Offcore": "1",
1250         "SampleAfterValue": "100003",
1251         "UMask": "0x1"
1252     },
1253     {
1254         "BriefDescription": "Counts any other requests",
1255         "Counter": "0,1,2,3",
1256         "CounterHTOff": "0,1,2,3",
1257         "EventCode": "0xB7, 0xBB",
1258         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE",
1259         "MSRIndex": "0x1a6,0x1a7",
1260         "MSRValue": "0x84008000",
1261         "Offcore": "1",
1262         "SampleAfterValue": "100003",
1263         "UMask": "0x1"
1264     },
1265     {
1266         "BriefDescription": "Counts any other requests",
1267         "Counter": "0,1,2,3",
1268         "CounterHTOff": "0,1,2,3",
1269         "EventCode": "0xB7, 0xBB",
1270         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM",
1271         "MSRIndex": "0x1a6,0x1a7",
1272         "MSRValue": "0x2004008000",
1273         "Offcore": "1",
1274         "SampleAfterValue": "100003",
1275         "UMask": "0x1"
1276     },
1277     {
1278         "BriefDescription": "Counts any other requests",
1279         "Counter": "0,1,2,3",
1280         "CounterHTOff": "0,1,2,3",
1281         "EventCode": "0xB7, 0xBB",
1282         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED",
1283         "MSRIndex": "0x1a6,0x1a7",
1284         "MSRValue": "0x104008000",
1285         "Offcore": "1",
1286         "SampleAfterValue": "100003",
1287         "UMask": "0x1"
1288     },
1289     {
1290         "BriefDescription": "Counts any other requests",
1291         "Counter": "0,1,2,3",
1292         "CounterHTOff": "0,1,2,3",
1293         "EventCode": "0xB7, 0xBB",
1294         "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SPL_HIT",
1295         "MSRIndex": "0x1a6,0x1a7",
1296         "MSRValue": "0x44008000",
1297         "Offcore": "1",
1298         "SampleAfterValue": "100003",
1299         "UMask": "0x1"
1300     },
1301     {
1302         "BriefDescription": "Counts any other requests",
1303         "Counter": "0,1,2,3",
1304         "CounterHTOff": "0,1,2,3",
1305         "EventCode": "0xB7, 0xBB",
1306         "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM",
1307         "MSRIndex": "0x1a6,0x1a7",
1308         "MSRValue": "0x2000408000",
1309         "Offcore": "1",
1310         "SampleAfterValue": "100003",
1311         "UMask": "0x1"
1312     },
1313     {
1314         "BriefDescription": "Counts any other requests",
1315         "Counter": "0,1,2,3",
1316         "CounterHTOff": "0,1,2,3",
1317         "EventCode": "0xB7, 0xBB",
1318         "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NON_DRAM",
1319         "MSRIndex": "0x1a6,0x1a7",
1320         "MSRValue": "0x2000028000",
1321         "Offcore": "1",
1322         "SampleAfterValue": "100003",
1323         "UMask": "0x1"
1324     },
1325     {
1326         "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).",
1327         "Counter": "0,1,2,3",
1328         "CounterHTOff": "0,1,2,3,4,5,6,7",
1329         "EventCode": "0xC9",
1330         "EventName": "RTM_RETIRED.ABORTED",
1331         "PEBS": "1",
1332         "PublicDescription": "Number of times RTM abort was triggered.",
1333         "SampleAfterValue": "2000003",
1334         "UMask": "0x4"
1335     },
1336     {
1337         "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
1338         "Counter": "0,1,2,3",
1339         "CounterHTOff": "0,1,2,3,4,5,6,7",
1340         "EventCode": "0xC9",
1341         "EventName": "RTM_RETIRED.ABORTED_EVENTS",
1342         "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
1343         "SampleAfterValue": "2000003",
1344         "UMask": "0x80"
1345     },
1346     {
1347         "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
1348         "Counter": "0,1,2,3",
1349         "CounterHTOff": "0,1,2,3,4,5,6,7",
1350         "EventCode": "0xC9",
1351         "EventName": "RTM_RETIRED.ABORTED_MEM",
1352         "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
1353         "SampleAfterValue": "2000003",
1354         "UMask": "0x8"
1355     },
1356     {
1357         "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
1358         "Counter": "0,1,2,3",
1359         "CounterHTOff": "0,1,2,3,4,5,6,7",
1360         "EventCode": "0xC9",
1361         "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
1362         "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.",
1363         "SampleAfterValue": "2000003",
1364         "UMask": "0x40"
1365     },
1366     {
1367         "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.",
1368         "Counter": "0,1,2,3",
1369         "CounterHTOff": "0,1,2,3,4,5,6,7",
1370         "EventCode": "0xC9",
1371         "EventName": "RTM_RETIRED.ABORTED_TIMER",
1372         "SampleAfterValue": "2000003",
1373         "UMask": "0x10"
1374     },
1375     {
1376         "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
1377         "Counter": "0,1,2,3",
1378         "CounterHTOff": "0,1,2,3,4,5,6,7",
1379         "EventCode": "0xC9",
1380         "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
1381         "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.",
1382         "SampleAfterValue": "2000003",
1383         "UMask": "0x20"
1384     },
1385     {
1386         "BriefDescription": "Number of times an RTM execution successfully committed",
1387         "Counter": "0,1,2,3",
1388         "CounterHTOff": "0,1,2,3,4,5,6,7",
1389         "EventCode": "0xC9",
1390         "EventName": "RTM_RETIRED.COMMIT",
1391         "PublicDescription": "Number of times RTM commit succeeded.",
1392         "SampleAfterValue": "2000003",
1393         "UMask": "0x2"
1394     },
1395     {
1396         "BriefDescription": "Number of times an RTM execution started.",
1397         "Counter": "0,1,2,3",
1398         "CounterHTOff": "0,1,2,3,4,5,6,7",
1399         "EventCode": "0xC9",
1400         "EventName": "RTM_RETIRED.START",
1401         "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.",
1402         "SampleAfterValue": "2000003",
1403         "UMask": "0x1"
1404     },
1405     {
1406         "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
1407         "Counter": "0,1,2,3",
1408         "CounterHTOff": "0,1,2,3,4,5,6,7",
1409         "EventCode": "0x5d",
1410         "EventName": "TX_EXEC.MISC1",
1411         "SampleAfterValue": "2000003",
1412         "UMask": "0x1"
1413     },
1414     {
1415         "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
1416         "Counter": "0,1,2,3",
1417         "CounterHTOff": "0,1,2,3,4,5,6,7",
1418         "EventCode": "0x5d",
1419         "EventName": "TX_EXEC.MISC2",
1420         "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
1421         "SampleAfterValue": "2000003",
1422         "UMask": "0x2"
1423     },
1424     {
1425         "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
1426         "Counter": "0,1,2,3",
1427         "CounterHTOff": "0,1,2,3,4,5,6,7",
1428         "EventCode": "0x5d",
1429         "EventName": "TX_EXEC.MISC3",
1430         "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
1431         "SampleAfterValue": "2000003",
1432         "UMask": "0x4"
1433     },
1434     {
1435         "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
1436         "Counter": "0,1,2,3",
1437         "CounterHTOff": "0,1,2,3,4,5,6,7",
1438         "EventCode": "0x5d",
1439         "EventName": "TX_EXEC.MISC4",
1440         "PublicDescription": "RTM region detected inside HLE.",
1441         "SampleAfterValue": "2000003",
1442         "UMask": "0x8"
1443     },
1444     {
1445         "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region",
1446         "Counter": "0,1,2,3",
1447         "CounterHTOff": "0,1,2,3,4,5,6,7",
1448         "EventCode": "0x5d",
1449         "EventName": "TX_EXEC.MISC5",
1450         "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
1451         "SampleAfterValue": "2000003",
1452         "UMask": "0x10"
1453     },
1454     {
1455         "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.",
1456         "Counter": "0,1,2,3",
1457         "CounterHTOff": "0,1,2,3,4,5,6,7",
1458         "EventCode": "0x54",
1459         "EventName": "TX_MEM.ABORT_CAPACITY",
1460         "SampleAfterValue": "2000003",
1461         "UMask": "0x2"
1462     },
1463     {
1464         "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
1465         "Counter": "0,1,2,3",
1466         "CounterHTOff": "0,1,2,3,4,5,6,7",
1467         "EventCode": "0x54",
1468         "EventName": "TX_MEM.ABORT_CONFLICT",
1469         "PublicDescription": "Number of times a TSX line had a cache conflict.",
1470         "SampleAfterValue": "2000003",
1471         "UMask": "0x1"
1472     },
1473     {
1474         "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer",
1475         "Counter": "0,1,2,3",
1476         "CounterHTOff": "0,1,2,3,4,5,6,7",
1477         "EventCode": "0x54",
1478         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
1479         "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
1480         "SampleAfterValue": "2000003",
1481         "UMask": "0x10"
1482     },
1483     {
1484         "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.",
1485         "Counter": "0,1,2,3",
1486         "CounterHTOff": "0,1,2,3,4,5,6,7",
1487         "EventCode": "0x54",
1488         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
1489         "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
1490         "SampleAfterValue": "2000003",
1491         "UMask": "0x8"
1492     },
1493     {
1494         "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.",
1495         "Counter": "0,1,2,3",
1496         "CounterHTOff": "0,1,2,3,4,5,6,7",
1497         "EventCode": "0x54",
1498         "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
1499         "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
1500         "SampleAfterValue": "2000003",
1501         "UMask": "0x20"
1502     },
1503     {
1504         "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer",
1505         "Counter": "0,1,2,3",
1506         "CounterHTOff": "0,1,2,3,4,5,6,7",
1507         "EventCode": "0x54",
1508         "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
1509         "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
1510         "SampleAfterValue": "2000003",
1511         "UMask": "0x4"
1512     },
1513     {
1514         "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.",
1515         "Counter": "0,1,2,3",
1516         "CounterHTOff": "0,1,2,3,4,5,6,7",
1517         "EventCode": "0x54",
1518         "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
1519         "PublicDescription": "Number of times we could not allocate Lock Buffer.",
1520         "SampleAfterValue": "2000003",
1521         "UMask": "0x40"
1522     }
1523 ]