tools/perf/pmu-events/arch/x86/sandybridge/memory.json

   1 [
   2     {
   3         "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
   4         "EventCode": "0xC3",
   5         "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
   6         "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers.  Machine clears can have a significant performance impact if they are happening frequently.",
   7         "SampleAfterValue": "100003",
   8         "UMask": "0x2"
   9     },
  10     {
  11         "BriefDescription": "Loads with latency value being above 128.",
  12         "EventCode": "0xCD",
  13         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
  14         "MSRIndex": "0x3F6",
  15         "MSRValue": "0x80",
  16         "PEBS": "2",
  17         "SampleAfterValue": "1009",
  18         "UMask": "0x1"
  19     },
  20     {
  21         "BriefDescription": "Loads with latency value being above 16.",
  22         "EventCode": "0xCD",
  23         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
  24         "MSRIndex": "0x3F6",
  25         "MSRValue": "0x10",
  26         "PEBS": "2",
  27         "SampleAfterValue": "20011",
  28         "UMask": "0x1"
  29     },
  30     {
  31         "BriefDescription": "Loads with latency value being above 256.",
  32         "EventCode": "0xCD",
  33         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
  34         "MSRIndex": "0x3F6",
  35         "MSRValue": "0x100",
  36         "PEBS": "2",
  37         "SampleAfterValue": "503",
  38         "UMask": "0x1"
  39     },
  40     {
  41         "BriefDescription": "Loads with latency value being above 32.",
  42         "EventCode": "0xCD",
  43         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
  44         "MSRIndex": "0x3F6",
  45         "MSRValue": "0x20",
  46         "PEBS": "2",
  47         "SampleAfterValue": "100007",
  48         "UMask": "0x1"
  49     },
  50     {
  51         "BriefDescription": "Loads with latency value being above 4 .",
  52         "EventCode": "0xCD",
  53         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
  54         "MSRIndex": "0x3F6",
  55         "MSRValue": "0x4",
  56         "PEBS": "2",
  57         "SampleAfterValue": "100003",
  58         "UMask": "0x1"
  59     },
  60     {
  61         "BriefDescription": "Loads with latency value being above 512.",
  62         "EventCode": "0xCD",
  63         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
  64         "MSRIndex": "0x3F6",
  65         "MSRValue": "0x200",
  66         "PEBS": "2",
  67         "SampleAfterValue": "101",
  68         "UMask": "0x1"
  69     },
  70     {
  71         "BriefDescription": "Loads with latency value being above 64.",
  72         "EventCode": "0xCD",
  73         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
  74         "MSRIndex": "0x3F6",
  75         "MSRValue": "0x40",
  76         "PEBS": "2",
  77         "SampleAfterValue": "2003",
  78         "UMask": "0x1"
  79     },
  80     {
  81         "BriefDescription": "Loads with latency value being above 8.",
  82         "EventCode": "0xCD",
  83         "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
  84         "MSRIndex": "0x3F6",
  85         "MSRValue": "0x8",
  86         "PEBS": "2",
  87         "SampleAfterValue": "50021",
  88         "UMask": "0x1"
  89     },
  90     {
  91         "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).",
  92         "EventCode": "0xCD",
  93         "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE",
  94         "PEBS": "2",
  95         "SampleAfterValue": "2000003",
  96         "UMask": "0x2"
  97     },
  98     {
  99         "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.",
 100         "EventCode": "0x05",
 101         "EventName": "MISALIGN_MEM_REF.LOADS",
 102         "SampleAfterValue": "2000003",
 103         "UMask": "0x1"
 104     },
 105     {
 106         "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.",
 107         "EventCode": "0x05",
 108         "EventName": "MISALIGN_MEM_REF.STORES",
 109         "SampleAfterValue": "2000003",
 110         "UMask": "0x2"
 111     },
 112     {
 113         "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC  and the data returned from dram.",
 114         "EventCode": "0xB7, 0xBB",
 115         "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM",
 116         "MSRIndex": "0x1a6,0x1a7",
 117         "MSRValue": "0x300400244",
 118         "SampleAfterValue": "100003",
 119         "UMask": "0x1"
 120     },
 121     {
 122         "BriefDescription": "Counts all demand & prefetch data reads that miss the LLC  and the data returned from dram.",
 123         "EventCode": "0xB7, 0xBB",
 124         "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM",
 125         "MSRIndex": "0x1a6,0x1a7",
 126         "MSRValue": "0x300400091",
 127         "SampleAfterValue": "100003",
 128         "UMask": "0x1"
 129     },
 130     {
 131         "BriefDescription": "Counts all prefetch code reads that miss the LLC  and the data returned from dram.",
 132         "EventCode": "0xB7, 0xBB",
 133         "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_MISS.DRAM",
 134         "MSRIndex": "0x1a6,0x1a7",
 135         "MSRValue": "0x300400240",
 136         "SampleAfterValue": "100003",
 137         "UMask": "0x1"
 138     },
 139     {
 140         "BriefDescription": "Counts all prefetch data reads that miss the LLC  and the data returned from dram.",
 141         "EventCode": "0xB7, 0xBB",
 142         "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_MISS.DRAM",
 143         "MSRIndex": "0x1a6,0x1a7",
 144         "MSRValue": "0x300400090",
 145         "SampleAfterValue": "100003",
 146         "UMask": "0x1"
 147     },
 148     {
 149         "BriefDescription": "Counts all prefetch RFOs that miss the LLC  and the data returned from dram.",
 150         "EventCode": "0xB7, 0xBB",
 151         "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_MISS.DRAM",
 152         "MSRIndex": "0x1a6,0x1a7",
 153         "MSRValue": "0x300400120",
 154         "SampleAfterValue": "100003",
 155         "UMask": "0x1"
 156     },
 157     {
 158         "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC  and the data returned from dram.",
 159         "EventCode": "0xB7, 0xBB",
 160         "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM",
 161         "MSRIndex": "0x1a6,0x1a7",
 162         "MSRValue": "0x3004003f7",
 163         "SampleAfterValue": "100003",
 164         "UMask": "0x1"
 165     },
 166     {
 167         "BriefDescription": "Counts all demand & prefetch RFOs that miss the LLC  and the data returned from dram.",
 168         "EventCode": "0xB7, 0xBB",
 169         "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.DRAM",
 170         "MSRIndex": "0x1a6,0x1a7",
 171         "MSRValue": "0x300400122",
 172         "SampleAfterValue": "100003",
 173         "UMask": "0x1"
 174     },
 175     {
 176         "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
 177         "EventCode": "0xB7, 0xBB",
 178         "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_MISS_LOCAL.DRAM",
 179         "MSRIndex": "0x1a6,0x1a7",
 180         "MSRValue": "0x1f80408fff",
 181         "PublicDescription": "This event counts any requests that miss the LLC where the data was returned from local DRAM",
 182         "SampleAfterValue": "100003",
 183         "UMask": "0x1"
 184     },
 185     {
 186         "BriefDescription": "Counts LLC replacements.",
 187         "EventCode": "0xB7, 0xBB",
 188         "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM",
 189         "MSRIndex": "0x1a6,0x1a7",
 190         "MSRValue": "0x6004001b3",
 191         "PublicDescription": "This event counts all data requests (demand/prefetch data reads and demand data writes (RFOs) that miss the LLC  where the data is returned from local DRAM",
 192         "SampleAfterValue": "100003",
 193         "UMask": "0x1"
 194     },
 195     {
 196         "BriefDescription": "REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT",
 197         "EventCode": "0xB7, 0xBB",
 198         "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS_LOCAL.ANY_LLC_HIT",
 199         "MSRIndex": "0x1a6,0x1a7",
 200         "MSRValue": "0x17004001b3",
 201         "SampleAfterValue": "100003",
 202         "UMask": "0x1"
 203     },
 204     {
 205         "BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram.",
 206         "EventCode": "0xB7, 0xBB",
 207         "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM",
 208         "MSRIndex": "0x1a6,0x1a7",
 209         "MSRValue": "0x300400004",
 210         "SampleAfterValue": "100003",
 211         "UMask": "0x1"
 212     },
 213     {
 214         "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram.",
 215         "EventCode": "0xB7, 0xBB",
 216         "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM",
 217         "MSRIndex": "0x1a6,0x1a7",
 218         "MSRValue": "0x300400001",
 219         "SampleAfterValue": "100003",
 220         "UMask": "0x1"
 221     },
 222     {
 223         "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
 224         "EventCode": "0xB7, 0xBB",
 225         "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_MISS_LOCAL.DRAM",
 226         "MSRIndex": "0x1a6,0x1a7",
 227         "MSRValue": "0x1f80400004",
 228         "SampleAfterValue": "100003",
 229         "UMask": "0x1"
 230     },
 231     {
 232         "BriefDescription": "Counts demand data writes (RFOs) that miss the LLC and the data returned from dram.",
 233         "EventCode": "0xB7, 0xBB",
 234         "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.DRAM",
 235         "MSRIndex": "0x1a6,0x1a7",
 236         "MSRValue": "0x300400002",
 237         "SampleAfterValue": "100003",
 238         "UMask": "0x1"
 239     },
 240     {
 241         "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
 242         "EventCode": "0xB7, 0xBB",
 243         "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_MISS_LOCAL.DRAM",
 244         "MSRIndex": "0x1a6,0x1a7",
 245         "MSRValue": "0x1f80400010",
 246         "SampleAfterValue": "100003",
 247         "UMask": "0x1"
 248     },
 249     {
 250         "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
 251         "EventCode": "0xB7, 0xBB",
 252         "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_MISS_LOCAL.DRAM",
 253         "MSRIndex": "0x1a6,0x1a7",
 254         "MSRValue": "0x1f80400040",
 255         "SampleAfterValue": "100003",
 256         "UMask": "0x1"
 257     },
 258     {
 259         "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC  and the data returned from dram.",
 260         "EventCode": "0xB7, 0xBB",
 261         "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.DRAM",
 262         "MSRIndex": "0x1a6,0x1a7",
 263         "MSRValue": "0x300400040",
 264         "SampleAfterValue": "100003",
 265         "UMask": "0x1"
 266     },
 267     {
 268         "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dram.",
 269         "EventCode": "0xB7, 0xBB",
 270         "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.DRAM",
 271         "MSRIndex": "0x1a6,0x1a7",
 272         "MSRValue": "0x300400010",
 273         "SampleAfterValue": "100003",
 274         "UMask": "0x1"
 275     },
 276     {
 277         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the LLC  and the data returned from dram.",
 278         "EventCode": "0xB7, 0xBB",
 279         "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.DRAM",
 280         "MSRIndex": "0x1a6,0x1a7",
 281         "MSRValue": "0x300400020",
 282         "SampleAfterValue": "100003",
 283         "UMask": "0x1"
 284     },
 285     {
 286         "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss the LLC  and the data returned from dram.",
 287         "EventCode": "0xB7, 0xBB",
 288         "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.DRAM",
 289         "MSRIndex": "0x1a6,0x1a7",
 290         "MSRValue": "0x300400200",
 291         "SampleAfterValue": "100003",
 292         "UMask": "0x1"
 293     },
 294     {
 295         "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the LLC  and the data returned from dram.",
 296         "EventCode": "0xB7, 0xBB",
 297         "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.DRAM",
 298         "MSRIndex": "0x1a6,0x1a7",
 299         "MSRValue": "0x300400080",
 300         "SampleAfterValue": "100003",
 301         "UMask": "0x1"
 302     },
 303     {
 304         "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC  and the data returned from dram.",
 305         "EventCode": "0xB7, 0xBB",
 306         "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.DRAM",
 307         "MSRIndex": "0x1a6,0x1a7",
 308         "MSRValue": "0x300400100",
 309         "SampleAfterValue": "100003",
 310         "UMask": "0x1"
 311     },
 312     {
 313         "BriefDescription": "REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
 314         "EventCode": "0xB7, 0xBB",
 315         "EventName": "OFFCORE_RESPONSE.PF_L_DATA_RD.LLC_MISS_LOCAL.DRAM",
 316         "MSRIndex": "0x1a6,0x1a7",
 317         "MSRValue": "0x1f80400080",
 318         "SampleAfterValue": "100003",
 319         "UMask": "0x1"
 320     },
 321     {
 322         "BriefDescription": "REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM",
 323         "EventCode": "0xB7, 0xBB",
 324         "EventName": "OFFCORE_RESPONSE.PF_L_IFETCH.LLC_MISS_LOCAL.DRAM",
 325         "MSRIndex": "0x1a6,0x1a7",
 326         "MSRValue": "0x1f80400200",
 327         "SampleAfterValue": "100003",
 328         "UMask": "0x1"
 329     },
 330     {
 331         "BriefDescription": "Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND.",
 332         "EventCode": "0xBE",
 333         "EventName": "PAGE_WALKS.LLC_MISS",
 334         "SampleAfterValue": "100003",
 335         "UMask": "0x1"
 336     }
 337 ]