3 "BriefDescription": "Unhalted core cycles when the thread is in ring 0.",
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
7 "EventName": "CPL_CYCLES.RING0",
8 "SampleAfterValue": "2000003",
12 "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
14 "CounterHTOff": "0,1,2,3,4,5,6,7",
18 "EventName": "CPL_CYCLES.RING0_TRANS",
19 "SampleAfterValue": "100007",
23 "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.",
25 "CounterHTOff": "0,1,2,3,4,5,6,7",
27 "EventName": "CPL_CYCLES.RING123",
28 "SampleAfterValue": "2000003",
32 "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .",
34 "CounterHTOff": "0,1,2,3,4,5,6,7",
36 "EventName": "HW_PRE_REQ.DL1_MISS",
37 "SampleAfterValue": "2000003",
41 "BriefDescription": "Valid instructions written to IQ per cycle.",
43 "CounterHTOff": "0,1,2,3,4,5,6,7",
45 "EventName": "INSTS_WRITTEN_TO_IQ.INSTS",
46 "SampleAfterValue": "2000003",
50 "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.",
52 "CounterHTOff": "0,1,2,3,4,5,6,7",
54 "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
55 "SampleAfterValue": "2000003",