2 * STM32 ALSA SoC Digital Audio Interface (SPDIF-rx) driver.
4 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
5 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
7 * License terms: GPL V2.0.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
19 #include <linux/clk.h>
20 #include <linux/completion.h>
21 #include <linux/delay.h>
22 #include <linux/module.h>
23 #include <linux/of_platform.h>
24 #include <linux/pinctrl/consumer.h>
25 #include <linux/regmap.h>
26 #include <linux/reset.h>
28 #include <sound/dmaengine_pcm.h>
29 #include <sound/pcm_params.h>
31 /* SPDIF-rx Register Map */
32 #define STM32_SPDIFRX_CR 0x00
33 #define STM32_SPDIFRX_IMR 0x04
34 #define STM32_SPDIFRX_SR 0x08
35 #define STM32_SPDIFRX_IFCR 0x0C
36 #define STM32_SPDIFRX_DR 0x10
37 #define STM32_SPDIFRX_CSR 0x14
38 #define STM32_SPDIFRX_DIR 0x18
40 /* Bit definition for SPDIF_CR register */
41 #define SPDIFRX_CR_SPDIFEN_SHIFT 0
42 #define SPDIFRX_CR_SPDIFEN_MASK GENMASK(1, SPDIFRX_CR_SPDIFEN_SHIFT)
43 #define SPDIFRX_CR_SPDIFENSET(x) ((x) << SPDIFRX_CR_SPDIFEN_SHIFT)
45 #define SPDIFRX_CR_RXDMAEN BIT(2)
46 #define SPDIFRX_CR_RXSTEO BIT(3)
48 #define SPDIFRX_CR_DRFMT_SHIFT 4
49 #define SPDIFRX_CR_DRFMT_MASK GENMASK(5, SPDIFRX_CR_DRFMT_SHIFT)
50 #define SPDIFRX_CR_DRFMTSET(x) ((x) << SPDIFRX_CR_DRFMT_SHIFT)
52 #define SPDIFRX_CR_PMSK BIT(6)
53 #define SPDIFRX_CR_VMSK BIT(7)
54 #define SPDIFRX_CR_CUMSK BIT(8)
55 #define SPDIFRX_CR_PTMSK BIT(9)
56 #define SPDIFRX_CR_CBDMAEN BIT(10)
57 #define SPDIFRX_CR_CHSEL_SHIFT 11
58 #define SPDIFRX_CR_CHSEL BIT(SPDIFRX_CR_CHSEL_SHIFT)
60 #define SPDIFRX_CR_NBTR_SHIFT 12
61 #define SPDIFRX_CR_NBTR_MASK GENMASK(13, SPDIFRX_CR_NBTR_SHIFT)
62 #define SPDIFRX_CR_NBTRSET(x) ((x) << SPDIFRX_CR_NBTR_SHIFT)
64 #define SPDIFRX_CR_WFA BIT(14)
66 #define SPDIFRX_CR_INSEL_SHIFT 16
67 #define SPDIFRX_CR_INSEL_MASK GENMASK(18, PDIFRX_CR_INSEL_SHIFT)
68 #define SPDIFRX_CR_INSELSET(x) ((x) << SPDIFRX_CR_INSEL_SHIFT)
70 #define SPDIFRX_CR_CKSEN_SHIFT 20
71 #define SPDIFRX_CR_CKSEN BIT(20)
72 #define SPDIFRX_CR_CKSBKPEN BIT(21)
74 /* Bit definition for SPDIFRX_IMR register */
75 #define SPDIFRX_IMR_RXNEI BIT(0)
76 #define SPDIFRX_IMR_CSRNEIE BIT(1)
77 #define SPDIFRX_IMR_PERRIE BIT(2)
78 #define SPDIFRX_IMR_OVRIE BIT(3)
79 #define SPDIFRX_IMR_SBLKIE BIT(4)
80 #define SPDIFRX_IMR_SYNCDIE BIT(5)
81 #define SPDIFRX_IMR_IFEIE BIT(6)
83 #define SPDIFRX_XIMR_MASK GENMASK(6, 0)
85 /* Bit definition for SPDIFRX_SR register */
86 #define SPDIFRX_SR_RXNE BIT(0)
87 #define SPDIFRX_SR_CSRNE BIT(1)
88 #define SPDIFRX_SR_PERR BIT(2)
89 #define SPDIFRX_SR_OVR BIT(3)
90 #define SPDIFRX_SR_SBD BIT(4)
91 #define SPDIFRX_SR_SYNCD BIT(5)
92 #define SPDIFRX_SR_FERR BIT(6)
93 #define SPDIFRX_SR_SERR BIT(7)
94 #define SPDIFRX_SR_TERR BIT(8)
96 #define SPDIFRX_SR_WIDTH5_SHIFT 16
97 #define SPDIFRX_SR_WIDTH5_MASK GENMASK(30, PDIFRX_SR_WIDTH5_SHIFT)
98 #define SPDIFRX_SR_WIDTH5SET(x) ((x) << SPDIFRX_SR_WIDTH5_SHIFT)
100 /* Bit definition for SPDIFRX_IFCR register */
101 #define SPDIFRX_IFCR_PERRCF BIT(2)
102 #define SPDIFRX_IFCR_OVRCF BIT(3)
103 #define SPDIFRX_IFCR_SBDCF BIT(4)
104 #define SPDIFRX_IFCR_SYNCDCF BIT(5)
106 #define SPDIFRX_XIFCR_MASK GENMASK(5, 2)
108 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b00) */
109 #define SPDIFRX_DR0_DR_SHIFT 0
110 #define SPDIFRX_DR0_DR_MASK GENMASK(23, SPDIFRX_DR0_DR_SHIFT)
111 #define SPDIFRX_DR0_DRSET(x) ((x) << SPDIFRX_DR0_DR_SHIFT)
113 #define SPDIFRX_DR0_PE BIT(24)
115 #define SPDIFRX_DR0_V BIT(25)
116 #define SPDIFRX_DR0_U BIT(26)
117 #define SPDIFRX_DR0_C BIT(27)
119 #define SPDIFRX_DR0_PT_SHIFT 28
120 #define SPDIFRX_DR0_PT_MASK GENMASK(29, SPDIFRX_DR0_PT_SHIFT)
121 #define SPDIFRX_DR0_PTSET(x) ((x) << SPDIFRX_DR0_PT_SHIFT)
123 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b01) */
124 #define SPDIFRX_DR1_PE BIT(0)
125 #define SPDIFRX_DR1_V BIT(1)
126 #define SPDIFRX_DR1_U BIT(2)
127 #define SPDIFRX_DR1_C BIT(3)
129 #define SPDIFRX_DR1_PT_SHIFT 4
130 #define SPDIFRX_DR1_PT_MASK GENMASK(5, SPDIFRX_DR1_PT_SHIFT)
131 #define SPDIFRX_DR1_PTSET(x) ((x) << SPDIFRX_DR1_PT_SHIFT)
133 #define SPDIFRX_DR1_DR_SHIFT 8
134 #define SPDIFRX_DR1_DR_MASK GENMASK(31, SPDIFRX_DR1_DR_SHIFT)
135 #define SPDIFRX_DR1_DRSET(x) ((x) << SPDIFRX_DR1_DR_SHIFT)
137 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b10) */
138 #define SPDIFRX_DR1_DRNL1_SHIFT 0
139 #define SPDIFRX_DR1_DRNL1_MASK GENMASK(15, SPDIFRX_DR1_DRNL1_SHIFT)
140 #define SPDIFRX_DR1_DRNL1SET(x) ((x) << SPDIFRX_DR1_DRNL1_SHIFT)
142 #define SPDIFRX_DR1_DRNL2_SHIFT 16
143 #define SPDIFRX_DR1_DRNL2_MASK GENMASK(31, SPDIFRX_DR1_DRNL2_SHIFT)
144 #define SPDIFRX_DR1_DRNL2SET(x) ((x) << SPDIFRX_DR1_DRNL2_SHIFT)
146 /* Bit definition for SPDIFRX_CSR register */
147 #define SPDIFRX_CSR_USR_SHIFT 0
148 #define SPDIFRX_CSR_USR_MASK GENMASK(15, SPDIFRX_CSR_USR_SHIFT)
149 #define SPDIFRX_CSR_USRGET(x) (((x) & SPDIFRX_CSR_USR_MASK)\
150 >> SPDIFRX_CSR_USR_SHIFT)
152 #define SPDIFRX_CSR_CS_SHIFT 16
153 #define SPDIFRX_CSR_CS_MASK GENMASK(23, SPDIFRX_CSR_CS_SHIFT)
154 #define SPDIFRX_CSR_CSGET(x) (((x) & SPDIFRX_CSR_CS_MASK)\
155 >> SPDIFRX_CSR_CS_SHIFT)
157 #define SPDIFRX_CSR_SOB BIT(24)
159 /* Bit definition for SPDIFRX_DIR register */
160 #define SPDIFRX_DIR_THI_SHIFT 0
161 #define SPDIFRX_DIR_THI_MASK GENMASK(12, SPDIFRX_DIR_THI_SHIFT)
162 #define SPDIFRX_DIR_THI_SET(x) ((x) << SPDIFRX_DIR_THI_SHIFT)
164 #define SPDIFRX_DIR_TLO_SHIFT 16
165 #define SPDIFRX_DIR_TLO_MASK GENMASK(28, SPDIFRX_DIR_TLO_SHIFT)
166 #define SPDIFRX_DIR_TLO_SET(x) ((x) << SPDIFRX_DIR_TLO_SHIFT)
168 #define SPDIFRX_SPDIFEN_DISABLE 0x0
169 #define SPDIFRX_SPDIFEN_SYNC 0x1
170 #define SPDIFRX_SPDIFEN_ENABLE 0x3
172 #define SPDIFRX_IN1 0x1
173 #define SPDIFRX_IN2 0x2
174 #define SPDIFRX_IN3 0x3
175 #define SPDIFRX_IN4 0x4
176 #define SPDIFRX_IN5 0x5
177 #define SPDIFRX_IN6 0x6
178 #define SPDIFRX_IN7 0x7
179 #define SPDIFRX_IN8 0x8
181 #define SPDIFRX_NBTR_NONE 0x0
182 #define SPDIFRX_NBTR_3 0x1
183 #define SPDIFRX_NBTR_15 0x2
184 #define SPDIFRX_NBTR_63 0x3
186 #define SPDIFRX_DRFMT_RIGHT 0x0
187 #define SPDIFRX_DRFMT_LEFT 0x1
188 #define SPDIFRX_DRFMT_PACKED 0x2
190 /* 192 CS bits in S/PDIF frame. i.e 24 CS bytes */
191 #define SPDIFRX_CS_BYTES_NB 24
192 #define SPDIFRX_UB_BYTES_NB 48
195 * CSR register is retrieved as a 32 bits word
196 * It contains 1 channel status byte and 2 user data bytes
197 * 2 S/PDIF frames are acquired to get all CS/UB bits
199 #define SPDIFRX_CSR_BUF_LENGTH (SPDIFRX_CS_BYTES_NB * 4 * 2)
202 * struct stm32_spdifrx_data - private data of SPDIFRX
203 * @pdev: device data pointer
204 * @base: mmio register base virtual address
205 * @regmap: SPDIFRX register map pointer
206 * @regmap_conf: SPDIFRX register map configuration pointer
207 * @cs_completion: channel status retrieving completion
208 * @kclk: kernel clock feeding the SPDIFRX clock generator
209 * @dma_params: dma configuration data for rx channel
210 * @substream: PCM substream data pointer
211 * @dmab: dma buffer info pointer
212 * @ctrl_chan: dma channel for S/PDIF control bits
213 * @desc:dma async transaction descriptor
214 * @slave_config: dma slave channel runtime config pointer
215 * @phys_addr: SPDIFRX registers physical base address
216 * @lock: synchronization enabling lock
217 * @cs: channel status buffer
218 * @ub: user data buffer
219 * @irq: SPDIFRX interrupt line
220 * @refcount: keep count of opened DMA channels
222 struct stm32_spdifrx_data {
223 struct platform_device *pdev;
225 struct regmap *regmap;
226 const struct regmap_config *regmap_conf;
227 struct completion cs_completion;
229 struct snd_dmaengine_dai_dma_data dma_params;
230 struct snd_pcm_substream *substream;
231 struct snd_dma_buffer *dmab;
232 struct dma_chan *ctrl_chan;
233 struct dma_async_tx_descriptor *desc;
234 struct dma_slave_config slave_config;
235 dma_addr_t phys_addr;
236 spinlock_t lock; /* Sync enabling lock */
237 unsigned char cs[SPDIFRX_CS_BYTES_NB];
238 unsigned char ub[SPDIFRX_UB_BYTES_NB];
243 static void stm32_spdifrx_dma_complete(void *data)
245 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)data;
246 struct platform_device *pdev = spdifrx->pdev;
247 u32 *p_start = (u32 *)spdifrx->dmab->area;
248 u32 *p_end = p_start + (2 * SPDIFRX_CS_BYTES_NB) - 1;
250 u16 *ub_ptr = (short *)spdifrx->ub;
253 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
255 (unsigned int)~SPDIFRX_CR_CBDMAEN);
257 if (!spdifrx->dmab->area)
260 while (ptr <= p_end) {
261 if (*ptr & SPDIFRX_CSR_SOB)
267 dev_err(&pdev->dev, "Start of S/PDIF block not found\n");
271 while (i < SPDIFRX_CS_BYTES_NB) {
272 spdifrx->cs[i] = (unsigned char)SPDIFRX_CSR_CSGET(*ptr);
273 *ub_ptr++ = SPDIFRX_CSR_USRGET(*ptr++);
275 dev_err(&pdev->dev, "Failed to get channel status\n");
281 complete(&spdifrx->cs_completion);
284 static int stm32_spdifrx_dma_ctrl_start(struct stm32_spdifrx_data *spdifrx)
289 spdifrx->desc = dmaengine_prep_slave_single(spdifrx->ctrl_chan,
291 SPDIFRX_CSR_BUF_LENGTH,
297 spdifrx->desc->callback = stm32_spdifrx_dma_complete;
298 spdifrx->desc->callback_param = spdifrx;
299 cookie = dmaengine_submit(spdifrx->desc);
300 err = dma_submit_error(cookie);
304 dma_async_issue_pending(spdifrx->ctrl_chan);
309 static void stm32_spdifrx_dma_ctrl_stop(struct stm32_spdifrx_data *spdifrx)
311 dmaengine_terminate_async(spdifrx->ctrl_chan);
314 static int stm32_spdifrx_start_sync(struct stm32_spdifrx_data *spdifrx)
316 int cr, cr_mask, imr, ret;
319 imr = SPDIFRX_IMR_IFEIE | SPDIFRX_IMR_SYNCDIE | SPDIFRX_IMR_PERRIE;
320 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, imr, imr);
324 spin_lock(&spdifrx->lock);
328 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr);
330 if (!(cr & SPDIFRX_CR_SPDIFEN_MASK)) {
332 * Start sync if SPDIFRX is still in idle state.
333 * SPDIFRX reception enabled when sync done
335 dev_dbg(&spdifrx->pdev->dev, "start synchronization\n");
338 * SPDIFRX configuration:
339 * Wait for activity before starting sync process. This avoid
340 * to issue sync errors when spdif signal is missing on input.
341 * Preamble, CS, user, validity and parity error bits not copied
344 cr = SPDIFRX_CR_WFA | SPDIFRX_CR_PMSK | SPDIFRX_CR_VMSK |
345 SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK | SPDIFRX_CR_RXSTEO;
348 cr |= SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC);
349 cr_mask |= SPDIFRX_CR_SPDIFEN_MASK;
350 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
353 dev_err(&spdifrx->pdev->dev,
354 "Failed to start synchronization\n");
357 spin_unlock(&spdifrx->lock);
362 static void stm32_spdifrx_stop(struct stm32_spdifrx_data *spdifrx)
364 int cr, cr_mask, reg;
366 spin_lock(&spdifrx->lock);
368 if (--spdifrx->refcount) {
369 spin_unlock(&spdifrx->lock);
373 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE);
374 cr_mask = SPDIFRX_CR_SPDIFEN_MASK | SPDIFRX_CR_RXDMAEN;
376 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, cr_mask, cr);
378 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR,
379 SPDIFRX_XIMR_MASK, 0);
381 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR,
382 SPDIFRX_XIFCR_MASK, SPDIFRX_XIFCR_MASK);
384 /* dummy read to clear CSRNE and RXNE in status register */
385 regmap_read(spdifrx->regmap, STM32_SPDIFRX_DR, ®);
386 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CSR, ®);
388 spin_unlock(&spdifrx->lock);
391 static int stm32_spdifrx_dma_ctrl_register(struct device *dev,
392 struct stm32_spdifrx_data *spdifrx)
396 spdifrx->ctrl_chan = dma_request_chan(dev, "rx-ctrl");
397 if (IS_ERR(spdifrx->ctrl_chan)) {
398 dev_err(dev, "dma_request_slave_channel failed\n");
399 return PTR_ERR(spdifrx->ctrl_chan);
402 spdifrx->dmab = devm_kzalloc(dev, sizeof(struct snd_dma_buffer),
407 spdifrx->dmab->dev.type = SNDRV_DMA_TYPE_DEV_IRAM;
408 spdifrx->dmab->dev.dev = dev;
409 ret = snd_dma_alloc_pages(spdifrx->dmab->dev.type, dev,
410 SPDIFRX_CSR_BUF_LENGTH, spdifrx->dmab);
412 dev_err(dev, "snd_dma_alloc_pages returned error %d\n", ret);
416 spdifrx->slave_config.direction = DMA_DEV_TO_MEM;
417 spdifrx->slave_config.src_addr = (dma_addr_t)(spdifrx->phys_addr +
419 spdifrx->slave_config.dst_addr = spdifrx->dmab->addr;
420 spdifrx->slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
421 spdifrx->slave_config.src_maxburst = 1;
423 ret = dmaengine_slave_config(spdifrx->ctrl_chan,
424 &spdifrx->slave_config);
426 dev_err(dev, "dmaengine_slave_config returned error %d\n", ret);
427 spdifrx->ctrl_chan = NULL;
433 static const char * const spdifrx_enum_input[] = {
434 "in0", "in1", "in2", "in3"
437 /* By default CS bits are retrieved from channel A */
438 static const char * const spdifrx_enum_cs_channel[] = {
442 static SOC_ENUM_SINGLE_DECL(ctrl_enum_input,
443 STM32_SPDIFRX_CR, SPDIFRX_CR_INSEL_SHIFT,
446 static SOC_ENUM_SINGLE_DECL(ctrl_enum_cs_channel,
447 STM32_SPDIFRX_CR, SPDIFRX_CR_CHSEL_SHIFT,
448 spdifrx_enum_cs_channel);
450 static int stm32_spdifrx_info(struct snd_kcontrol *kcontrol,
451 struct snd_ctl_elem_info *uinfo)
453 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
459 static int stm32_spdifrx_ub_info(struct snd_kcontrol *kcontrol,
460 struct snd_ctl_elem_info *uinfo)
462 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
468 static int stm32_spdifrx_get_ctrl_data(struct stm32_spdifrx_data *spdifrx)
472 memset(spdifrx->cs, 0, SPDIFRX_CS_BYTES_NB);
473 memset(spdifrx->ub, 0, SPDIFRX_UB_BYTES_NB);
475 pinctrl_pm_select_default_state(&spdifrx->pdev->dev);
477 ret = stm32_spdifrx_dma_ctrl_start(spdifrx);
481 ret = clk_prepare_enable(spdifrx->kclk);
483 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret);
487 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
488 SPDIFRX_CR_CBDMAEN, SPDIFRX_CR_CBDMAEN);
492 ret = stm32_spdifrx_start_sync(spdifrx);
496 if (wait_for_completion_interruptible_timeout(&spdifrx->cs_completion,
497 msecs_to_jiffies(100))
499 dev_dbg(&spdifrx->pdev->dev, "Failed to get control data\n");
503 stm32_spdifrx_stop(spdifrx);
504 stm32_spdifrx_dma_ctrl_stop(spdifrx);
507 clk_disable_unprepare(spdifrx->kclk);
508 pinctrl_pm_select_sleep_state(&spdifrx->pdev->dev);
513 static int stm32_spdifrx_capture_get(struct snd_kcontrol *kcontrol,
514 struct snd_ctl_elem_value *ucontrol)
516 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
517 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
519 stm32_spdifrx_get_ctrl_data(spdifrx);
521 ucontrol->value.iec958.status[0] = spdifrx->cs[0];
522 ucontrol->value.iec958.status[1] = spdifrx->cs[1];
523 ucontrol->value.iec958.status[2] = spdifrx->cs[2];
524 ucontrol->value.iec958.status[3] = spdifrx->cs[3];
525 ucontrol->value.iec958.status[4] = spdifrx->cs[4];
530 static int stm32_spdif_user_bits_get(struct snd_kcontrol *kcontrol,
531 struct snd_ctl_elem_value *ucontrol)
533 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
534 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
536 stm32_spdifrx_get_ctrl_data(spdifrx);
538 ucontrol->value.iec958.status[0] = spdifrx->ub[0];
539 ucontrol->value.iec958.status[1] = spdifrx->ub[1];
540 ucontrol->value.iec958.status[2] = spdifrx->ub[2];
541 ucontrol->value.iec958.status[3] = spdifrx->ub[3];
542 ucontrol->value.iec958.status[4] = spdifrx->ub[4];
547 static struct snd_kcontrol_new stm32_spdifrx_iec_ctrls[] = {
548 /* Channel status control */
550 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
551 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
552 .access = SNDRV_CTL_ELEM_ACCESS_READ |
553 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
554 .info = stm32_spdifrx_info,
555 .get = stm32_spdifrx_capture_get,
557 /* User bits control */
559 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
560 .name = "IEC958 User Bit Capture Default",
561 .access = SNDRV_CTL_ELEM_ACCESS_READ |
562 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
563 .info = stm32_spdifrx_ub_info,
564 .get = stm32_spdif_user_bits_get,
568 static struct snd_kcontrol_new stm32_spdifrx_ctrls[] = {
569 SOC_ENUM("SPDIFRX input", ctrl_enum_input),
570 SOC_ENUM("SPDIFRX CS channel", ctrl_enum_cs_channel),
573 static int stm32_spdifrx_dai_register_ctrls(struct snd_soc_dai *cpu_dai)
577 ret = snd_soc_add_dai_controls(cpu_dai, stm32_spdifrx_iec_ctrls,
578 ARRAY_SIZE(stm32_spdifrx_iec_ctrls));
582 return snd_soc_add_component_controls(cpu_dai->component,
584 ARRAY_SIZE(stm32_spdifrx_ctrls));
587 static int stm32_spdifrx_dai_probe(struct snd_soc_dai *cpu_dai)
589 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(cpu_dai->dev);
591 spdifrx->dma_params.addr = (dma_addr_t)(spdifrx->phys_addr +
593 spdifrx->dma_params.maxburst = 1;
595 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params);
597 return stm32_spdifrx_dai_register_ctrls(cpu_dai);
600 static bool stm32_spdifrx_readable_reg(struct device *dev, unsigned int reg)
603 case STM32_SPDIFRX_CR:
604 case STM32_SPDIFRX_IMR:
605 case STM32_SPDIFRX_SR:
606 case STM32_SPDIFRX_IFCR:
607 case STM32_SPDIFRX_DR:
608 case STM32_SPDIFRX_CSR:
609 case STM32_SPDIFRX_DIR:
616 static bool stm32_spdifrx_volatile_reg(struct device *dev, unsigned int reg)
619 case STM32_SPDIFRX_DR:
620 case STM32_SPDIFRX_CSR:
621 case STM32_SPDIFRX_SR:
622 case STM32_SPDIFRX_DIR:
629 static bool stm32_spdifrx_writeable_reg(struct device *dev, unsigned int reg)
632 case STM32_SPDIFRX_CR:
633 case STM32_SPDIFRX_IMR:
634 case STM32_SPDIFRX_IFCR:
641 static const struct regmap_config stm32_h7_spdifrx_regmap_conf = {
645 .max_register = STM32_SPDIFRX_DIR,
646 .readable_reg = stm32_spdifrx_readable_reg,
647 .volatile_reg = stm32_spdifrx_volatile_reg,
648 .writeable_reg = stm32_spdifrx_writeable_reg,
650 .cache_type = REGCACHE_FLAT,
653 static irqreturn_t stm32_spdifrx_isr(int irq, void *devid)
655 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)devid;
656 struct snd_pcm_substream *substream = spdifrx->substream;
657 struct platform_device *pdev = spdifrx->pdev;
658 unsigned int cr, mask, sr, imr;
660 int err = 0, err_xrun = 0;
662 regmap_read(spdifrx->regmap, STM32_SPDIFRX_SR, &sr);
663 regmap_read(spdifrx->regmap, STM32_SPDIFRX_IMR, &imr);
665 mask = imr & SPDIFRX_XIMR_MASK;
666 /* SERR, TERR, FERR IRQs are generated if IFEIE is set */
667 if (mask & SPDIFRX_IMR_IFEIE)
668 mask |= (SPDIFRX_IMR_IFEIE << 1) | (SPDIFRX_IMR_IFEIE << 2);
672 dev_err(&pdev->dev, "Unexpected IRQ. rflags=%#x, imr=%#x\n",
678 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR,
679 SPDIFRX_XIFCR_MASK, flags);
681 if (flags & SPDIFRX_SR_PERR) {
682 dev_dbg(&pdev->dev, "Parity error\n");
686 if (flags & SPDIFRX_SR_OVR) {
687 dev_dbg(&pdev->dev, "Overrun error\n");
691 if (flags & SPDIFRX_SR_SBD)
692 dev_dbg(&pdev->dev, "Synchronization block detected\n");
694 if (flags & SPDIFRX_SR_SYNCD) {
695 dev_dbg(&pdev->dev, "Synchronization done\n");
698 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_ENABLE);
699 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
700 SPDIFRX_CR_SPDIFEN_MASK, cr);
703 if (flags & SPDIFRX_SR_FERR) {
704 dev_dbg(&pdev->dev, "Frame error\n");
708 if (flags & SPDIFRX_SR_SERR) {
709 dev_dbg(&pdev->dev, "Synchronization error\n");
713 if (flags & SPDIFRX_SR_TERR) {
714 dev_dbg(&pdev->dev, "Timeout error\n");
719 /* SPDIFRX in STATE_STOP. Disable SPDIFRX to clear errors */
720 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE);
721 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
722 SPDIFRX_CR_SPDIFEN_MASK, cr);
725 snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED);
730 if (err_xrun && substream)
731 snd_pcm_stop_xrun(substream);
736 static int stm32_spdifrx_startup(struct snd_pcm_substream *substream,
737 struct snd_soc_dai *cpu_dai)
739 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
742 spdifrx->substream = substream;
744 ret = clk_prepare_enable(spdifrx->kclk);
746 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret);
751 static int stm32_spdifrx_hw_params(struct snd_pcm_substream *substream,
752 struct snd_pcm_hw_params *params,
753 struct snd_soc_dai *cpu_dai)
755 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
756 int data_size = params_width(params);
761 fmt = SPDIFRX_DRFMT_PACKED;
764 fmt = SPDIFRX_DRFMT_LEFT;
767 dev_err(&spdifrx->pdev->dev, "Unexpected data format\n");
772 * Set buswidth to 4 bytes for all data formats.
773 * Packed format: transfer 2 x 2 bytes samples
774 * Left format: transfer 1 x 3 bytes samples + 1 dummy byte
776 spdifrx->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
777 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params);
779 return regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
780 SPDIFRX_CR_DRFMT_MASK,
781 SPDIFRX_CR_DRFMTSET(fmt));
784 static int stm32_spdifrx_trigger(struct snd_pcm_substream *substream, int cmd,
785 struct snd_soc_dai *cpu_dai)
787 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
791 case SNDRV_PCM_TRIGGER_START:
792 case SNDRV_PCM_TRIGGER_RESUME:
793 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
794 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR,
795 SPDIFRX_IMR_OVRIE, SPDIFRX_IMR_OVRIE);
797 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
798 SPDIFRX_CR_RXDMAEN, SPDIFRX_CR_RXDMAEN);
800 ret = stm32_spdifrx_start_sync(spdifrx);
802 case SNDRV_PCM_TRIGGER_SUSPEND:
803 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
804 case SNDRV_PCM_TRIGGER_STOP:
805 stm32_spdifrx_stop(spdifrx);
814 static void stm32_spdifrx_shutdown(struct snd_pcm_substream *substream,
815 struct snd_soc_dai *cpu_dai)
817 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
819 spdifrx->substream = NULL;
820 clk_disable_unprepare(spdifrx->kclk);
823 static const struct snd_soc_dai_ops stm32_spdifrx_pcm_dai_ops = {
824 .startup = stm32_spdifrx_startup,
825 .hw_params = stm32_spdifrx_hw_params,
826 .trigger = stm32_spdifrx_trigger,
827 .shutdown = stm32_spdifrx_shutdown,
830 static struct snd_soc_dai_driver stm32_spdifrx_dai[] = {
832 .probe = stm32_spdifrx_dai_probe,
834 .stream_name = "CPU-Capture",
837 .rates = SNDRV_PCM_RATE_8000_192000,
838 .formats = SNDRV_PCM_FMTBIT_S32_LE |
839 SNDRV_PCM_FMTBIT_S16_LE,
841 .ops = &stm32_spdifrx_pcm_dai_ops,
845 static const struct snd_pcm_hardware stm32_spdifrx_pcm_hw = {
846 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
847 .buffer_bytes_max = 8 * PAGE_SIZE,
848 .period_bytes_min = 1024,
849 .period_bytes_max = 4 * PAGE_SIZE,
854 static const struct snd_soc_component_driver stm32_spdifrx_component = {
855 .name = "stm32-spdifrx",
858 static const struct snd_dmaengine_pcm_config stm32_spdifrx_pcm_config = {
859 .pcm_hardware = &stm32_spdifrx_pcm_hw,
860 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
863 static const struct of_device_id stm32_spdifrx_ids[] = {
865 .compatible = "st,stm32h7-spdifrx",
866 .data = &stm32_h7_spdifrx_regmap_conf
871 static int stm32_spdifrx_parse_of(struct platform_device *pdev,
872 struct stm32_spdifrx_data *spdifrx)
874 struct device_node *np = pdev->dev.of_node;
875 const struct of_device_id *of_id;
876 struct resource *res;
881 of_id = of_match_device(stm32_spdifrx_ids, &pdev->dev);
883 spdifrx->regmap_conf =
884 (const struct regmap_config *)of_id->data;
888 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
889 spdifrx->base = devm_ioremap_resource(&pdev->dev, res);
890 if (IS_ERR(spdifrx->base))
891 return PTR_ERR(spdifrx->base);
893 spdifrx->phys_addr = res->start;
895 spdifrx->kclk = devm_clk_get(&pdev->dev, "kclk");
896 if (IS_ERR(spdifrx->kclk)) {
897 dev_err(&pdev->dev, "Could not get kclk\n");
898 return PTR_ERR(spdifrx->kclk);
901 spdifrx->irq = platform_get_irq(pdev, 0);
902 if (spdifrx->irq < 0) {
903 dev_err(&pdev->dev, "No irq for node %s\n", pdev->name);
910 static int stm32_spdifrx_probe(struct platform_device *pdev)
912 struct stm32_spdifrx_data *spdifrx;
913 struct reset_control *rst;
914 const struct snd_dmaengine_pcm_config *pcm_config = NULL;
917 spdifrx = devm_kzalloc(&pdev->dev, sizeof(*spdifrx), GFP_KERNEL);
921 spdifrx->pdev = pdev;
922 init_completion(&spdifrx->cs_completion);
923 spin_lock_init(&spdifrx->lock);
925 platform_set_drvdata(pdev, spdifrx);
927 ret = stm32_spdifrx_parse_of(pdev, spdifrx);
931 spdifrx->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "kclk",
933 spdifrx->regmap_conf);
934 if (IS_ERR(spdifrx->regmap)) {
935 dev_err(&pdev->dev, "Regmap init failed\n");
936 return PTR_ERR(spdifrx->regmap);
939 ret = devm_request_irq(&pdev->dev, spdifrx->irq, stm32_spdifrx_isr, 0,
940 dev_name(&pdev->dev), spdifrx);
942 dev_err(&pdev->dev, "IRQ request returned %d\n", ret);
946 rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
948 reset_control_assert(rst);
950 reset_control_deassert(rst);
953 ret = devm_snd_soc_register_component(&pdev->dev,
954 &stm32_spdifrx_component,
956 ARRAY_SIZE(stm32_spdifrx_dai));
960 ret = stm32_spdifrx_dma_ctrl_register(&pdev->dev, spdifrx);
964 pcm_config = &stm32_spdifrx_pcm_config;
965 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, pcm_config, 0);
967 dev_err(&pdev->dev, "PCM DMA register returned %d\n", ret);
974 if (!IS_ERR(spdifrx->ctrl_chan))
975 dma_release_channel(spdifrx->ctrl_chan);
977 snd_dma_free_pages(spdifrx->dmab);
982 static int stm32_spdifrx_remove(struct platform_device *pdev)
984 struct stm32_spdifrx_data *spdifrx = platform_get_drvdata(pdev);
986 if (spdifrx->ctrl_chan)
987 dma_release_channel(spdifrx->ctrl_chan);
990 snd_dma_free_pages(spdifrx->dmab);
995 MODULE_DEVICE_TABLE(of, stm32_spdifrx_ids);
997 #ifdef CONFIG_PM_SLEEP
998 static int stm32_spdifrx_suspend(struct device *dev)
1000 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev);
1002 regcache_cache_only(spdifrx->regmap, true);
1003 regcache_mark_dirty(spdifrx->regmap);
1008 static int stm32_spdifrx_resume(struct device *dev)
1010 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev);
1012 regcache_cache_only(spdifrx->regmap, false);
1014 return regcache_sync(spdifrx->regmap);
1016 #endif /* CONFIG_PM_SLEEP */
1018 static const struct dev_pm_ops stm32_spdifrx_pm_ops = {
1019 SET_SYSTEM_SLEEP_PM_OPS(stm32_spdifrx_suspend, stm32_spdifrx_resume)
1022 static struct platform_driver stm32_spdifrx_driver = {
1024 .name = "st,stm32-spdifrx",
1025 .of_match_table = stm32_spdifrx_ids,
1026 .pm = &stm32_spdifrx_pm_ops,
1028 .probe = stm32_spdifrx_probe,
1029 .remove = stm32_spdifrx_remove,
1032 module_platform_driver(stm32_spdifrx_driver);
1034 MODULE_DESCRIPTION("STM32 Soc spdifrx Interface");
1035 MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>");
1036 MODULE_ALIAS("platform:stm32-spdifrx");
1037 MODULE_LICENSE("GPL v2");