2 * rt5665.c -- RT5665/RT5658 ALSA SoC audio codec driver
4 * Copyright 2016 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
17 #include <linux/i2c.h>
18 #include <linux/platform_device.h>
19 #include <linux/spi/spi.h>
20 #include <linux/acpi.h>
21 #include <linux/gpio.h>
22 #include <linux/of_gpio.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/mutex.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/jack.h>
29 #include <sound/soc.h>
30 #include <sound/soc-dapm.h>
31 #include <sound/initval.h>
32 #include <sound/tlv.h>
33 #include <sound/rt5665.h>
38 #define RT5665_NUM_SUPPLIES 3
40 static const char *rt5665_supply_names[RT5665_NUM_SUPPLIES] = {
47 struct snd_soc_codec *codec;
48 struct rt5665_platform_data pdata;
49 struct regmap *regmap;
50 struct gpio_desc *gpiod_ldo1_en;
51 struct gpio_desc *gpiod_reset;
52 struct snd_soc_jack *hs_jack;
53 struct regulator_bulk_data supplies[RT5665_NUM_SUPPLIES];
54 struct delayed_work jack_detect_work;
55 struct delayed_work calibrate_work;
56 struct delayed_work jd_check_work;
57 struct mutex calibrate_mutex;
61 int lrck[RT5665_AIFS];
62 int bclk[RT5665_AIFS];
63 int master[RT5665_AIFS];
71 int irq_work_delay_time;
72 unsigned int sar_adc_value;
75 static const struct reg_default rt5665_reg[] = {
466 static bool rt5665_volatile_register(struct device *dev, unsigned int reg)
470 case RT5665_EJD_CTRL_2:
471 case RT5665_GPIO_STA:
472 case RT5665_INT_ST_1:
473 case RT5665_IL_CMD_1:
474 case RT5665_4BTN_IL_CMD_1:
475 case RT5665_PSV_IL_CMD_1:
476 case RT5665_AJD1_CTRL:
477 case RT5665_JD_CTRL_3:
478 case RT5665_STO_NG2_CTRL_1:
479 case RT5665_SAR_IL_CMD_4:
480 case RT5665_DEVICE_ID:
481 case RT5665_STO1_DAC_SIL_DET ... RT5665_STO2_DAC_SIL_DET:
482 case RT5665_MONO_AMP_CALIB_STA1 ... RT5665_MONO_AMP_CALIB_STA6:
483 case RT5665_HP_IMP_SENS_CTRL_12 ... RT5665_HP_IMP_SENS_CTRL_15:
484 case RT5665_HP_CALIB_STA_1 ... RT5665_HP_CALIB_STA_11:
491 static bool rt5665_readable_register(struct device *dev, unsigned int reg)
495 case RT5665_VENDOR_ID:
496 case RT5665_VENDOR_ID_1:
497 case RT5665_DEVICE_ID:
499 case RT5665_HP_CTRL_1:
500 case RT5665_HP_CTRL_2:
501 case RT5665_MONO_OUT:
502 case RT5665_HPL_GAIN:
503 case RT5665_HPR_GAIN:
504 case RT5665_MONO_GAIN:
505 case RT5665_CAL_BST_CTRL:
506 case RT5665_CBJ_BST_CTRL:
509 case RT5665_INL1_INR1_VOL:
510 case RT5665_EJD_CTRL_1:
511 case RT5665_EJD_CTRL_2:
512 case RT5665_EJD_CTRL_3:
513 case RT5665_EJD_CTRL_4:
514 case RT5665_EJD_CTRL_5:
515 case RT5665_EJD_CTRL_6:
516 case RT5665_EJD_CTRL_7:
517 case RT5665_DAC2_CTRL:
518 case RT5665_DAC2_DIG_VOL:
519 case RT5665_DAC1_DIG_VOL:
520 case RT5665_DAC3_DIG_VOL:
521 case RT5665_DAC3_CTRL:
522 case RT5665_STO1_ADC_DIG_VOL:
523 case RT5665_MONO_ADC_DIG_VOL:
524 case RT5665_STO2_ADC_DIG_VOL:
525 case RT5665_STO1_ADC_BOOST:
526 case RT5665_MONO_ADC_BOOST:
527 case RT5665_STO2_ADC_BOOST:
528 case RT5665_HP_IMP_GAIN_1:
529 case RT5665_HP_IMP_GAIN_2:
530 case RT5665_STO1_ADC_MIXER:
531 case RT5665_MONO_ADC_MIXER:
532 case RT5665_STO2_ADC_MIXER:
533 case RT5665_AD_DA_MIXER:
534 case RT5665_STO1_DAC_MIXER:
535 case RT5665_MONO_DAC_MIXER:
536 case RT5665_STO2_DAC_MIXER:
537 case RT5665_A_DAC1_MUX:
538 case RT5665_A_DAC2_MUX:
539 case RT5665_DIG_INF2_DATA:
540 case RT5665_DIG_INF3_DATA:
541 case RT5665_PDM_OUT_CTRL:
542 case RT5665_PDM_DATA_CTRL_1:
543 case RT5665_PDM_DATA_CTRL_2:
544 case RT5665_PDM_DATA_CTRL_3:
545 case RT5665_PDM_DATA_CTRL_4:
546 case RT5665_REC1_GAIN:
547 case RT5665_REC1_L1_MIXER:
548 case RT5665_REC1_L2_MIXER:
549 case RT5665_REC1_R1_MIXER:
550 case RT5665_REC1_R2_MIXER:
551 case RT5665_REC2_GAIN:
552 case RT5665_REC2_L1_MIXER:
553 case RT5665_REC2_L2_MIXER:
554 case RT5665_REC2_R1_MIXER:
555 case RT5665_REC2_R2_MIXER:
557 case RT5665_ALC_BACK_GAIN:
558 case RT5665_MONOMIX_GAIN:
559 case RT5665_MONOMIX_IN_GAIN:
560 case RT5665_OUT_L_GAIN:
561 case RT5665_OUT_L_MIXER:
562 case RT5665_OUT_R_GAIN:
563 case RT5665_OUT_R_MIXER:
564 case RT5665_LOUT_MIXER:
565 case RT5665_PWR_DIG_1:
566 case RT5665_PWR_DIG_2:
567 case RT5665_PWR_ANLG_1:
568 case RT5665_PWR_ANLG_2:
569 case RT5665_PWR_ANLG_3:
570 case RT5665_PWR_MIXER:
573 case RT5665_HPF_CTRL1:
574 case RT5665_DMIC_CTRL_1:
575 case RT5665_DMIC_CTRL_2:
576 case RT5665_I2S1_SDP:
577 case RT5665_I2S2_SDP:
578 case RT5665_I2S3_SDP:
579 case RT5665_ADDA_CLK_1:
580 case RT5665_ADDA_CLK_2:
581 case RT5665_I2S1_F_DIV_CTRL_1:
582 case RT5665_I2S1_F_DIV_CTRL_2:
583 case RT5665_TDM_CTRL_1:
584 case RT5665_TDM_CTRL_2:
585 case RT5665_TDM_CTRL_3:
586 case RT5665_TDM_CTRL_4:
587 case RT5665_TDM_CTRL_5:
588 case RT5665_TDM_CTRL_6:
589 case RT5665_TDM_CTRL_7:
590 case RT5665_TDM_CTRL_8:
592 case RT5665_PLL_CTRL_1:
593 case RT5665_PLL_CTRL_2:
606 case RT5665_HP_CHARGE_PUMP_1:
607 case RT5665_HP_CHARGE_PUMP_2:
608 case RT5665_MICBIAS_1:
609 case RT5665_MICBIAS_2:
613 case RT5665_RC_CLK_CTRL:
614 case RT5665_I2S_M_CLK_CTRL_1:
615 case RT5665_I2S2_F_DIV_CTRL_1:
616 case RT5665_I2S2_F_DIV_CTRL_2:
617 case RT5665_I2S3_F_DIV_CTRL_1:
618 case RT5665_I2S3_F_DIV_CTRL_2:
619 case RT5665_EQ_CTRL_1:
620 case RT5665_EQ_CTRL_2:
621 case RT5665_IRQ_CTRL_1:
622 case RT5665_IRQ_CTRL_2:
623 case RT5665_IRQ_CTRL_3:
624 case RT5665_IRQ_CTRL_4:
625 case RT5665_IRQ_CTRL_5:
626 case RT5665_IRQ_CTRL_6:
627 case RT5665_INT_ST_1:
628 case RT5665_GPIO_CTRL_1:
629 case RT5665_GPIO_CTRL_2:
630 case RT5665_GPIO_CTRL_3:
631 case RT5665_GPIO_CTRL_4:
632 case RT5665_GPIO_STA:
633 case RT5665_HP_AMP_DET_CTRL_1:
634 case RT5665_HP_AMP_DET_CTRL_2:
635 case RT5665_MID_HP_AMP_DET:
636 case RT5665_LOW_HP_AMP_DET:
637 case RT5665_SV_ZCD_1:
638 case RT5665_SV_ZCD_2:
639 case RT5665_IL_CMD_1:
640 case RT5665_IL_CMD_2:
641 case RT5665_IL_CMD_3:
642 case RT5665_IL_CMD_4:
643 case RT5665_4BTN_IL_CMD_1:
644 case RT5665_4BTN_IL_CMD_2:
645 case RT5665_4BTN_IL_CMD_3:
646 case RT5665_PSV_IL_CMD_1:
647 case RT5665_ADC_STO1_HP_CTRL_1:
648 case RT5665_ADC_STO1_HP_CTRL_2:
649 case RT5665_ADC_MONO_HP_CTRL_1:
650 case RT5665_ADC_MONO_HP_CTRL_2:
651 case RT5665_ADC_STO2_HP_CTRL_1:
652 case RT5665_ADC_STO2_HP_CTRL_2:
653 case RT5665_AJD1_CTRL:
656 case RT5665_JD_CTRL_1:
657 case RT5665_JD_CTRL_2:
658 case RT5665_JD_CTRL_3:
659 case RT5665_DIG_MISC:
662 case RT5665_DAC_ADC_DIG_VOL1:
663 case RT5665_DAC_ADC_DIG_VOL2:
664 case RT5665_BIAS_CUR_CTRL_1:
665 case RT5665_BIAS_CUR_CTRL_2:
666 case RT5665_BIAS_CUR_CTRL_3:
667 case RT5665_BIAS_CUR_CTRL_4:
668 case RT5665_BIAS_CUR_CTRL_5:
669 case RT5665_BIAS_CUR_CTRL_6:
670 case RT5665_BIAS_CUR_CTRL_7:
671 case RT5665_BIAS_CUR_CTRL_8:
672 case RT5665_BIAS_CUR_CTRL_9:
673 case RT5665_BIAS_CUR_CTRL_10:
674 case RT5665_VREF_REC_OP_FB_CAP_CTRL:
675 case RT5665_CHARGE_PUMP_1:
676 case RT5665_DIG_IN_CTRL_1:
677 case RT5665_DIG_IN_CTRL_2:
678 case RT5665_PAD_DRIVING_CTRL:
679 case RT5665_SOFT_RAMP_DEPOP:
681 case RT5665_CHOP_DAC:
682 case RT5665_CHOP_ADC:
683 case RT5665_CALIB_ADC_CTRL:
684 case RT5665_VOL_TEST:
685 case RT5665_TEST_MODE_CTRL_1:
686 case RT5665_TEST_MODE_CTRL_2:
687 case RT5665_TEST_MODE_CTRL_3:
688 case RT5665_TEST_MODE_CTRL_4:
689 case RT5665_BASSBACK_CTRL:
690 case RT5665_STO_NG2_CTRL_1:
691 case RT5665_STO_NG2_CTRL_2:
692 case RT5665_STO_NG2_CTRL_3:
693 case RT5665_STO_NG2_CTRL_4:
694 case RT5665_STO_NG2_CTRL_5:
695 case RT5665_STO_NG2_CTRL_6:
696 case RT5665_STO_NG2_CTRL_7:
697 case RT5665_STO_NG2_CTRL_8:
698 case RT5665_MONO_NG2_CTRL_1:
699 case RT5665_MONO_NG2_CTRL_2:
700 case RT5665_MONO_NG2_CTRL_3:
701 case RT5665_MONO_NG2_CTRL_4:
702 case RT5665_MONO_NG2_CTRL_5:
703 case RT5665_MONO_NG2_CTRL_6:
704 case RT5665_STO1_DAC_SIL_DET:
705 case RT5665_MONOL_DAC_SIL_DET:
706 case RT5665_MONOR_DAC_SIL_DET:
707 case RT5665_STO2_DAC_SIL_DET:
708 case RT5665_SIL_PSV_CTRL1:
709 case RT5665_SIL_PSV_CTRL2:
710 case RT5665_SIL_PSV_CTRL3:
711 case RT5665_SIL_PSV_CTRL4:
712 case RT5665_SIL_PSV_CTRL5:
713 case RT5665_SIL_PSV_CTRL6:
714 case RT5665_MONO_AMP_CALIB_CTRL_1:
715 case RT5665_MONO_AMP_CALIB_CTRL_2:
716 case RT5665_MONO_AMP_CALIB_CTRL_3:
717 case RT5665_MONO_AMP_CALIB_CTRL_4:
718 case RT5665_MONO_AMP_CALIB_CTRL_5:
719 case RT5665_MONO_AMP_CALIB_CTRL_6:
720 case RT5665_MONO_AMP_CALIB_CTRL_7:
721 case RT5665_MONO_AMP_CALIB_STA1:
722 case RT5665_MONO_AMP_CALIB_STA2:
723 case RT5665_MONO_AMP_CALIB_STA3:
724 case RT5665_MONO_AMP_CALIB_STA4:
725 case RT5665_MONO_AMP_CALIB_STA6:
726 case RT5665_HP_IMP_SENS_CTRL_01:
727 case RT5665_HP_IMP_SENS_CTRL_02:
728 case RT5665_HP_IMP_SENS_CTRL_03:
729 case RT5665_HP_IMP_SENS_CTRL_04:
730 case RT5665_HP_IMP_SENS_CTRL_05:
731 case RT5665_HP_IMP_SENS_CTRL_06:
732 case RT5665_HP_IMP_SENS_CTRL_07:
733 case RT5665_HP_IMP_SENS_CTRL_08:
734 case RT5665_HP_IMP_SENS_CTRL_09:
735 case RT5665_HP_IMP_SENS_CTRL_10:
736 case RT5665_HP_IMP_SENS_CTRL_11:
737 case RT5665_HP_IMP_SENS_CTRL_12:
738 case RT5665_HP_IMP_SENS_CTRL_13:
739 case RT5665_HP_IMP_SENS_CTRL_14:
740 case RT5665_HP_IMP_SENS_CTRL_15:
741 case RT5665_HP_IMP_SENS_CTRL_16:
742 case RT5665_HP_IMP_SENS_CTRL_17:
743 case RT5665_HP_IMP_SENS_CTRL_18:
744 case RT5665_HP_IMP_SENS_CTRL_19:
745 case RT5665_HP_IMP_SENS_CTRL_20:
746 case RT5665_HP_IMP_SENS_CTRL_21:
747 case RT5665_HP_IMP_SENS_CTRL_22:
748 case RT5665_HP_IMP_SENS_CTRL_23:
749 case RT5665_HP_IMP_SENS_CTRL_24:
750 case RT5665_HP_IMP_SENS_CTRL_25:
751 case RT5665_HP_IMP_SENS_CTRL_26:
752 case RT5665_HP_IMP_SENS_CTRL_27:
753 case RT5665_HP_IMP_SENS_CTRL_28:
754 case RT5665_HP_IMP_SENS_CTRL_29:
755 case RT5665_HP_IMP_SENS_CTRL_30:
756 case RT5665_HP_IMP_SENS_CTRL_31:
757 case RT5665_HP_IMP_SENS_CTRL_32:
758 case RT5665_HP_IMP_SENS_CTRL_33:
759 case RT5665_HP_IMP_SENS_CTRL_34:
760 case RT5665_HP_LOGIC_CTRL_1:
761 case RT5665_HP_LOGIC_CTRL_2:
762 case RT5665_HP_LOGIC_CTRL_3:
763 case RT5665_HP_CALIB_CTRL_1:
764 case RT5665_HP_CALIB_CTRL_2:
765 case RT5665_HP_CALIB_CTRL_3:
766 case RT5665_HP_CALIB_CTRL_4:
767 case RT5665_HP_CALIB_CTRL_5:
768 case RT5665_HP_CALIB_CTRL_6:
769 case RT5665_HP_CALIB_CTRL_7:
770 case RT5665_HP_CALIB_CTRL_9:
771 case RT5665_HP_CALIB_CTRL_10:
772 case RT5665_HP_CALIB_CTRL_11:
773 case RT5665_HP_CALIB_STA_1:
774 case RT5665_HP_CALIB_STA_2:
775 case RT5665_HP_CALIB_STA_3:
776 case RT5665_HP_CALIB_STA_4:
777 case RT5665_HP_CALIB_STA_5:
778 case RT5665_HP_CALIB_STA_6:
779 case RT5665_HP_CALIB_STA_7:
780 case RT5665_HP_CALIB_STA_8:
781 case RT5665_HP_CALIB_STA_9:
782 case RT5665_HP_CALIB_STA_10:
783 case RT5665_HP_CALIB_STA_11:
784 case RT5665_PGM_TAB_CTRL1:
785 case RT5665_PGM_TAB_CTRL2:
786 case RT5665_PGM_TAB_CTRL3:
787 case RT5665_PGM_TAB_CTRL4:
788 case RT5665_PGM_TAB_CTRL5:
789 case RT5665_PGM_TAB_CTRL6:
790 case RT5665_PGM_TAB_CTRL7:
791 case RT5665_PGM_TAB_CTRL8:
792 case RT5665_PGM_TAB_CTRL9:
793 case RT5665_SAR_IL_CMD_1:
794 case RT5665_SAR_IL_CMD_2:
795 case RT5665_SAR_IL_CMD_3:
796 case RT5665_SAR_IL_CMD_4:
797 case RT5665_SAR_IL_CMD_5:
798 case RT5665_SAR_IL_CMD_6:
799 case RT5665_SAR_IL_CMD_7:
800 case RT5665_SAR_IL_CMD_8:
801 case RT5665_SAR_IL_CMD_9:
802 case RT5665_SAR_IL_CMD_10:
803 case RT5665_SAR_IL_CMD_11:
804 case RT5665_SAR_IL_CMD_12:
805 case RT5665_DRC1_CTRL_0:
806 case RT5665_DRC1_CTRL_1:
807 case RT5665_DRC1_CTRL_2:
808 case RT5665_DRC1_CTRL_3:
809 case RT5665_DRC1_CTRL_4:
810 case RT5665_DRC1_CTRL_5:
811 case RT5665_DRC1_CTRL_6:
812 case RT5665_DRC1_HARD_LMT_CTRL_1:
813 case RT5665_DRC1_HARD_LMT_CTRL_2:
814 case RT5665_DRC1_PRIV_1:
815 case RT5665_DRC1_PRIV_2:
816 case RT5665_DRC1_PRIV_3:
817 case RT5665_DRC1_PRIV_4:
818 case RT5665_DRC1_PRIV_5:
819 case RT5665_DRC1_PRIV_6:
820 case RT5665_DRC1_PRIV_7:
821 case RT5665_DRC1_PRIV_8:
822 case RT5665_ALC_PGA_CTRL_1:
823 case RT5665_ALC_PGA_CTRL_2:
824 case RT5665_ALC_PGA_CTRL_3:
825 case RT5665_ALC_PGA_CTRL_4:
826 case RT5665_ALC_PGA_CTRL_5:
827 case RT5665_ALC_PGA_CTRL_6:
828 case RT5665_ALC_PGA_CTRL_7:
829 case RT5665_ALC_PGA_CTRL_8:
830 case RT5665_ALC_PGA_STA_1:
831 case RT5665_ALC_PGA_STA_2:
832 case RT5665_ALC_PGA_STA_3:
833 case RT5665_EQ_AUTO_RCV_CTRL1:
834 case RT5665_EQ_AUTO_RCV_CTRL2:
835 case RT5665_EQ_AUTO_RCV_CTRL3:
836 case RT5665_EQ_AUTO_RCV_CTRL4:
837 case RT5665_EQ_AUTO_RCV_CTRL5:
838 case RT5665_EQ_AUTO_RCV_CTRL6:
839 case RT5665_EQ_AUTO_RCV_CTRL7:
840 case RT5665_EQ_AUTO_RCV_CTRL8:
841 case RT5665_EQ_AUTO_RCV_CTRL9:
842 case RT5665_EQ_AUTO_RCV_CTRL10:
843 case RT5665_EQ_AUTO_RCV_CTRL11:
844 case RT5665_EQ_AUTO_RCV_CTRL12:
845 case RT5665_EQ_AUTO_RCV_CTRL13:
846 case RT5665_ADC_L_EQ_LPF1_A1:
847 case RT5665_R_EQ_LPF1_A1:
848 case RT5665_L_EQ_LPF1_H0:
849 case RT5665_R_EQ_LPF1_H0:
850 case RT5665_L_EQ_BPF1_A1:
851 case RT5665_R_EQ_BPF1_A1:
852 case RT5665_L_EQ_BPF1_A2:
853 case RT5665_R_EQ_BPF1_A2:
854 case RT5665_L_EQ_BPF1_H0:
855 case RT5665_R_EQ_BPF1_H0:
856 case RT5665_L_EQ_BPF2_A1:
857 case RT5665_R_EQ_BPF2_A1:
858 case RT5665_L_EQ_BPF2_A2:
859 case RT5665_R_EQ_BPF2_A2:
860 case RT5665_L_EQ_BPF2_H0:
861 case RT5665_R_EQ_BPF2_H0:
862 case RT5665_L_EQ_BPF3_A1:
863 case RT5665_R_EQ_BPF3_A1:
864 case RT5665_L_EQ_BPF3_A2:
865 case RT5665_R_EQ_BPF3_A2:
866 case RT5665_L_EQ_BPF3_H0:
867 case RT5665_R_EQ_BPF3_H0:
868 case RT5665_L_EQ_BPF4_A1:
869 case RT5665_R_EQ_BPF4_A1:
870 case RT5665_L_EQ_BPF4_A2:
871 case RT5665_R_EQ_BPF4_A2:
872 case RT5665_L_EQ_BPF4_H0:
873 case RT5665_R_EQ_BPF4_H0:
874 case RT5665_L_EQ_HPF1_A1:
875 case RT5665_R_EQ_HPF1_A1:
876 case RT5665_L_EQ_HPF1_H0:
877 case RT5665_R_EQ_HPF1_H0:
878 case RT5665_L_EQ_PRE_VOL:
879 case RT5665_R_EQ_PRE_VOL:
880 case RT5665_L_EQ_POST_VOL:
881 case RT5665_R_EQ_POST_VOL:
882 case RT5665_SCAN_MODE_CTRL:
883 case RT5665_I2C_MODE:
890 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
891 static const DECLARE_TLV_DB_SCALE(mono_vol_tlv, -1400, 150, 0);
892 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
893 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
894 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
895 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
896 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
897 static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
899 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
900 static const DECLARE_TLV_DB_RANGE(bst_tlv,
901 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
902 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
903 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
904 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
905 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
906 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
907 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
910 /* Interface data select */
911 static const char * const rt5665_data_select[] = {
912 "L/R", "R/L", "L/L", "R/R"
915 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_1_01_adc_enum,
916 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT01_SFT, rt5665_data_select);
918 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_1_23_adc_enum,
919 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT23_SFT, rt5665_data_select);
921 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_1_45_adc_enum,
922 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT45_SFT, rt5665_data_select);
924 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_1_67_adc_enum,
925 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT67_SFT, rt5665_data_select);
927 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_2_01_adc_enum,
928 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT01_SFT, rt5665_data_select);
930 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_2_23_adc_enum,
931 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT23_SFT, rt5665_data_select);
933 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_2_45_adc_enum,
934 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT45_SFT, rt5665_data_select);
936 static const SOC_ENUM_SINGLE_DECL(rt5665_if1_2_67_adc_enum,
937 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT67_SFT, rt5665_data_select);
939 static const SOC_ENUM_SINGLE_DECL(rt5665_if2_1_dac_enum,
940 RT5665_DIG_INF2_DATA, RT5665_IF2_1_DAC_SEL_SFT, rt5665_data_select);
942 static const SOC_ENUM_SINGLE_DECL(rt5665_if2_1_adc_enum,
943 RT5665_DIG_INF2_DATA, RT5665_IF2_1_ADC_SEL_SFT, rt5665_data_select);
945 static const SOC_ENUM_SINGLE_DECL(rt5665_if2_2_dac_enum,
946 RT5665_DIG_INF2_DATA, RT5665_IF2_2_DAC_SEL_SFT, rt5665_data_select);
948 static const SOC_ENUM_SINGLE_DECL(rt5665_if2_2_adc_enum,
949 RT5665_DIG_INF2_DATA, RT5665_IF2_2_ADC_SEL_SFT, rt5665_data_select);
951 static const SOC_ENUM_SINGLE_DECL(rt5665_if3_dac_enum,
952 RT5665_DIG_INF3_DATA, RT5665_IF3_DAC_SEL_SFT, rt5665_data_select);
954 static const SOC_ENUM_SINGLE_DECL(rt5665_if3_adc_enum,
955 RT5665_DIG_INF3_DATA, RT5665_IF3_ADC_SEL_SFT, rt5665_data_select);
957 static const struct snd_kcontrol_new rt5665_if1_1_01_adc_swap_mux =
958 SOC_DAPM_ENUM("IF1_1 01 ADC Swap Mux", rt5665_if1_1_01_adc_enum);
960 static const struct snd_kcontrol_new rt5665_if1_1_23_adc_swap_mux =
961 SOC_DAPM_ENUM("IF1_1 23 ADC Swap Mux", rt5665_if1_1_23_adc_enum);
963 static const struct snd_kcontrol_new rt5665_if1_1_45_adc_swap_mux =
964 SOC_DAPM_ENUM("IF1_1 45 ADC Swap Mux", rt5665_if1_1_45_adc_enum);
966 static const struct snd_kcontrol_new rt5665_if1_1_67_adc_swap_mux =
967 SOC_DAPM_ENUM("IF1_1 67 ADC Swap Mux", rt5665_if1_1_67_adc_enum);
969 static const struct snd_kcontrol_new rt5665_if1_2_01_adc_swap_mux =
970 SOC_DAPM_ENUM("IF1_2 01 ADC Swap Mux", rt5665_if1_2_01_adc_enum);
972 static const struct snd_kcontrol_new rt5665_if1_2_23_adc_swap_mux =
973 SOC_DAPM_ENUM("IF1_2 23 ADC1 Swap Mux", rt5665_if1_2_23_adc_enum);
975 static const struct snd_kcontrol_new rt5665_if1_2_45_adc_swap_mux =
976 SOC_DAPM_ENUM("IF1_2 45 ADC1 Swap Mux", rt5665_if1_2_45_adc_enum);
978 static const struct snd_kcontrol_new rt5665_if1_2_67_adc_swap_mux =
979 SOC_DAPM_ENUM("IF1_2 67 ADC1 Swap Mux", rt5665_if1_2_67_adc_enum);
981 static const struct snd_kcontrol_new rt5665_if2_1_dac_swap_mux =
982 SOC_DAPM_ENUM("IF2_1 DAC Swap Source", rt5665_if2_1_dac_enum);
984 static const struct snd_kcontrol_new rt5665_if2_1_adc_swap_mux =
985 SOC_DAPM_ENUM("IF2_1 ADC Swap Source", rt5665_if2_1_adc_enum);
987 static const struct snd_kcontrol_new rt5665_if2_2_dac_swap_mux =
988 SOC_DAPM_ENUM("IF2_2 DAC Swap Source", rt5665_if2_2_dac_enum);
990 static const struct snd_kcontrol_new rt5665_if2_2_adc_swap_mux =
991 SOC_DAPM_ENUM("IF2_2 ADC Swap Source", rt5665_if2_2_adc_enum);
993 static const struct snd_kcontrol_new rt5665_if3_dac_swap_mux =
994 SOC_DAPM_ENUM("IF3 DAC Swap Source", rt5665_if3_dac_enum);
996 static const struct snd_kcontrol_new rt5665_if3_adc_swap_mux =
997 SOC_DAPM_ENUM("IF3 ADC Swap Source", rt5665_if3_adc_enum);
999 static int rt5665_hp_vol_put(struct snd_kcontrol *kcontrol,
1000 struct snd_ctl_elem_value *ucontrol)
1002 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1003 int ret = snd_soc_put_volsw(kcontrol, ucontrol);
1005 if (snd_soc_read(codec, RT5665_STO_NG2_CTRL_1) & RT5665_NG2_EN) {
1006 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
1007 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
1008 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
1009 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
1015 static int rt5665_mono_vol_put(struct snd_kcontrol *kcontrol,
1016 struct snd_ctl_elem_value *ucontrol)
1018 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1019 int ret = snd_soc_put_volsw(kcontrol, ucontrol);
1021 if (snd_soc_read(codec, RT5665_MONO_NG2_CTRL_1) & RT5665_NG2_EN) {
1022 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
1023 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
1024 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
1025 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
1032 * rt5665_sel_asrc_clk_src - select ASRC clock source for a set of filters
1033 * @codec: SoC audio codec device.
1034 * @filter_mask: mask of filters.
1035 * @clk_src: clock source
1037 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5665 can
1038 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1039 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1040 * ASRC function will track i2s clock and generate a corresponding system clock
1041 * for codec. This function provides an API to select the clock source for a
1042 * set of filters specified by the mask. And the codec driver will turn on ASRC
1043 * for these filters if ASRC is selected as their clock source.
1045 int rt5665_sel_asrc_clk_src(struct snd_soc_codec *codec,
1046 unsigned int filter_mask, unsigned int clk_src)
1048 unsigned int asrc2_mask = 0;
1049 unsigned int asrc2_value = 0;
1050 unsigned int asrc3_mask = 0;
1051 unsigned int asrc3_value = 0;
1054 case RT5665_CLK_SEL_SYS:
1055 case RT5665_CLK_SEL_I2S1_ASRC:
1056 case RT5665_CLK_SEL_I2S2_ASRC:
1057 case RT5665_CLK_SEL_I2S3_ASRC:
1058 case RT5665_CLK_SEL_SYS2:
1059 case RT5665_CLK_SEL_SYS3:
1060 case RT5665_CLK_SEL_SYS4:
1067 if (filter_mask & RT5665_DA_STEREO1_FILTER) {
1068 asrc2_mask |= RT5665_DA_STO1_CLK_SEL_MASK;
1069 asrc2_value = (asrc2_value & ~RT5665_DA_STO1_CLK_SEL_MASK)
1070 | (clk_src << RT5665_DA_STO1_CLK_SEL_SFT);
1073 if (filter_mask & RT5665_DA_STEREO2_FILTER) {
1074 asrc2_mask |= RT5665_DA_STO2_CLK_SEL_MASK;
1075 asrc2_value = (asrc2_value & ~RT5665_DA_STO2_CLK_SEL_MASK)
1076 | (clk_src << RT5665_DA_STO2_CLK_SEL_SFT);
1079 if (filter_mask & RT5665_DA_MONO_L_FILTER) {
1080 asrc2_mask |= RT5665_DA_MONOL_CLK_SEL_MASK;
1081 asrc2_value = (asrc2_value & ~RT5665_DA_MONOL_CLK_SEL_MASK)
1082 | (clk_src << RT5665_DA_MONOL_CLK_SEL_SFT);
1085 if (filter_mask & RT5665_DA_MONO_R_FILTER) {
1086 asrc2_mask |= RT5665_DA_MONOR_CLK_SEL_MASK;
1087 asrc2_value = (asrc2_value & ~RT5665_DA_MONOR_CLK_SEL_MASK)
1088 | (clk_src << RT5665_DA_MONOR_CLK_SEL_SFT);
1091 if (filter_mask & RT5665_AD_STEREO1_FILTER) {
1092 asrc3_mask |= RT5665_AD_STO1_CLK_SEL_MASK;
1093 asrc3_value = (asrc2_value & ~RT5665_AD_STO1_CLK_SEL_MASK)
1094 | (clk_src << RT5665_AD_STO1_CLK_SEL_SFT);
1097 if (filter_mask & RT5665_AD_STEREO2_FILTER) {
1098 asrc3_mask |= RT5665_AD_STO2_CLK_SEL_MASK;
1099 asrc3_value = (asrc2_value & ~RT5665_AD_STO2_CLK_SEL_MASK)
1100 | (clk_src << RT5665_AD_STO2_CLK_SEL_SFT);
1103 if (filter_mask & RT5665_AD_MONO_L_FILTER) {
1104 asrc3_mask |= RT5665_AD_MONOL_CLK_SEL_MASK;
1105 asrc3_value = (asrc3_value & ~RT5665_AD_MONOL_CLK_SEL_MASK)
1106 | (clk_src << RT5665_AD_MONOL_CLK_SEL_SFT);
1109 if (filter_mask & RT5665_AD_MONO_R_FILTER) {
1110 asrc3_mask |= RT5665_AD_MONOR_CLK_SEL_MASK;
1111 asrc3_value = (asrc3_value & ~RT5665_AD_MONOR_CLK_SEL_MASK)
1112 | (clk_src << RT5665_AD_MONOR_CLK_SEL_SFT);
1116 snd_soc_update_bits(codec, RT5665_ASRC_2,
1117 asrc2_mask, asrc2_value);
1120 snd_soc_update_bits(codec, RT5665_ASRC_3,
1121 asrc3_mask, asrc3_value);
1125 EXPORT_SYMBOL_GPL(rt5665_sel_asrc_clk_src);
1127 static int rt5665_button_detect(struct snd_soc_codec *codec)
1131 val = snd_soc_read(codec, RT5665_4BTN_IL_CMD_1);
1132 btn_type = val & 0xfff0;
1133 snd_soc_write(codec, RT5665_4BTN_IL_CMD_1, val);
1138 static void rt5665_enable_push_button_irq(struct snd_soc_codec *codec,
1142 snd_soc_write(codec, RT5665_4BTN_IL_CMD_1, 0x000b);
1143 snd_soc_write(codec, RT5665_IL_CMD_1, 0x0048);
1144 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1145 RT5665_4BTN_IL_MASK | RT5665_4BTN_IL_RST_MASK,
1146 RT5665_4BTN_IL_EN | RT5665_4BTN_IL_NOR);
1147 snd_soc_update_bits(codec, RT5665_IRQ_CTRL_3,
1148 RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_EN);
1150 snd_soc_update_bits(codec, RT5665_IRQ_CTRL_3,
1151 RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_DIS);
1152 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1153 RT5665_4BTN_IL_MASK, RT5665_4BTN_IL_DIS);
1154 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1155 RT5665_4BTN_IL_RST_MASK, RT5665_4BTN_IL_RST);
1160 * rt5665_headset_detect - Detect headset.
1161 * @codec: SoC audio codec device.
1162 * @jack_insert: Jack insert or not.
1164 * Detect whether is headset or not when jack inserted.
1166 * Returns detect status.
1168 static int rt5665_headset_detect(struct snd_soc_codec *codec, int jack_insert)
1170 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1171 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1172 unsigned int sar_hs_type, val;
1175 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1176 snd_soc_dapm_sync(dapm);
1178 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100,
1181 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
1183 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
1186 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
1188 usleep_range(10000, 15000);
1189 regmap_read(rt5665->regmap, RT5665_GPIO_STA,
1194 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
1196 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_3, 0x3424);
1197 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0xa291);
1199 rt5665->sar_adc_value = snd_soc_read(rt5665->codec,
1200 RT5665_SAR_IL_CMD_4) & 0x7ff;
1202 sar_hs_type = rt5665->pdata.sar_hs_type ?
1203 rt5665->pdata.sar_hs_type : 729;
1205 if (rt5665->sar_adc_value > sar_hs_type) {
1206 rt5665->jack_type = SND_JACK_HEADSET;
1207 rt5665_enable_push_button_irq(codec, true);
1209 rt5665->jack_type = SND_JACK_HEADPHONE;
1210 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1,
1212 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2,
1214 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1215 snd_soc_dapm_sync(dapm);
1218 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0x2291);
1219 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100, 0);
1220 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1221 snd_soc_dapm_sync(dapm);
1222 if (rt5665->jack_type == SND_JACK_HEADSET)
1223 rt5665_enable_push_button_irq(codec, false);
1224 rt5665->jack_type = 0;
1227 dev_dbg(codec->dev, "jack_type = %d\n", rt5665->jack_type);
1228 return rt5665->jack_type;
1231 static irqreturn_t rt5665_irq(int irq, void *data)
1233 struct rt5665_priv *rt5665 = data;
1235 mod_delayed_work(system_power_efficient_wq,
1236 &rt5665->jack_detect_work, msecs_to_jiffies(250));
1241 static void rt5665_jd_check_handler(struct work_struct *work)
1243 struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
1244 calibrate_work.work);
1246 if (snd_soc_read(rt5665->codec, RT5665_AJD1_CTRL) & 0x0010) {
1248 rt5665->jack_type = rt5665_headset_detect(rt5665->codec, 0);
1250 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
1252 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1253 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1255 schedule_delayed_work(&rt5665->jd_check_work, 500);
1259 int rt5665_set_jack_detect(struct snd_soc_codec *codec,
1260 struct snd_soc_jack *hs_jack)
1262 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1264 switch (rt5665->pdata.jd_src) {
1266 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
1267 RT5665_GP1_PIN_MASK, RT5665_GP1_PIN_IRQ);
1268 regmap_update_bits(rt5665->regmap, RT5665_RC_CLK_CTRL,
1270 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_2,
1271 RT5665_PWR_JD1, RT5665_PWR_JD1);
1272 regmap_update_bits(rt5665->regmap, RT5665_IRQ_CTRL_1, 0x8, 0x8);
1275 case RT5665_JD_NULL:
1279 dev_warn(codec->dev, "Wrong JD source\n");
1283 rt5665->hs_jack = hs_jack;
1287 EXPORT_SYMBOL_GPL(rt5665_set_jack_detect);
1289 static void rt5665_jack_detect_handler(struct work_struct *work)
1291 struct rt5665_priv *rt5665 =
1292 container_of(work, struct rt5665_priv, jack_detect_work.work);
1295 while (!rt5665->codec) {
1296 pr_debug("%s codec = null\n", __func__);
1297 usleep_range(10000, 15000);
1300 while (!rt5665->codec->component.card->instantiated) {
1301 pr_debug("%s\n", __func__);
1302 usleep_range(10000, 15000);
1305 mutex_lock(&rt5665->calibrate_mutex);
1307 val = snd_soc_read(rt5665->codec, RT5665_AJD1_CTRL) & 0x0010;
1310 if (rt5665->jack_type == 0) {
1311 /* jack was out, report jack type */
1313 rt5665_headset_detect(rt5665->codec, 1);
1315 /* jack is already in, report button event */
1316 rt5665->jack_type = SND_JACK_HEADSET;
1317 btn_type = rt5665_button_detect(rt5665->codec);
1319 * rt5665 can report three kinds of button behavior,
1320 * one click, double click and hold. However,
1321 * currently we will report button pressed/released
1322 * event. So all the three button behaviors are
1323 * treated as button pressed.
1329 rt5665->jack_type |= SND_JACK_BTN_0;
1334 rt5665->jack_type |= SND_JACK_BTN_1;
1339 rt5665->jack_type |= SND_JACK_BTN_2;
1344 rt5665->jack_type |= SND_JACK_BTN_3;
1346 case 0x0000: /* unpressed */
1350 dev_err(rt5665->codec->dev,
1351 "Unexpected button code 0x%04x\n",
1358 rt5665->jack_type = rt5665_headset_detect(rt5665->codec, 0);
1361 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
1363 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1364 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1366 if (rt5665->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1367 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1368 schedule_delayed_work(&rt5665->jd_check_work, 0);
1370 cancel_delayed_work_sync(&rt5665->jd_check_work);
1372 mutex_unlock(&rt5665->calibrate_mutex);
1375 static const struct snd_kcontrol_new rt5665_snd_controls[] = {
1376 /* Headphone Output Volume */
1377 SOC_DOUBLE_R_EXT_TLV("Headphone Playback Volume", RT5665_HPL_GAIN,
1378 RT5665_HPR_GAIN, RT5665_G_HP_SFT, 15, 1, snd_soc_get_volsw,
1379 rt5665_hp_vol_put, hp_vol_tlv),
1381 /* Mono Output Volume */
1382 SOC_SINGLE_EXT_TLV("Mono Playback Volume", RT5665_MONO_GAIN,
1383 RT5665_L_VOL_SFT, 15, 1, snd_soc_get_volsw,
1384 rt5665_mono_vol_put, mono_vol_tlv),
1387 SOC_DOUBLE_TLV("OUT Playback Volume", RT5665_LOUT, RT5665_L_VOL_SFT,
1388 RT5665_R_VOL_SFT, 39, 1, out_vol_tlv),
1390 /* DAC Digital Volume */
1391 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5665_DAC1_DIG_VOL,
1392 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
1393 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5665_DAC2_DIG_VOL,
1394 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
1395 SOC_DOUBLE("DAC2 Playback Switch", RT5665_DAC2_CTRL,
1396 RT5665_M_DAC2_L_VOL_SFT, RT5665_M_DAC2_R_VOL_SFT, 1, 1),
1398 /* IN1/IN2/IN3/IN4 Volume */
1399 SOC_SINGLE_TLV("IN1 Boost Volume", RT5665_IN1_IN2,
1400 RT5665_BST1_SFT, 69, 0, in_bst_tlv),
1401 SOC_SINGLE_TLV("IN2 Boost Volume", RT5665_IN1_IN2,
1402 RT5665_BST2_SFT, 69, 0, in_bst_tlv),
1403 SOC_SINGLE_TLV("IN3 Boost Volume", RT5665_IN3_IN4,
1404 RT5665_BST3_SFT, 69, 0, in_bst_tlv),
1405 SOC_SINGLE_TLV("IN4 Boost Volume", RT5665_IN3_IN4,
1406 RT5665_BST4_SFT, 69, 0, in_bst_tlv),
1407 SOC_SINGLE_TLV("CBJ Boost Volume", RT5665_CBJ_BST_CTRL,
1408 RT5665_BST_CBJ_SFT, 8, 0, bst_tlv),
1410 /* INL/INR Volume Control */
1411 SOC_DOUBLE_TLV("IN Capture Volume", RT5665_INL1_INR1_VOL,
1412 RT5665_INL_VOL_SFT, RT5665_INR_VOL_SFT, 31, 1, in_vol_tlv),
1414 /* ADC Digital Volume Control */
1415 SOC_DOUBLE("STO1 ADC Capture Switch", RT5665_STO1_ADC_DIG_VOL,
1416 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1417 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5665_STO1_ADC_DIG_VOL,
1418 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1419 SOC_DOUBLE("Mono ADC Capture Switch", RT5665_MONO_ADC_DIG_VOL,
1420 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1421 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5665_MONO_ADC_DIG_VOL,
1422 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1423 SOC_DOUBLE("STO2 ADC Capture Switch", RT5665_STO2_ADC_DIG_VOL,
1424 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1425 SOC_DOUBLE_TLV("STO2 ADC Capture Volume", RT5665_STO2_ADC_DIG_VOL,
1426 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1428 /* ADC Boost Volume Control */
1429 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5665_STO1_ADC_BOOST,
1430 RT5665_STO1_ADC_L_BST_SFT, RT5665_STO1_ADC_R_BST_SFT,
1433 SOC_DOUBLE_TLV("Mono ADC Boost Gain Volume", RT5665_MONO_ADC_BOOST,
1434 RT5665_MONO_ADC_L_BST_SFT, RT5665_MONO_ADC_R_BST_SFT,
1437 SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5665_STO2_ADC_BOOST,
1438 RT5665_STO2_ADC_L_BST_SFT, RT5665_STO2_ADC_R_BST_SFT,
1443 * set_dmic_clk - Set parameter of dmic.
1446 * @kcontrol: The kcontrol of this widget.
1449 * Choose dmic clock between 1MHz and 3MHz.
1450 * It is better for clock to approximate 3MHz.
1452 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1453 struct snd_kcontrol *kcontrol, int event)
1455 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1456 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1457 int pd, idx = -EINVAL;
1459 pd = rl6231_get_pre_div(rt5665->regmap,
1460 RT5665_ADDA_CLK_1, RT5665_I2S_PD1_SFT);
1461 idx = rl6231_calc_dmic_clk(rt5665->sysclk / pd);
1464 dev_err(codec->dev, "Failed to set DMIC clock\n");
1466 snd_soc_update_bits(codec, RT5665_DMIC_CTRL_1,
1467 RT5665_DMIC_CLK_MASK, idx << RT5665_DMIC_CLK_SFT);
1472 static int rt5665_charge_pump_event(struct snd_soc_dapm_widget *w,
1473 struct snd_kcontrol *kcontrol, int event)
1475 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1478 case SND_SOC_DAPM_PRE_PMU:
1479 snd_soc_update_bits(codec, RT5665_HP_CHARGE_PUMP_1,
1480 RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
1481 RT5665_PM_HP_HV | RT5665_OSW_L_EN);
1483 case SND_SOC_DAPM_POST_PMD:
1484 snd_soc_update_bits(codec, RT5665_HP_CHARGE_PUMP_1,
1485 RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
1486 RT5665_PM_HP_LV | RT5665_OSW_L_DIS);
1495 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
1496 struct snd_soc_dapm_widget *sink)
1499 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1501 val = snd_soc_read(codec, RT5665_GLB_CLK);
1502 val &= RT5665_SCLK_SRC_MASK;
1503 if (val == RT5665_SCLK_SRC_PLL1)
1509 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1510 struct snd_soc_dapm_widget *sink)
1512 unsigned int reg, shift, val;
1513 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1516 case RT5665_ADC_MONO_R_ASRC_SFT:
1517 reg = RT5665_ASRC_3;
1518 shift = RT5665_AD_MONOR_CLK_SEL_SFT;
1520 case RT5665_ADC_MONO_L_ASRC_SFT:
1521 reg = RT5665_ASRC_3;
1522 shift = RT5665_AD_MONOL_CLK_SEL_SFT;
1524 case RT5665_ADC_STO1_ASRC_SFT:
1525 reg = RT5665_ASRC_3;
1526 shift = RT5665_AD_STO1_CLK_SEL_SFT;
1528 case RT5665_ADC_STO2_ASRC_SFT:
1529 reg = RT5665_ASRC_3;
1530 shift = RT5665_AD_STO2_CLK_SEL_SFT;
1532 case RT5665_DAC_MONO_R_ASRC_SFT:
1533 reg = RT5665_ASRC_2;
1534 shift = RT5665_DA_MONOR_CLK_SEL_SFT;
1536 case RT5665_DAC_MONO_L_ASRC_SFT:
1537 reg = RT5665_ASRC_2;
1538 shift = RT5665_DA_MONOL_CLK_SEL_SFT;
1540 case RT5665_DAC_STO1_ASRC_SFT:
1541 reg = RT5665_ASRC_2;
1542 shift = RT5665_DA_STO1_CLK_SEL_SFT;
1544 case RT5665_DAC_STO2_ASRC_SFT:
1545 reg = RT5665_ASRC_2;
1546 shift = RT5665_DA_STO2_CLK_SEL_SFT;
1552 val = (snd_soc_read(codec, reg) >> shift) & 0xf;
1554 case RT5665_CLK_SEL_I2S1_ASRC:
1555 case RT5665_CLK_SEL_I2S2_ASRC:
1556 case RT5665_CLK_SEL_I2S3_ASRC:
1557 /* I2S_Pre_Div1 should be 1 in asrc mode */
1558 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
1559 RT5665_I2S_PD1_MASK, RT5665_I2S_PD1_2);
1568 static const struct snd_kcontrol_new rt5665_sto1_adc_l_mix[] = {
1569 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
1570 RT5665_M_STO1_ADC_L1_SFT, 1, 1),
1571 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
1572 RT5665_M_STO1_ADC_L2_SFT, 1, 1),
1575 static const struct snd_kcontrol_new rt5665_sto1_adc_r_mix[] = {
1576 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
1577 RT5665_M_STO1_ADC_R1_SFT, 1, 1),
1578 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
1579 RT5665_M_STO1_ADC_R2_SFT, 1, 1),
1582 static const struct snd_kcontrol_new rt5665_sto2_adc_l_mix[] = {
1583 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
1584 RT5665_M_STO2_ADC_L1_SFT, 1, 1),
1585 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
1586 RT5665_M_STO2_ADC_L2_SFT, 1, 1),
1589 static const struct snd_kcontrol_new rt5665_sto2_adc_r_mix[] = {
1590 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
1591 RT5665_M_STO2_ADC_R1_SFT, 1, 1),
1592 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
1593 RT5665_M_STO2_ADC_R2_SFT, 1, 1),
1596 static const struct snd_kcontrol_new rt5665_mono_adc_l_mix[] = {
1597 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
1598 RT5665_M_MONO_ADC_L1_SFT, 1, 1),
1599 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
1600 RT5665_M_MONO_ADC_L2_SFT, 1, 1),
1603 static const struct snd_kcontrol_new rt5665_mono_adc_r_mix[] = {
1604 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
1605 RT5665_M_MONO_ADC_R1_SFT, 1, 1),
1606 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
1607 RT5665_M_MONO_ADC_R2_SFT, 1, 1),
1610 static const struct snd_kcontrol_new rt5665_dac_l_mix[] = {
1611 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
1612 RT5665_M_ADCMIX_L_SFT, 1, 1),
1613 SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
1614 RT5665_M_DAC1_L_SFT, 1, 1),
1617 static const struct snd_kcontrol_new rt5665_dac_r_mix[] = {
1618 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
1619 RT5665_M_ADCMIX_R_SFT, 1, 1),
1620 SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
1621 RT5665_M_DAC1_R_SFT, 1, 1),
1624 static const struct snd_kcontrol_new rt5665_sto1_dac_l_mix[] = {
1625 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
1626 RT5665_M_DAC_L1_STO_L_SFT, 1, 1),
1627 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
1628 RT5665_M_DAC_R1_STO_L_SFT, 1, 1),
1629 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
1630 RT5665_M_DAC_L2_STO_L_SFT, 1, 1),
1631 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
1632 RT5665_M_DAC_R2_STO_L_SFT, 1, 1),
1635 static const struct snd_kcontrol_new rt5665_sto1_dac_r_mix[] = {
1636 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
1637 RT5665_M_DAC_L1_STO_R_SFT, 1, 1),
1638 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
1639 RT5665_M_DAC_R1_STO_R_SFT, 1, 1),
1640 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
1641 RT5665_M_DAC_L2_STO_R_SFT, 1, 1),
1642 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
1643 RT5665_M_DAC_R2_STO_R_SFT, 1, 1),
1646 static const struct snd_kcontrol_new rt5665_sto2_dac_l_mix[] = {
1647 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO2_DAC_MIXER,
1648 RT5665_M_DAC_L1_STO2_L_SFT, 1, 1),
1649 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO2_DAC_MIXER,
1650 RT5665_M_DAC_L2_STO2_L_SFT, 1, 1),
1651 SOC_DAPM_SINGLE("DAC L3 Switch", RT5665_STO2_DAC_MIXER,
1652 RT5665_M_DAC_L3_STO2_L_SFT, 1, 1),
1655 static const struct snd_kcontrol_new rt5665_sto2_dac_r_mix[] = {
1656 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO2_DAC_MIXER,
1657 RT5665_M_DAC_R1_STO2_R_SFT, 1, 1),
1658 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO2_DAC_MIXER,
1659 RT5665_M_DAC_R2_STO2_R_SFT, 1, 1),
1660 SOC_DAPM_SINGLE("DAC R3 Switch", RT5665_STO2_DAC_MIXER,
1661 RT5665_M_DAC_R3_STO2_R_SFT, 1, 1),
1664 static const struct snd_kcontrol_new rt5665_mono_dac_l_mix[] = {
1665 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
1666 RT5665_M_DAC_L1_MONO_L_SFT, 1, 1),
1667 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
1668 RT5665_M_DAC_R1_MONO_L_SFT, 1, 1),
1669 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
1670 RT5665_M_DAC_L2_MONO_L_SFT, 1, 1),
1671 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
1672 RT5665_M_DAC_R2_MONO_L_SFT, 1, 1),
1675 static const struct snd_kcontrol_new rt5665_mono_dac_r_mix[] = {
1676 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
1677 RT5665_M_DAC_L1_MONO_R_SFT, 1, 1),
1678 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
1679 RT5665_M_DAC_R1_MONO_R_SFT, 1, 1),
1680 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
1681 RT5665_M_DAC_L2_MONO_R_SFT, 1, 1),
1682 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
1683 RT5665_M_DAC_R2_MONO_R_SFT, 1, 1),
1686 /* Analog Input Mixer */
1687 static const struct snd_kcontrol_new rt5665_rec1_l_mix[] = {
1688 SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC1_L2_MIXER,
1689 RT5665_M_CBJ_RM1_L_SFT, 1, 1),
1690 SOC_DAPM_SINGLE("INL Switch", RT5665_REC1_L2_MIXER,
1691 RT5665_M_INL_RM1_L_SFT, 1, 1),
1692 SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_L2_MIXER,
1693 RT5665_M_INR_RM1_L_SFT, 1, 1),
1694 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_L2_MIXER,
1695 RT5665_M_BST4_RM1_L_SFT, 1, 1),
1696 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_L2_MIXER,
1697 RT5665_M_BST3_RM1_L_SFT, 1, 1),
1698 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_L2_MIXER,
1699 RT5665_M_BST2_RM1_L_SFT, 1, 1),
1700 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_L2_MIXER,
1701 RT5665_M_BST1_RM1_L_SFT, 1, 1),
1704 static const struct snd_kcontrol_new rt5665_rec1_r_mix[] = {
1705 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC1_R2_MIXER,
1706 RT5665_M_AEC_REF_RM1_R_SFT, 1, 1),
1707 SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_R2_MIXER,
1708 RT5665_M_INR_RM1_R_SFT, 1, 1),
1709 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_R2_MIXER,
1710 RT5665_M_BST4_RM1_R_SFT, 1, 1),
1711 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_R2_MIXER,
1712 RT5665_M_BST3_RM1_R_SFT, 1, 1),
1713 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_R2_MIXER,
1714 RT5665_M_BST2_RM1_R_SFT, 1, 1),
1715 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_R2_MIXER,
1716 RT5665_M_BST1_RM1_R_SFT, 1, 1),
1719 static const struct snd_kcontrol_new rt5665_rec2_l_mix[] = {
1720 SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_L2_MIXER,
1721 RT5665_M_INL_RM2_L_SFT, 1, 1),
1722 SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_L2_MIXER,
1723 RT5665_M_INR_RM2_L_SFT, 1, 1),
1724 SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC2_L2_MIXER,
1725 RT5665_M_CBJ_RM2_L_SFT, 1, 1),
1726 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_L2_MIXER,
1727 RT5665_M_BST4_RM2_L_SFT, 1, 1),
1728 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_L2_MIXER,
1729 RT5665_M_BST3_RM2_L_SFT, 1, 1),
1730 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_L2_MIXER,
1731 RT5665_M_BST2_RM2_L_SFT, 1, 1),
1732 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_L2_MIXER,
1733 RT5665_M_BST1_RM2_L_SFT, 1, 1),
1736 static const struct snd_kcontrol_new rt5665_rec2_r_mix[] = {
1737 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC2_R2_MIXER,
1738 RT5665_M_MONOVOL_RM2_R_SFT, 1, 1),
1739 SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_R2_MIXER,
1740 RT5665_M_INL_RM2_R_SFT, 1, 1),
1741 SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_R2_MIXER,
1742 RT5665_M_INR_RM2_R_SFT, 1, 1),
1743 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_R2_MIXER,
1744 RT5665_M_BST4_RM2_R_SFT, 1, 1),
1745 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_R2_MIXER,
1746 RT5665_M_BST3_RM2_R_SFT, 1, 1),
1747 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_R2_MIXER,
1748 RT5665_M_BST2_RM2_R_SFT, 1, 1),
1749 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_R2_MIXER,
1750 RT5665_M_BST1_RM2_R_SFT, 1, 1),
1753 static const struct snd_kcontrol_new rt5665_monovol_mix[] = {
1754 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
1755 RT5665_M_DAC_L2_MM_SFT, 1, 1),
1756 SOC_DAPM_SINGLE("RECMIX2L Switch", RT5665_MONOMIX_IN_GAIN,
1757 RT5665_M_RECMIC2L_MM_SFT, 1, 1),
1758 SOC_DAPM_SINGLE("BST1 Switch", RT5665_MONOMIX_IN_GAIN,
1759 RT5665_M_BST1_MM_SFT, 1, 1),
1760 SOC_DAPM_SINGLE("BST2 Switch", RT5665_MONOMIX_IN_GAIN,
1761 RT5665_M_BST2_MM_SFT, 1, 1),
1762 SOC_DAPM_SINGLE("BST3 Switch", RT5665_MONOMIX_IN_GAIN,
1763 RT5665_M_BST3_MM_SFT, 1, 1),
1766 static const struct snd_kcontrol_new rt5665_out_l_mix[] = {
1767 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_OUT_L_MIXER,
1768 RT5665_M_DAC_L2_OM_L_SFT, 1, 1),
1769 SOC_DAPM_SINGLE("INL Switch", RT5665_OUT_L_MIXER,
1770 RT5665_M_IN_L_OM_L_SFT, 1, 1),
1771 SOC_DAPM_SINGLE("BST1 Switch", RT5665_OUT_L_MIXER,
1772 RT5665_M_BST1_OM_L_SFT, 1, 1),
1773 SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_L_MIXER,
1774 RT5665_M_BST2_OM_L_SFT, 1, 1),
1775 SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_L_MIXER,
1776 RT5665_M_BST3_OM_L_SFT, 1, 1),
1779 static const struct snd_kcontrol_new rt5665_out_r_mix[] = {
1780 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_OUT_R_MIXER,
1781 RT5665_M_DAC_R2_OM_R_SFT, 1, 1),
1782 SOC_DAPM_SINGLE("INR Switch", RT5665_OUT_R_MIXER,
1783 RT5665_M_IN_R_OM_R_SFT, 1, 1),
1784 SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_R_MIXER,
1785 RT5665_M_BST2_OM_R_SFT, 1, 1),
1786 SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_R_MIXER,
1787 RT5665_M_BST3_OM_R_SFT, 1, 1),
1788 SOC_DAPM_SINGLE("BST4 Switch", RT5665_OUT_R_MIXER,
1789 RT5665_M_BST4_OM_R_SFT, 1, 1),
1792 static const struct snd_kcontrol_new rt5665_mono_mix[] = {
1793 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
1794 RT5665_M_DAC_L2_MA_SFT, 1, 1),
1795 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_MONOMIX_IN_GAIN,
1796 RT5665_M_MONOVOL_MA_SFT, 1, 1),
1799 static const struct snd_kcontrol_new rt5665_lout_l_mix[] = {
1800 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_LOUT_MIXER,
1801 RT5665_M_DAC_L2_LM_SFT, 1, 1),
1802 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5665_LOUT_MIXER,
1803 RT5665_M_OV_L_LM_SFT, 1, 1),
1806 static const struct snd_kcontrol_new rt5665_lout_r_mix[] = {
1807 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_LOUT_MIXER,
1808 RT5665_M_DAC_R2_LM_SFT, 1, 1),
1809 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5665_LOUT_MIXER,
1810 RT5665_M_OV_R_LM_SFT, 1, 1),
1814 /*MX-17 [6:4], MX-17 [2:0]*/
1815 static const char * const rt5665_dac2_src[] = {
1816 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "Mono ADC MIX"
1819 static const SOC_ENUM_SINGLE_DECL(
1820 rt5665_dac_l2_enum, RT5665_DAC2_CTRL,
1821 RT5665_DAC_L2_SEL_SFT, rt5665_dac2_src);
1823 static const struct snd_kcontrol_new rt5665_dac_l2_mux =
1824 SOC_DAPM_ENUM("Digital DAC L2 Source", rt5665_dac_l2_enum);
1826 static const SOC_ENUM_SINGLE_DECL(
1827 rt5665_dac_r2_enum, RT5665_DAC2_CTRL,
1828 RT5665_DAC_R2_SEL_SFT, rt5665_dac2_src);
1830 static const struct snd_kcontrol_new rt5665_dac_r2_mux =
1831 SOC_DAPM_ENUM("Digital DAC R2 Source", rt5665_dac_r2_enum);
1834 /*MX-1B [6:4], MX-1B [2:0]*/
1835 static const char * const rt5665_dac3_src[] = {
1836 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "STO2 ADC MIX"
1839 static const SOC_ENUM_SINGLE_DECL(
1840 rt5665_dac_l3_enum, RT5665_DAC3_CTRL,
1841 RT5665_DAC_L3_SEL_SFT, rt5665_dac3_src);
1843 static const struct snd_kcontrol_new rt5665_dac_l3_mux =
1844 SOC_DAPM_ENUM("Digital DAC L3 Source", rt5665_dac_l3_enum);
1846 static const SOC_ENUM_SINGLE_DECL(
1847 rt5665_dac_r3_enum, RT5665_DAC3_CTRL,
1848 RT5665_DAC_R3_SEL_SFT, rt5665_dac3_src);
1850 static const struct snd_kcontrol_new rt5665_dac_r3_mux =
1851 SOC_DAPM_ENUM("Digital DAC R3 Source", rt5665_dac_r3_enum);
1853 /* STO1 ADC1 Source */
1854 /* MX-26 [13] [5] */
1855 static const char * const rt5665_sto1_adc1_src[] = {
1859 static const SOC_ENUM_SINGLE_DECL(
1860 rt5665_sto1_adc1l_enum, RT5665_STO1_ADC_MIXER,
1861 RT5665_STO1_ADC1L_SRC_SFT, rt5665_sto1_adc1_src);
1863 static const struct snd_kcontrol_new rt5665_sto1_adc1l_mux =
1864 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1l_enum);
1866 static const SOC_ENUM_SINGLE_DECL(
1867 rt5665_sto1_adc1r_enum, RT5665_STO1_ADC_MIXER,
1868 RT5665_STO1_ADC1R_SRC_SFT, rt5665_sto1_adc1_src);
1870 static const struct snd_kcontrol_new rt5665_sto1_adc1r_mux =
1871 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1r_enum);
1873 /* STO1 ADC Source */
1874 /* MX-26 [11:10] [3:2] */
1875 static const char * const rt5665_sto1_adc_src[] = {
1876 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
1879 static const SOC_ENUM_SINGLE_DECL(
1880 rt5665_sto1_adcl_enum, RT5665_STO1_ADC_MIXER,
1881 RT5665_STO1_ADCL_SRC_SFT, rt5665_sto1_adc_src);
1883 static const struct snd_kcontrol_new rt5665_sto1_adcl_mux =
1884 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5665_sto1_adcl_enum);
1886 static const SOC_ENUM_SINGLE_DECL(
1887 rt5665_sto1_adcr_enum, RT5665_STO1_ADC_MIXER,
1888 RT5665_STO1_ADCR_SRC_SFT, rt5665_sto1_adc_src);
1890 static const struct snd_kcontrol_new rt5665_sto1_adcr_mux =
1891 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5665_sto1_adcr_enum);
1893 /* STO1 ADC2 Source */
1894 /* MX-26 [12] [4] */
1895 static const char * const rt5665_sto1_adc2_src[] = {
1899 static const SOC_ENUM_SINGLE_DECL(
1900 rt5665_sto1_adc2l_enum, RT5665_STO1_ADC_MIXER,
1901 RT5665_STO1_ADC2L_SRC_SFT, rt5665_sto1_adc2_src);
1903 static const struct snd_kcontrol_new rt5665_sto1_adc2l_mux =
1904 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5665_sto1_adc2l_enum);
1906 static const SOC_ENUM_SINGLE_DECL(
1907 rt5665_sto1_adc2r_enum, RT5665_STO1_ADC_MIXER,
1908 RT5665_STO1_ADC2R_SRC_SFT, rt5665_sto1_adc2_src);
1910 static const struct snd_kcontrol_new rt5665_sto1_adc2r_mux =
1911 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5665_sto1_adc2r_enum);
1913 /* STO1 DMIC Source */
1915 static const char * const rt5665_sto1_dmic_src[] = {
1919 static const SOC_ENUM_SINGLE_DECL(
1920 rt5665_sto1_dmic_enum, RT5665_STO1_ADC_MIXER,
1921 RT5665_STO1_DMIC_SRC_SFT, rt5665_sto1_dmic_src);
1923 static const struct snd_kcontrol_new rt5665_sto1_dmic_mux =
1924 SOC_DAPM_ENUM("Stereo1 DMIC Mux", rt5665_sto1_dmic_enum);
1927 static const char * const rt5665_sto1_dd_l_src[] = {
1928 "STO2 DAC", "MONO DAC"
1931 static const SOC_ENUM_SINGLE_DECL(
1932 rt5665_sto1_dd_l_enum, RT5665_STO1_ADC_MIXER,
1933 RT5665_STO1_DD_L_SRC_SFT, rt5665_sto1_dd_l_src);
1935 static const struct snd_kcontrol_new rt5665_sto1_dd_l_mux =
1936 SOC_DAPM_ENUM("Stereo1 DD L Source", rt5665_sto1_dd_l_enum);
1939 static const char * const rt5665_sto1_dd_r_src[] = {
1940 "STO2 DAC", "MONO DAC", "AEC REF"
1943 static const SOC_ENUM_SINGLE_DECL(
1944 rt5665_sto1_dd_r_enum, RT5665_STO1_ADC_MIXER,
1945 RT5665_STO1_DD_R_SRC_SFT, rt5665_sto1_dd_r_src);
1947 static const struct snd_kcontrol_new rt5665_sto1_dd_r_mux =
1948 SOC_DAPM_ENUM("Stereo1 DD R Source", rt5665_sto1_dd_r_enum);
1950 /* MONO ADC L2 Source */
1952 static const char * const rt5665_mono_adc_l2_src[] = {
1956 static const SOC_ENUM_SINGLE_DECL(
1957 rt5665_mono_adc_l2_enum, RT5665_MONO_ADC_MIXER,
1958 RT5665_MONO_ADC_L2_SRC_SFT, rt5665_mono_adc_l2_src);
1960 static const struct snd_kcontrol_new rt5665_mono_adc_l2_mux =
1961 SOC_DAPM_ENUM("Mono ADC L2 Source", rt5665_mono_adc_l2_enum);
1964 /* MONO ADC L1 Source */
1966 static const char * const rt5665_mono_adc_l1_src[] = {
1970 static const SOC_ENUM_SINGLE_DECL(
1971 rt5665_mono_adc_l1_enum, RT5665_MONO_ADC_MIXER,
1972 RT5665_MONO_ADC_L1_SRC_SFT, rt5665_mono_adc_l1_src);
1974 static const struct snd_kcontrol_new rt5665_mono_adc_l1_mux =
1975 SOC_DAPM_ENUM("Mono ADC L1 Source", rt5665_mono_adc_l1_enum);
1978 static const char * const rt5665_mono_dd_src[] = {
1979 "STO2 DAC", "MONO DAC"
1982 static const SOC_ENUM_SINGLE_DECL(
1983 rt5665_mono_dd_l_enum, RT5665_MONO_ADC_MIXER,
1984 RT5665_MONO_DD_L_SRC_SFT, rt5665_mono_dd_src);
1986 static const struct snd_kcontrol_new rt5665_mono_dd_l_mux =
1987 SOC_DAPM_ENUM("Mono DD L Source", rt5665_mono_dd_l_enum);
1989 static const SOC_ENUM_SINGLE_DECL(
1990 rt5665_mono_dd_r_enum, RT5665_MONO_ADC_MIXER,
1991 RT5665_MONO_DD_R_SRC_SFT, rt5665_mono_dd_src);
1993 static const struct snd_kcontrol_new rt5665_mono_dd_r_mux =
1994 SOC_DAPM_ENUM("Mono DD R Source", rt5665_mono_dd_r_enum);
1996 /* MONO ADC L Source, MONO ADC R Source*/
1997 /* MX-27 [11:10], MX-27 [3:2] */
1998 static const char * const rt5665_mono_adc_src[] = {
1999 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
2002 static const SOC_ENUM_SINGLE_DECL(
2003 rt5665_mono_adc_l_enum, RT5665_MONO_ADC_MIXER,
2004 RT5665_MONO_ADC_L_SRC_SFT, rt5665_mono_adc_src);
2006 static const struct snd_kcontrol_new rt5665_mono_adc_l_mux =
2007 SOC_DAPM_ENUM("Mono ADC L Source", rt5665_mono_adc_l_enum);
2009 static const SOC_ENUM_SINGLE_DECL(
2010 rt5665_mono_adcr_enum, RT5665_MONO_ADC_MIXER,
2011 RT5665_MONO_ADC_R_SRC_SFT, rt5665_mono_adc_src);
2013 static const struct snd_kcontrol_new rt5665_mono_adc_r_mux =
2014 SOC_DAPM_ENUM("Mono ADC R Source", rt5665_mono_adcr_enum);
2016 /* MONO DMIC L Source */
2018 static const char * const rt5665_mono_dmic_l_src[] = {
2019 "DMIC1 L", "DMIC2 L"
2022 static const SOC_ENUM_SINGLE_DECL(
2023 rt5665_mono_dmic_l_enum, RT5665_MONO_ADC_MIXER,
2024 RT5665_MONO_DMIC_L_SRC_SFT, rt5665_mono_dmic_l_src);
2026 static const struct snd_kcontrol_new rt5665_mono_dmic_l_mux =
2027 SOC_DAPM_ENUM("Mono DMIC L Source", rt5665_mono_dmic_l_enum);
2029 /* MONO ADC R2 Source */
2031 static const char * const rt5665_mono_adc_r2_src[] = {
2035 static const SOC_ENUM_SINGLE_DECL(
2036 rt5665_mono_adc_r2_enum, RT5665_MONO_ADC_MIXER,
2037 RT5665_MONO_ADC_R2_SRC_SFT, rt5665_mono_adc_r2_src);
2039 static const struct snd_kcontrol_new rt5665_mono_adc_r2_mux =
2040 SOC_DAPM_ENUM("Mono ADC R2 Source", rt5665_mono_adc_r2_enum);
2042 /* MONO ADC R1 Source */
2044 static const char * const rt5665_mono_adc_r1_src[] = {
2048 static const SOC_ENUM_SINGLE_DECL(
2049 rt5665_mono_adc_r1_enum, RT5665_MONO_ADC_MIXER,
2050 RT5665_MONO_ADC_R1_SRC_SFT, rt5665_mono_adc_r1_src);
2052 static const struct snd_kcontrol_new rt5665_mono_adc_r1_mux =
2053 SOC_DAPM_ENUM("Mono ADC R1 Source", rt5665_mono_adc_r1_enum);
2055 /* MONO DMIC R Source */
2057 static const char * const rt5665_mono_dmic_r_src[] = {
2058 "DMIC1 R", "DMIC2 R"
2061 static const SOC_ENUM_SINGLE_DECL(
2062 rt5665_mono_dmic_r_enum, RT5665_MONO_ADC_MIXER,
2063 RT5665_MONO_DMIC_R_SRC_SFT, rt5665_mono_dmic_r_src);
2065 static const struct snd_kcontrol_new rt5665_mono_dmic_r_mux =
2066 SOC_DAPM_ENUM("Mono DMIC R Source", rt5665_mono_dmic_r_enum);
2069 /* STO2 ADC1 Source */
2070 /* MX-28 [13] [5] */
2071 static const char * const rt5665_sto2_adc1_src[] = {
2075 static const SOC_ENUM_SINGLE_DECL(
2076 rt5665_sto2_adc1l_enum, RT5665_STO2_ADC_MIXER,
2077 RT5665_STO2_ADC1L_SRC_SFT, rt5665_sto2_adc1_src);
2079 static const struct snd_kcontrol_new rt5665_sto2_adc1l_mux =
2080 SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1l_enum);
2082 static const SOC_ENUM_SINGLE_DECL(
2083 rt5665_sto2_adc1r_enum, RT5665_STO2_ADC_MIXER,
2084 RT5665_STO2_ADC1R_SRC_SFT, rt5665_sto2_adc1_src);
2086 static const struct snd_kcontrol_new rt5665_sto2_adc1r_mux =
2087 SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1r_enum);
2089 /* STO2 ADC Source */
2090 /* MX-28 [11:10] [3:2] */
2091 static const char * const rt5665_sto2_adc_src[] = {
2092 "ADC1 L", "ADC1 R", "ADC2 L"
2095 static const SOC_ENUM_SINGLE_DECL(
2096 rt5665_sto2_adcl_enum, RT5665_STO2_ADC_MIXER,
2097 RT5665_STO2_ADCL_SRC_SFT, rt5665_sto2_adc_src);
2099 static const struct snd_kcontrol_new rt5665_sto2_adcl_mux =
2100 SOC_DAPM_ENUM("Stereo2 ADCL Source", rt5665_sto2_adcl_enum);
2102 static const SOC_ENUM_SINGLE_DECL(
2103 rt5665_sto2_adcr_enum, RT5665_STO2_ADC_MIXER,
2104 RT5665_STO2_ADCR_SRC_SFT, rt5665_sto2_adc_src);
2106 static const struct snd_kcontrol_new rt5665_sto2_adcr_mux =
2107 SOC_DAPM_ENUM("Stereo2 ADCR Source", rt5665_sto2_adcr_enum);
2109 /* STO2 ADC2 Source */
2110 /* MX-28 [12] [4] */
2111 static const char * const rt5665_sto2_adc2_src[] = {
2115 static const SOC_ENUM_SINGLE_DECL(
2116 rt5665_sto2_adc2l_enum, RT5665_STO2_ADC_MIXER,
2117 RT5665_STO2_ADC2L_SRC_SFT, rt5665_sto2_adc2_src);
2119 static const struct snd_kcontrol_new rt5665_sto2_adc2l_mux =
2120 SOC_DAPM_ENUM("Stereo2 ADC2L Source", rt5665_sto2_adc2l_enum);
2122 static const SOC_ENUM_SINGLE_DECL(
2123 rt5665_sto2_adc2r_enum, RT5665_STO2_ADC_MIXER,
2124 RT5665_STO2_ADC2R_SRC_SFT, rt5665_sto2_adc2_src);
2126 static const struct snd_kcontrol_new rt5665_sto2_adc2r_mux =
2127 SOC_DAPM_ENUM("Stereo2 ADC2R Source", rt5665_sto2_adc2r_enum);
2129 /* STO2 DMIC Source */
2131 static const char * const rt5665_sto2_dmic_src[] = {
2135 static const SOC_ENUM_SINGLE_DECL(
2136 rt5665_sto2_dmic_enum, RT5665_STO2_ADC_MIXER,
2137 RT5665_STO2_DMIC_SRC_SFT, rt5665_sto2_dmic_src);
2139 static const struct snd_kcontrol_new rt5665_sto2_dmic_mux =
2140 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5665_sto2_dmic_enum);
2143 static const char * const rt5665_sto2_dd_l_src[] = {
2144 "STO2 DAC", "MONO DAC"
2147 static const SOC_ENUM_SINGLE_DECL(
2148 rt5665_sto2_dd_l_enum, RT5665_STO2_ADC_MIXER,
2149 RT5665_STO2_DD_L_SRC_SFT, rt5665_sto2_dd_l_src);
2151 static const struct snd_kcontrol_new rt5665_sto2_dd_l_mux =
2152 SOC_DAPM_ENUM("Stereo2 DD L Source", rt5665_sto2_dd_l_enum);
2155 static const char * const rt5665_sto2_dd_r_src[] = {
2156 "STO2 DAC", "MONO DAC"
2159 static const SOC_ENUM_SINGLE_DECL(
2160 rt5665_sto2_dd_r_enum, RT5665_STO2_ADC_MIXER,
2161 RT5665_STO2_DD_R_SRC_SFT, rt5665_sto2_dd_r_src);
2163 static const struct snd_kcontrol_new rt5665_sto2_dd_r_mux =
2164 SOC_DAPM_ENUM("Stereo2 DD R Source", rt5665_sto2_dd_r_enum);
2166 /* DAC R1 Source, DAC L1 Source*/
2167 /* MX-29 [11:10], MX-29 [9:8]*/
2168 static const char * const rt5665_dac1_src[] = {
2169 "IF1 DAC1", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC"
2172 static const SOC_ENUM_SINGLE_DECL(
2173 rt5665_dac_r1_enum, RT5665_AD_DA_MIXER,
2174 RT5665_DAC1_R_SEL_SFT, rt5665_dac1_src);
2176 static const struct snd_kcontrol_new rt5665_dac_r1_mux =
2177 SOC_DAPM_ENUM("DAC R1 Source", rt5665_dac_r1_enum);
2179 static const SOC_ENUM_SINGLE_DECL(
2180 rt5665_dac_l1_enum, RT5665_AD_DA_MIXER,
2181 RT5665_DAC1_L_SEL_SFT, rt5665_dac1_src);
2183 static const struct snd_kcontrol_new rt5665_dac_l1_mux =
2184 SOC_DAPM_ENUM("DAC L1 Source", rt5665_dac_l1_enum);
2186 /* DAC Digital Mixer L Source, DAC Digital Mixer R Source*/
2187 /* MX-2D [13:12], MX-2D [9:8]*/
2188 static const char * const rt5665_dig_dac_mix_src[] = {
2189 "Stereo1 DAC Mixer", "Stereo2 DAC Mixer", "Mono DAC Mixer"
2192 static const SOC_ENUM_SINGLE_DECL(
2193 rt5665_dig_dac_mixl_enum, RT5665_A_DAC1_MUX,
2194 RT5665_DAC_MIX_L_SFT, rt5665_dig_dac_mix_src);
2196 static const struct snd_kcontrol_new rt5665_dig_dac_mixl_mux =
2197 SOC_DAPM_ENUM("DAC Digital Mixer L Source", rt5665_dig_dac_mixl_enum);
2199 static const SOC_ENUM_SINGLE_DECL(
2200 rt5665_dig_dac_mixr_enum, RT5665_A_DAC1_MUX,
2201 RT5665_DAC_MIX_R_SFT, rt5665_dig_dac_mix_src);
2203 static const struct snd_kcontrol_new rt5665_dig_dac_mixr_mux =
2204 SOC_DAPM_ENUM("DAC Digital Mixer R Source", rt5665_dig_dac_mixr_enum);
2206 /* Analog DAC L1 Source, Analog DAC R1 Source*/
2207 /* MX-2D [5:4], MX-2D [1:0]*/
2208 static const char * const rt5665_alg_dac1_src[] = {
2209 "Stereo1 DAC Mixer", "DAC1", "DMIC1"
2212 static const SOC_ENUM_SINGLE_DECL(
2213 rt5665_alg_dac_l1_enum, RT5665_A_DAC1_MUX,
2214 RT5665_A_DACL1_SFT, rt5665_alg_dac1_src);
2216 static const struct snd_kcontrol_new rt5665_alg_dac_l1_mux =
2217 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5665_alg_dac_l1_enum);
2219 static const SOC_ENUM_SINGLE_DECL(
2220 rt5665_alg_dac_r1_enum, RT5665_A_DAC1_MUX,
2221 RT5665_A_DACR1_SFT, rt5665_alg_dac1_src);
2223 static const struct snd_kcontrol_new rt5665_alg_dac_r1_mux =
2224 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5665_alg_dac_r1_enum);
2226 /* Analog DAC LR Source, Analog DAC R2 Source*/
2227 /* MX-2E [5:4], MX-2E [0]*/
2228 static const char * const rt5665_alg_dac2_src[] = {
2229 "Mono DAC Mixer", "DAC2"
2232 static const SOC_ENUM_SINGLE_DECL(
2233 rt5665_alg_dac_l2_enum, RT5665_A_DAC2_MUX,
2234 RT5665_A_DACL2_SFT, rt5665_alg_dac2_src);
2236 static const struct snd_kcontrol_new rt5665_alg_dac_l2_mux =
2237 SOC_DAPM_ENUM("Analog DAC L2 Source", rt5665_alg_dac_l2_enum);
2239 static const SOC_ENUM_SINGLE_DECL(
2240 rt5665_alg_dac_r2_enum, RT5665_A_DAC2_MUX,
2241 RT5665_A_DACR2_SFT, rt5665_alg_dac2_src);
2243 static const struct snd_kcontrol_new rt5665_alg_dac_r2_mux =
2244 SOC_DAPM_ENUM("Analog DAC R2 Source", rt5665_alg_dac_r2_enum);
2246 /* Interface2 ADC Data Input*/
2248 static const char * const rt5665_if2_1_adc_in_src[] = {
2249 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2250 "IF1 DAC2", "IF2_2 DAC", "IF3 DAC", "DAC1 MIX"
2253 static const SOC_ENUM_SINGLE_DECL(
2254 rt5665_if2_1_adc_in_enum, RT5665_DIG_INF2_DATA,
2255 RT5665_IF3_ADC_IN_SFT, rt5665_if2_1_adc_in_src);
2257 static const struct snd_kcontrol_new rt5665_if2_1_adc_in_mux =
2258 SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_1_adc_in_enum);
2261 static const char * const rt5665_if2_2_adc_in_src[] = {
2262 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2263 "IF1 DAC2", "IF2_1 DAC", "IF3 DAC", "DAC1 MIX"
2266 static const SOC_ENUM_SINGLE_DECL(
2267 rt5665_if2_2_adc_in_enum, RT5665_DIG_INF2_DATA,
2268 RT5665_IF2_2_ADC_IN_SFT, rt5665_if2_2_adc_in_src);
2270 static const struct snd_kcontrol_new rt5665_if2_2_adc_in_mux =
2271 SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_2_adc_in_enum);
2273 /* Interface3 ADC Data Input*/
2275 static const char * const rt5665_if3_adc_in_src[] = {
2276 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2277 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "DAC1 MIX"
2280 static const SOC_ENUM_SINGLE_DECL(
2281 rt5665_if3_adc_in_enum, RT5665_DIG_INF3_DATA,
2282 RT5665_IF3_ADC_IN_SFT, rt5665_if3_adc_in_src);
2284 static const struct snd_kcontrol_new rt5665_if3_adc_in_mux =
2285 SOC_DAPM_ENUM("IF3 ADC IN Source", rt5665_if3_adc_in_enum);
2288 /* MX-31 [11:10] [9:8] */
2289 static const char * const rt5665_pdm_src[] = {
2290 "Stereo1 DAC", "Stereo2 DAC", "Mono DAC"
2293 static const SOC_ENUM_SINGLE_DECL(
2294 rt5665_pdm_l_enum, RT5665_PDM_OUT_CTRL,
2295 RT5665_PDM1_L_SFT, rt5665_pdm_src);
2297 static const struct snd_kcontrol_new rt5665_pdm_l_mux =
2298 SOC_DAPM_ENUM("PDM L Source", rt5665_pdm_l_enum);
2300 static const SOC_ENUM_SINGLE_DECL(
2301 rt5665_pdm_r_enum, RT5665_PDM_OUT_CTRL,
2302 RT5665_PDM1_R_SFT, rt5665_pdm_src);
2304 static const struct snd_kcontrol_new rt5665_pdm_r_mux =
2305 SOC_DAPM_ENUM("PDM R Source", rt5665_pdm_r_enum);
2308 /* I2S1 TDM ADCDAT Source */
2310 static const char * const rt5665_if1_1_adc1_data_src[] = {
2311 "STO1 ADC", "IF2_1 DAC",
2314 static const SOC_ENUM_SINGLE_DECL(
2315 rt5665_if1_1_adc1_data_enum, RT5665_TDM_CTRL_3,
2316 RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_1_adc1_data_src);
2318 static const struct snd_kcontrol_new rt5665_if1_1_adc1_mux =
2319 SOC_DAPM_ENUM("IF1_1 ADC1 Source", rt5665_if1_1_adc1_data_enum);
2322 static const char * const rt5665_if1_1_adc2_data_src[] = {
2323 "STO2 ADC", "IF2_2 DAC",
2326 static const SOC_ENUM_SINGLE_DECL(
2327 rt5665_if1_1_adc2_data_enum, RT5665_TDM_CTRL_3,
2328 RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_1_adc2_data_src);
2330 static const struct snd_kcontrol_new rt5665_if1_1_adc2_mux =
2331 SOC_DAPM_ENUM("IF1_1 ADC2 Source", rt5665_if1_1_adc2_data_enum);
2334 static const char * const rt5665_if1_1_adc3_data_src[] = {
2335 "MONO ADC", "IF3 DAC",
2338 static const SOC_ENUM_SINGLE_DECL(
2339 rt5665_if1_1_adc3_data_enum, RT5665_TDM_CTRL_3,
2340 RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_1_adc3_data_src);
2342 static const struct snd_kcontrol_new rt5665_if1_1_adc3_mux =
2343 SOC_DAPM_ENUM("IF1_1 ADC3 Source", rt5665_if1_1_adc3_data_enum);
2346 static const char * const rt5665_if1_2_adc1_data_src[] = {
2347 "STO1 ADC", "IF1 DAC",
2350 static const SOC_ENUM_SINGLE_DECL(
2351 rt5665_if1_2_adc1_data_enum, RT5665_TDM_CTRL_4,
2352 RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_2_adc1_data_src);
2354 static const struct snd_kcontrol_new rt5665_if1_2_adc1_mux =
2355 SOC_DAPM_ENUM("IF1_2 ADC1 Source", rt5665_if1_2_adc1_data_enum);
2358 static const char * const rt5665_if1_2_adc2_data_src[] = {
2359 "STO2 ADC", "IF2_1 DAC",
2362 static const SOC_ENUM_SINGLE_DECL(
2363 rt5665_if1_2_adc2_data_enum, RT5665_TDM_CTRL_4,
2364 RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_2_adc2_data_src);
2366 static const struct snd_kcontrol_new rt5665_if1_2_adc2_mux =
2367 SOC_DAPM_ENUM("IF1_2 ADC2 Source", rt5665_if1_2_adc2_data_enum);
2370 static const char * const rt5665_if1_2_adc3_data_src[] = {
2371 "MONO ADC", "IF2_2 DAC",
2374 static const SOC_ENUM_SINGLE_DECL(
2375 rt5665_if1_2_adc3_data_enum, RT5665_TDM_CTRL_4,
2376 RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_2_adc3_data_src);
2378 static const struct snd_kcontrol_new rt5665_if1_2_adc3_mux =
2379 SOC_DAPM_ENUM("IF1_2 ADC3 Source", rt5665_if1_2_adc3_data_enum);
2382 static const char * const rt5665_if1_2_adc4_data_src[] = {
2386 static const SOC_ENUM_SINGLE_DECL(
2387 rt5665_if1_2_adc4_data_enum, RT5665_TDM_CTRL_4,
2388 RT5665_IF1_ADC4_SEL_SFT, rt5665_if1_2_adc4_data_src);
2390 static const struct snd_kcontrol_new rt5665_if1_2_adc4_mux =
2391 SOC_DAPM_ENUM("IF1_2 ADC4 Source", rt5665_if1_2_adc4_data_enum);
2393 /* MX-7a[4:0] MX-7b[4:0] */
2394 static const char * const rt5665_tdm_adc_data_src[] = {
2395 "1234", "1243", "1324", "1342", "1432", "1423",
2396 "2134", "2143", "2314", "2341", "2431", "2413",
2397 "3124", "3142", "3214", "3241", "3412", "3421",
2398 "4123", "4132", "4213", "4231", "4312", "4321"
2401 static const SOC_ENUM_SINGLE_DECL(
2402 rt5665_tdm1_adc_data_enum, RT5665_TDM_CTRL_3,
2403 RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
2405 static const struct snd_kcontrol_new rt5665_tdm1_adc_mux =
2406 SOC_DAPM_ENUM("TDM1 ADC Mux", rt5665_tdm1_adc_data_enum);
2408 static const SOC_ENUM_SINGLE_DECL(
2409 rt5665_tdm2_adc_data_enum, RT5665_TDM_CTRL_4,
2410 RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
2412 static const struct snd_kcontrol_new rt5665_tdm2_adc_mux =
2413 SOC_DAPM_ENUM("TDM2 ADCDAT Source", rt5665_tdm2_adc_data_enum);
2415 /* Out Volume Switch */
2416 static const struct snd_kcontrol_new monovol_switch =
2417 SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_VOL_L_SFT, 1, 1);
2419 static const struct snd_kcontrol_new outvol_l_switch =
2420 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_L_SFT, 1, 1);
2422 static const struct snd_kcontrol_new outvol_r_switch =
2423 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_R_SFT, 1, 1);
2426 static const struct snd_kcontrol_new mono_switch =
2427 SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_L_MUTE_SFT, 1, 1);
2429 static const struct snd_kcontrol_new hpo_switch =
2430 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5665_HP_CTRL_2,
2431 RT5665_VOL_L_SFT, 1, 0);
2433 static const struct snd_kcontrol_new lout_l_switch =
2434 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_L_MUTE_SFT, 1, 1);
2436 static const struct snd_kcontrol_new lout_r_switch =
2437 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_R_MUTE_SFT, 1, 1);
2439 static const struct snd_kcontrol_new pdm_l_switch =
2440 SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
2441 RT5665_M_PDM1_L_SFT, 1, 1);
2443 static const struct snd_kcontrol_new pdm_r_switch =
2444 SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
2445 RT5665_M_PDM1_R_SFT, 1, 1);
2447 static int rt5665_mono_event(struct snd_soc_dapm_widget *w,
2448 struct snd_kcontrol *kcontrol, int event)
2450 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2453 case SND_SOC_DAPM_PRE_PMU:
2454 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
2455 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
2456 snd_soc_update_bits(codec, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
2458 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x10, 0x10);
2459 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x20, 0x20);
2462 case SND_SOC_DAPM_POST_PMD:
2463 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x20, 0);
2464 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x10, 0);
2465 snd_soc_update_bits(codec, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
2467 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
2468 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
2479 static int rt5665_hp_event(struct snd_soc_dapm_widget *w,
2480 struct snd_kcontrol *kcontrol, int event)
2482 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2485 case SND_SOC_DAPM_PRE_PMU:
2486 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
2487 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
2488 snd_soc_write(codec, RT5665_HP_LOGIC_CTRL_2, 0x0003);
2491 case SND_SOC_DAPM_POST_PMD:
2492 snd_soc_write(codec, RT5665_HP_LOGIC_CTRL_2, 0x0002);
2493 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
2494 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
2505 static int rt5665_lout_event(struct snd_soc_dapm_widget *w,
2506 struct snd_kcontrol *kcontrol, int event)
2508 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2511 case SND_SOC_DAPM_POST_PMU:
2512 snd_soc_update_bits(codec, RT5665_DEPOP_1,
2513 RT5665_PUMP_EN, RT5665_PUMP_EN);
2516 case SND_SOC_DAPM_PRE_PMD:
2517 snd_soc_update_bits(codec, RT5665_DEPOP_1,
2529 static int set_dmic_power(struct snd_soc_dapm_widget *w,
2530 struct snd_kcontrol *kcontrol, int event)
2533 case SND_SOC_DAPM_POST_PMU:
2534 /*Add delay to avoid pop noise*/
2545 static int rt5655_set_verf(struct snd_soc_dapm_widget *w,
2546 struct snd_kcontrol *kcontrol, int event)
2548 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2551 case SND_SOC_DAPM_PRE_PMU:
2553 case RT5665_PWR_VREF1_BIT:
2554 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2558 case RT5665_PWR_VREF2_BIT:
2559 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2563 case RT5665_PWR_VREF3_BIT:
2564 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2573 case SND_SOC_DAPM_POST_PMU:
2574 usleep_range(15000, 20000);
2576 case RT5665_PWR_VREF1_BIT:
2577 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2578 RT5665_PWR_FV1, RT5665_PWR_FV1);
2581 case RT5665_PWR_VREF2_BIT:
2582 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2583 RT5665_PWR_FV2, RT5665_PWR_FV2);
2586 case RT5665_PWR_VREF3_BIT:
2587 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2588 RT5665_PWR_FV3, RT5665_PWR_FV3);
2604 static const struct snd_soc_dapm_widget rt5665_dapm_widgets[] = {
2605 SND_SOC_DAPM_SUPPLY("LDO2", RT5665_PWR_ANLG_3, RT5665_PWR_LDO2_BIT, 0,
2607 SND_SOC_DAPM_SUPPLY("PLL", RT5665_PWR_ANLG_3, RT5665_PWR_PLL_BIT, 0,
2609 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5665_PWR_VOL,
2610 RT5665_PWR_MIC_DET_BIT, 0, NULL, 0),
2611 SND_SOC_DAPM_SUPPLY("Vref1", RT5665_PWR_ANLG_1, RT5665_PWR_VREF1_BIT, 0,
2612 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2613 SND_SOC_DAPM_SUPPLY("Vref2", RT5665_PWR_ANLG_1, RT5665_PWR_VREF2_BIT, 0,
2614 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2615 SND_SOC_DAPM_SUPPLY("Vref3", RT5665_PWR_ANLG_1, RT5665_PWR_VREF3_BIT, 0,
2616 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2619 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5665_ASRC_1,
2620 RT5665_I2S1_ASRC_SFT, 0, NULL, 0),
2621 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5665_ASRC_1,
2622 RT5665_I2S2_ASRC_SFT, 0, NULL, 0),
2623 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5665_ASRC_1,
2624 RT5665_I2S3_ASRC_SFT, 0, NULL, 0),
2625 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5665_ASRC_1,
2626 RT5665_DAC_STO1_ASRC_SFT, 0, NULL, 0),
2627 SND_SOC_DAPM_SUPPLY_S("DAC STO2 ASRC", 1, RT5665_ASRC_1,
2628 RT5665_DAC_STO2_ASRC_SFT, 0, NULL, 0),
2629 SND_SOC_DAPM_SUPPLY_S("DAC Mono L ASRC", 1, RT5665_ASRC_1,
2630 RT5665_DAC_MONO_L_ASRC_SFT, 0, NULL, 0),
2631 SND_SOC_DAPM_SUPPLY_S("DAC Mono R ASRC", 1, RT5665_ASRC_1,
2632 RT5665_DAC_MONO_R_ASRC_SFT, 0, NULL, 0),
2633 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5665_ASRC_1,
2634 RT5665_ADC_STO1_ASRC_SFT, 0, NULL, 0),
2635 SND_SOC_DAPM_SUPPLY_S("ADC Mono L ASRC", 1, RT5665_ASRC_1,
2636 RT5665_ADC_MONO_L_ASRC_SFT, 0, NULL, 0),
2637 SND_SOC_DAPM_SUPPLY_S("ADC Mono R ASRC", 1, RT5665_ASRC_1,
2638 RT5665_ADC_MONO_R_ASRC_SFT, 0, NULL, 0),
2639 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5665_ASRC_1,
2640 RT5665_DMIC_STO1_ASRC_SFT, 0, NULL, 0),
2641 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5665_ASRC_1,
2642 RT5665_DMIC_STO2_ASRC_SFT, 0, NULL, 0),
2643 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5665_ASRC_1,
2644 RT5665_DMIC_MONO_L_ASRC_SFT, 0, NULL, 0),
2645 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5665_ASRC_1,
2646 RT5665_DMIC_MONO_R_ASRC_SFT, 0, NULL, 0),
2649 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5665_PWR_ANLG_2, RT5665_PWR_MB1_BIT,
2651 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5665_PWR_ANLG_2, RT5665_PWR_MB2_BIT,
2653 SND_SOC_DAPM_SUPPLY("MICBIAS3", RT5665_PWR_ANLG_2, RT5665_PWR_MB3_BIT,
2657 SND_SOC_DAPM_INPUT("DMIC L1"),
2658 SND_SOC_DAPM_INPUT("DMIC R1"),
2659 SND_SOC_DAPM_INPUT("DMIC L2"),
2660 SND_SOC_DAPM_INPUT("DMIC R2"),
2662 SND_SOC_DAPM_INPUT("IN1P"),
2663 SND_SOC_DAPM_INPUT("IN1N"),
2664 SND_SOC_DAPM_INPUT("IN2P"),
2665 SND_SOC_DAPM_INPUT("IN2N"),
2666 SND_SOC_DAPM_INPUT("IN3P"),
2667 SND_SOC_DAPM_INPUT("IN3N"),
2668 SND_SOC_DAPM_INPUT("IN4P"),
2669 SND_SOC_DAPM_INPUT("IN4N"),
2671 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2672 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2674 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2675 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2676 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5665_DMIC_CTRL_1,
2677 RT5665_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2678 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5665_DMIC_CTRL_1,
2679 RT5665_DMIC_2_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2682 SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM,
2684 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM,
2686 SND_SOC_DAPM_PGA("BST3", SND_SOC_NOPM,
2688 SND_SOC_DAPM_PGA("BST4", SND_SOC_NOPM,
2690 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
2692 SND_SOC_DAPM_SUPPLY("BST1 Power", RT5665_PWR_ANLG_2,
2693 RT5665_PWR_BST1_BIT, 0, NULL, 0),
2694 SND_SOC_DAPM_SUPPLY("BST2 Power", RT5665_PWR_ANLG_2,
2695 RT5665_PWR_BST2_BIT, 0, NULL, 0),
2696 SND_SOC_DAPM_SUPPLY("BST3 Power", RT5665_PWR_ANLG_2,
2697 RT5665_PWR_BST3_BIT, 0, NULL, 0),
2698 SND_SOC_DAPM_SUPPLY("BST4 Power", RT5665_PWR_ANLG_2,
2699 RT5665_PWR_BST4_BIT, 0, NULL, 0),
2700 SND_SOC_DAPM_SUPPLY("BST1P Power", RT5665_PWR_ANLG_2,
2701 RT5665_PWR_BST1_P_BIT, 0, NULL, 0),
2702 SND_SOC_DAPM_SUPPLY("BST2P Power", RT5665_PWR_ANLG_2,
2703 RT5665_PWR_BST2_P_BIT, 0, NULL, 0),
2704 SND_SOC_DAPM_SUPPLY("BST3P Power", RT5665_PWR_ANLG_2,
2705 RT5665_PWR_BST3_P_BIT, 0, NULL, 0),
2706 SND_SOC_DAPM_SUPPLY("BST4P Power", RT5665_PWR_ANLG_2,
2707 RT5665_PWR_BST4_P_BIT, 0, NULL, 0),
2708 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5665_PWR_ANLG_3,
2709 RT5665_PWR_CBJ_BIT, 0, NULL, 0),
2713 SND_SOC_DAPM_PGA("INL VOL", RT5665_PWR_VOL, RT5665_PWR_IN_L_BIT,
2715 SND_SOC_DAPM_PGA("INR VOL", RT5665_PWR_VOL, RT5665_PWR_IN_R_BIT,
2719 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5665_rec1_l_mix,
2720 ARRAY_SIZE(rt5665_rec1_l_mix)),
2721 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5665_rec1_r_mix,
2722 ARRAY_SIZE(rt5665_rec1_r_mix)),
2723 SND_SOC_DAPM_MIXER("RECMIX2L", SND_SOC_NOPM, 0, 0, rt5665_rec2_l_mix,
2724 ARRAY_SIZE(rt5665_rec2_l_mix)),
2725 SND_SOC_DAPM_MIXER("RECMIX2R", SND_SOC_NOPM, 0, 0, rt5665_rec2_r_mix,
2726 ARRAY_SIZE(rt5665_rec2_r_mix)),
2727 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5665_PWR_ANLG_2,
2728 RT5665_PWR_RM1_L_BIT, 0, NULL, 0),
2729 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5665_PWR_ANLG_2,
2730 RT5665_PWR_RM1_R_BIT, 0, NULL, 0),
2731 SND_SOC_DAPM_SUPPLY("RECMIX2L Power", RT5665_PWR_MIXER,
2732 RT5665_PWR_RM2_L_BIT, 0, NULL, 0),
2733 SND_SOC_DAPM_SUPPLY("RECMIX2R Power", RT5665_PWR_MIXER,
2734 RT5665_PWR_RM2_R_BIT, 0, NULL, 0),
2737 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
2738 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
2739 SND_SOC_DAPM_ADC("ADC2 L", NULL, SND_SOC_NOPM, 0, 0),
2740 SND_SOC_DAPM_ADC("ADC2 R", NULL, SND_SOC_NOPM, 0, 0),
2742 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5665_PWR_DIG_1,
2743 RT5665_PWR_ADC_L1_BIT, 0, NULL, 0),
2744 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5665_PWR_DIG_1,
2745 RT5665_PWR_ADC_R1_BIT, 0, NULL, 0),
2746 SND_SOC_DAPM_SUPPLY("ADC2 L Power", RT5665_PWR_DIG_1,
2747 RT5665_PWR_ADC_L2_BIT, 0, NULL, 0),
2748 SND_SOC_DAPM_SUPPLY("ADC2 R Power", RT5665_PWR_DIG_1,
2749 RT5665_PWR_ADC_R2_BIT, 0, NULL, 0),
2750 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5665_CHOP_ADC,
2751 RT5665_CKGEN_ADC1_SFT, 0, NULL, 0),
2752 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5665_CHOP_ADC,
2753 RT5665_CKGEN_ADC2_SFT, 0, NULL, 0),
2756 SND_SOC_DAPM_MUX("Stereo1 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2757 &rt5665_sto1_dmic_mux),
2758 SND_SOC_DAPM_MUX("Stereo1 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2759 &rt5665_sto1_dmic_mux),
2760 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2761 &rt5665_sto1_adc1l_mux),
2762 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2763 &rt5665_sto1_adc1r_mux),
2764 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2765 &rt5665_sto1_adc2l_mux),
2766 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2767 &rt5665_sto1_adc2r_mux),
2768 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2769 &rt5665_sto1_adcl_mux),
2770 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2771 &rt5665_sto1_adcr_mux),
2772 SND_SOC_DAPM_MUX("Stereo1 DD L Mux", SND_SOC_NOPM, 0, 0,
2773 &rt5665_sto1_dd_l_mux),
2774 SND_SOC_DAPM_MUX("Stereo1 DD R Mux", SND_SOC_NOPM, 0, 0,
2775 &rt5665_sto1_dd_r_mux),
2776 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2777 &rt5665_mono_adc_l2_mux),
2778 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2779 &rt5665_mono_adc_r2_mux),
2780 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2781 &rt5665_mono_adc_l1_mux),
2782 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2783 &rt5665_mono_adc_r1_mux),
2784 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2785 &rt5665_mono_dmic_l_mux),
2786 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2787 &rt5665_mono_dmic_r_mux),
2788 SND_SOC_DAPM_MUX("Mono ADC L Mux", SND_SOC_NOPM, 0, 0,
2789 &rt5665_mono_adc_l_mux),
2790 SND_SOC_DAPM_MUX("Mono ADC R Mux", SND_SOC_NOPM, 0, 0,
2791 &rt5665_mono_adc_r_mux),
2792 SND_SOC_DAPM_MUX("Mono DD L Mux", SND_SOC_NOPM, 0, 0,
2793 &rt5665_mono_dd_l_mux),
2794 SND_SOC_DAPM_MUX("Mono DD R Mux", SND_SOC_NOPM, 0, 0,
2795 &rt5665_mono_dd_r_mux),
2796 SND_SOC_DAPM_MUX("Stereo2 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2797 &rt5665_sto2_dmic_mux),
2798 SND_SOC_DAPM_MUX("Stereo2 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2799 &rt5665_sto2_dmic_mux),
2800 SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2801 &rt5665_sto2_adc1l_mux),
2802 SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2803 &rt5665_sto2_adc1r_mux),
2804 SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2805 &rt5665_sto2_adc2l_mux),
2806 SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2807 &rt5665_sto2_adc2r_mux),
2808 SND_SOC_DAPM_MUX("Stereo2 ADC L Mux", SND_SOC_NOPM, 0, 0,
2809 &rt5665_sto2_adcl_mux),
2810 SND_SOC_DAPM_MUX("Stereo2 ADC R Mux", SND_SOC_NOPM, 0, 0,
2811 &rt5665_sto2_adcr_mux),
2812 SND_SOC_DAPM_MUX("Stereo2 DD L Mux", SND_SOC_NOPM, 0, 0,
2813 &rt5665_sto2_dd_l_mux),
2814 SND_SOC_DAPM_MUX("Stereo2 DD R Mux", SND_SOC_NOPM, 0, 0,
2815 &rt5665_sto2_dd_r_mux),
2817 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5665_PWR_DIG_2,
2818 RT5665_PWR_ADC_S1F_BIT, 0, NULL, 0),
2819 SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5665_PWR_DIG_2,
2820 RT5665_PWR_ADC_S2F_BIT, 0, NULL, 0),
2821 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5665_STO1_ADC_DIG_VOL,
2822 RT5665_L_MUTE_SFT, 1, rt5665_sto1_adc_l_mix,
2823 ARRAY_SIZE(rt5665_sto1_adc_l_mix)),
2824 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5665_STO1_ADC_DIG_VOL,
2825 RT5665_R_MUTE_SFT, 1, rt5665_sto1_adc_r_mix,
2826 ARRAY_SIZE(rt5665_sto1_adc_r_mix)),
2827 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", RT5665_STO2_ADC_DIG_VOL,
2828 RT5665_L_MUTE_SFT, 1, rt5665_sto2_adc_l_mix,
2829 ARRAY_SIZE(rt5665_sto2_adc_l_mix)),
2830 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", RT5665_STO2_ADC_DIG_VOL,
2831 RT5665_R_MUTE_SFT, 1, rt5665_sto2_adc_r_mix,
2832 ARRAY_SIZE(rt5665_sto2_adc_r_mix)),
2833 SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5665_PWR_DIG_2,
2834 RT5665_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2835 SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5665_MONO_ADC_DIG_VOL,
2836 RT5665_L_MUTE_SFT, 1, rt5665_mono_adc_l_mix,
2837 ARRAY_SIZE(rt5665_mono_adc_l_mix)),
2838 SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5665_PWR_DIG_2,
2839 RT5665_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2840 SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5665_MONO_ADC_DIG_VOL,
2841 RT5665_R_MUTE_SFT, 1, rt5665_mono_adc_r_mix,
2842 ARRAY_SIZE(rt5665_mono_adc_r_mix)),
2845 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2846 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2847 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2849 /* Digital Interface */
2850 SND_SOC_DAPM_SUPPLY("I2S1_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_1_BIT,
2852 SND_SOC_DAPM_SUPPLY("I2S1_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_2_BIT,
2854 SND_SOC_DAPM_SUPPLY("I2S2_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_1_BIT,
2856 SND_SOC_DAPM_SUPPLY("I2S2_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_2_BIT,
2858 SND_SOC_DAPM_SUPPLY("I2S3", RT5665_PWR_DIG_1, RT5665_PWR_I2S3_BIT,
2860 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2861 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2862 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2863 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2864 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2865 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2866 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2867 SND_SOC_DAPM_PGA("IF1 DAC3 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2868 SND_SOC_DAPM_PGA("IF1 DAC3 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2870 SND_SOC_DAPM_PGA("IF2_1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2871 SND_SOC_DAPM_PGA("IF2_2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2872 SND_SOC_DAPM_PGA("IF2_1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2873 SND_SOC_DAPM_PGA("IF2_1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2874 SND_SOC_DAPM_PGA("IF2_2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2875 SND_SOC_DAPM_PGA("IF2_2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2876 SND_SOC_DAPM_PGA("IF2_1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2877 SND_SOC_DAPM_PGA("IF2_2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2879 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2880 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2881 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2882 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2884 /* Digital Interface Select */
2885 SND_SOC_DAPM_MUX("IF1_1_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2886 &rt5665_if1_1_adc1_mux),
2887 SND_SOC_DAPM_MUX("IF1_1_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2888 &rt5665_if1_1_adc2_mux),
2889 SND_SOC_DAPM_MUX("IF1_1_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2890 &rt5665_if1_1_adc3_mux),
2891 SND_SOC_DAPM_PGA("IF1_1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2892 SND_SOC_DAPM_MUX("IF1_2_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2893 &rt5665_if1_2_adc1_mux),
2894 SND_SOC_DAPM_MUX("IF1_2_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2895 &rt5665_if1_2_adc2_mux),
2896 SND_SOC_DAPM_MUX("IF1_2_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2897 &rt5665_if1_2_adc3_mux),
2898 SND_SOC_DAPM_MUX("IF1_2_ADC4 Mux", SND_SOC_NOPM, 0, 0,
2899 &rt5665_if1_2_adc4_mux),
2900 SND_SOC_DAPM_MUX("TDM1 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2901 &rt5665_tdm1_adc_mux),
2902 SND_SOC_DAPM_MUX("TDM1 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2903 &rt5665_tdm1_adc_mux),
2904 SND_SOC_DAPM_MUX("TDM1 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2905 &rt5665_tdm1_adc_mux),
2906 SND_SOC_DAPM_MUX("TDM1 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2907 &rt5665_tdm1_adc_mux),
2908 SND_SOC_DAPM_MUX("TDM2 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2909 &rt5665_tdm2_adc_mux),
2910 SND_SOC_DAPM_MUX("TDM2 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2911 &rt5665_tdm2_adc_mux),
2912 SND_SOC_DAPM_MUX("TDM2 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2913 &rt5665_tdm2_adc_mux),
2914 SND_SOC_DAPM_MUX("TDM2 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2915 &rt5665_tdm2_adc_mux),
2916 SND_SOC_DAPM_MUX("IF2_1 ADC Mux", SND_SOC_NOPM, 0, 0,
2917 &rt5665_if2_1_adc_in_mux),
2918 SND_SOC_DAPM_MUX("IF2_2 ADC Mux", SND_SOC_NOPM, 0, 0,
2919 &rt5665_if2_2_adc_in_mux),
2920 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2921 &rt5665_if3_adc_in_mux),
2922 SND_SOC_DAPM_MUX("IF1_1 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2923 &rt5665_if1_1_01_adc_swap_mux),
2924 SND_SOC_DAPM_MUX("IF1_1 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2925 &rt5665_if1_1_01_adc_swap_mux),
2926 SND_SOC_DAPM_MUX("IF1_1 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2927 &rt5665_if1_1_23_adc_swap_mux),
2928 SND_SOC_DAPM_MUX("IF1_1 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2929 &rt5665_if1_1_23_adc_swap_mux),
2930 SND_SOC_DAPM_MUX("IF1_1 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2931 &rt5665_if1_1_45_adc_swap_mux),
2932 SND_SOC_DAPM_MUX("IF1_1 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2933 &rt5665_if1_1_45_adc_swap_mux),
2934 SND_SOC_DAPM_MUX("IF1_1 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2935 &rt5665_if1_1_67_adc_swap_mux),
2936 SND_SOC_DAPM_MUX("IF1_1 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2937 &rt5665_if1_1_67_adc_swap_mux),
2938 SND_SOC_DAPM_MUX("IF1_2 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2939 &rt5665_if1_2_01_adc_swap_mux),
2940 SND_SOC_DAPM_MUX("IF1_2 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2941 &rt5665_if1_2_01_adc_swap_mux),
2942 SND_SOC_DAPM_MUX("IF1_2 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2943 &rt5665_if1_2_23_adc_swap_mux),
2944 SND_SOC_DAPM_MUX("IF1_2 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2945 &rt5665_if1_2_23_adc_swap_mux),
2946 SND_SOC_DAPM_MUX("IF1_2 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2947 &rt5665_if1_2_45_adc_swap_mux),
2948 SND_SOC_DAPM_MUX("IF1_2 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2949 &rt5665_if1_2_45_adc_swap_mux),
2950 SND_SOC_DAPM_MUX("IF1_2 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2951 &rt5665_if1_2_67_adc_swap_mux),
2952 SND_SOC_DAPM_MUX("IF1_2 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2953 &rt5665_if1_2_67_adc_swap_mux),
2954 SND_SOC_DAPM_MUX("IF2_1 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
2955 &rt5665_if2_1_dac_swap_mux),
2956 SND_SOC_DAPM_MUX("IF2_1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2957 &rt5665_if2_1_adc_swap_mux),
2958 SND_SOC_DAPM_MUX("IF2_2 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
2959 &rt5665_if2_2_dac_swap_mux),
2960 SND_SOC_DAPM_MUX("IF2_2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2961 &rt5665_if2_2_adc_swap_mux),
2962 SND_SOC_DAPM_MUX("IF3 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
2963 &rt5665_if3_dac_swap_mux),
2964 SND_SOC_DAPM_MUX("IF3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2965 &rt5665_if3_adc_swap_mux),
2967 /* Audio Interface */
2968 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 0", "AIF1_1 Capture",
2969 0, SND_SOC_NOPM, 0, 0),
2970 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 1", "AIF1_1 Capture",
2971 1, SND_SOC_NOPM, 0, 0),
2972 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 2", "AIF1_1 Capture",
2973 2, SND_SOC_NOPM, 0, 0),
2974 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 3", "AIF1_1 Capture",
2975 3, SND_SOC_NOPM, 0, 0),
2976 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 4", "AIF1_1 Capture",
2977 4, SND_SOC_NOPM, 0, 0),
2978 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 5", "AIF1_1 Capture",
2979 5, SND_SOC_NOPM, 0, 0),
2980 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 6", "AIF1_1 Capture",
2981 6, SND_SOC_NOPM, 0, 0),
2982 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 7", "AIF1_1 Capture",
2983 7, SND_SOC_NOPM, 0, 0),
2984 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 0", "AIF1_2 Capture",
2985 0, SND_SOC_NOPM, 0, 0),
2986 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 1", "AIF1_2 Capture",
2987 1, SND_SOC_NOPM, 0, 0),
2988 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 2", "AIF1_2 Capture",
2989 2, SND_SOC_NOPM, 0, 0),
2990 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 3", "AIF1_2 Capture",
2991 3, SND_SOC_NOPM, 0, 0),
2992 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 4", "AIF1_2 Capture",
2993 4, SND_SOC_NOPM, 0, 0),
2994 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 5", "AIF1_2 Capture",
2995 5, SND_SOC_NOPM, 0, 0),
2996 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 6", "AIF1_2 Capture",
2997 6, SND_SOC_NOPM, 0, 0),
2998 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 7", "AIF1_2 Capture",
2999 7, SND_SOC_NOPM, 0, 0),
3000 SND_SOC_DAPM_AIF_OUT("AIF2_1TX", "AIF2_1 Capture",
3001 0, SND_SOC_NOPM, 0, 0),
3002 SND_SOC_DAPM_AIF_OUT("AIF2_2TX", "AIF2_2 Capture",
3003 0, SND_SOC_NOPM, 0, 0),
3004 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture",
3005 0, SND_SOC_NOPM, 0, 0),
3006 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback",
3007 0, SND_SOC_NOPM, 0, 0),
3008 SND_SOC_DAPM_AIF_IN("AIF2_1RX", "AIF2_1 Playback",
3009 0, SND_SOC_NOPM, 0, 0),
3010 SND_SOC_DAPM_AIF_IN("AIF2_2RX", "AIF2_2 Playback",
3011 0, SND_SOC_NOPM, 0, 0),
3012 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback",
3013 0, SND_SOC_NOPM, 0, 0),
3016 /* DAC mixer before sound effect */
3017 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
3018 rt5665_dac_l_mix, ARRAY_SIZE(rt5665_dac_l_mix)),
3019 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
3020 rt5665_dac_r_mix, ARRAY_SIZE(rt5665_dac_r_mix)),
3022 /* DAC channel Mux */
3023 SND_SOC_DAPM_MUX("DAC L1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l1_mux),
3024 SND_SOC_DAPM_MUX("DAC R1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r1_mux),
3025 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l2_mux),
3026 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r2_mux),
3027 SND_SOC_DAPM_MUX("DAC L3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l3_mux),
3028 SND_SOC_DAPM_MUX("DAC R3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r3_mux),
3030 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
3031 &rt5665_alg_dac_l1_mux),
3032 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
3033 &rt5665_alg_dac_r1_mux),
3034 SND_SOC_DAPM_MUX("DAC L2 Source", SND_SOC_NOPM, 0, 0,
3035 &rt5665_alg_dac_l2_mux),
3036 SND_SOC_DAPM_MUX("DAC R2 Source", SND_SOC_NOPM, 0, 0,
3037 &rt5665_alg_dac_r2_mux),
3040 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5665_PWR_DIG_2,
3041 RT5665_PWR_DAC_S1F_BIT, 0, NULL, 0),
3042 SND_SOC_DAPM_SUPPLY("DAC Stereo2 Filter", RT5665_PWR_DIG_2,
3043 RT5665_PWR_DAC_S2F_BIT, 0, NULL, 0),
3044 SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter", RT5665_PWR_DIG_2,
3045 RT5665_PWR_DAC_MF_L_BIT, 0, NULL, 0),
3046 SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter", RT5665_PWR_DIG_2,
3047 RT5665_PWR_DAC_MF_R_BIT, 0, NULL, 0),
3048 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
3049 rt5665_sto1_dac_l_mix, ARRAY_SIZE(rt5665_sto1_dac_l_mix)),
3050 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
3051 rt5665_sto1_dac_r_mix, ARRAY_SIZE(rt5665_sto1_dac_r_mix)),
3052 SND_SOC_DAPM_MIXER("Stereo2 DAC MIXL", SND_SOC_NOPM, 0, 0,
3053 rt5665_sto2_dac_l_mix, ARRAY_SIZE(rt5665_sto2_dac_l_mix)),
3054 SND_SOC_DAPM_MIXER("Stereo2 DAC MIXR", SND_SOC_NOPM, 0, 0,
3055 rt5665_sto2_dac_r_mix, ARRAY_SIZE(rt5665_sto2_dac_r_mix)),
3056 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
3057 rt5665_mono_dac_l_mix, ARRAY_SIZE(rt5665_mono_dac_l_mix)),
3058 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
3059 rt5665_mono_dac_r_mix, ARRAY_SIZE(rt5665_mono_dac_r_mix)),
3060 SND_SOC_DAPM_MUX("DAC MIXL", SND_SOC_NOPM, 0, 0,
3061 &rt5665_dig_dac_mixl_mux),
3062 SND_SOC_DAPM_MUX("DAC MIXR", SND_SOC_NOPM, 0, 0,
3063 &rt5665_dig_dac_mixr_mux),
3066 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
3067 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
3069 SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT5665_PWR_DIG_1,
3070 RT5665_PWR_DAC_L2_BIT, 0, NULL, 0),
3071 SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT5665_PWR_DIG_1,
3072 RT5665_PWR_DAC_R2_BIT, 0, NULL, 0),
3073 SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0, 0),
3074 SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0, 0),
3075 SND_SOC_DAPM_PGA("DAC1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3077 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 1, RT5665_CHOP_DAC,
3078 RT5665_CKGEN_DAC1_SFT, 0, NULL, 0),
3079 SND_SOC_DAPM_SUPPLY_S("DAC 2 Clock", 1, RT5665_CHOP_DAC,
3080 RT5665_CKGEN_DAC2_SFT, 0, NULL, 0),
3083 SND_SOC_DAPM_MIXER("MONOVOL MIX", RT5665_PWR_MIXER, RT5665_PWR_MM_BIT,
3084 0, rt5665_monovol_mix, ARRAY_SIZE(rt5665_monovol_mix)),
3085 SND_SOC_DAPM_MIXER("OUT MIXL", RT5665_PWR_MIXER, RT5665_PWR_OM_L_BIT,
3086 0, rt5665_out_l_mix, ARRAY_SIZE(rt5665_out_l_mix)),
3087 SND_SOC_DAPM_MIXER("OUT MIXR", RT5665_PWR_MIXER, RT5665_PWR_OM_R_BIT,
3088 0, rt5665_out_r_mix, ARRAY_SIZE(rt5665_out_r_mix)),
3091 SND_SOC_DAPM_SWITCH("MONOVOL", RT5665_PWR_VOL, RT5665_PWR_MV_BIT, 0,
3093 SND_SOC_DAPM_SWITCH("OUTVOL L", RT5665_PWR_VOL, RT5665_PWR_OV_L_BIT, 0,
3095 SND_SOC_DAPM_SWITCH("OUTVOL R", RT5665_PWR_VOL, RT5665_PWR_OV_R_BIT, 0,
3099 SND_SOC_DAPM_MIXER("Mono MIX", SND_SOC_NOPM, 0, 0, rt5665_mono_mix,
3100 ARRAY_SIZE(rt5665_mono_mix)),
3101 SND_SOC_DAPM_MIXER("LOUT L MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_l_mix,
3102 ARRAY_SIZE(rt5665_lout_l_mix)),
3103 SND_SOC_DAPM_MIXER("LOUT R MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_r_mix,
3104 ARRAY_SIZE(rt5665_lout_r_mix)),
3105 SND_SOC_DAPM_PGA_S("Mono Amp", 1, RT5665_PWR_ANLG_1, RT5665_PWR_MA_BIT,
3106 0, rt5665_mono_event, SND_SOC_DAPM_POST_PMD |
3107 SND_SOC_DAPM_PRE_PMU),
3108 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5665_hp_event,
3109 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
3110 SND_SOC_DAPM_PGA_S("LOUT Amp", 1, RT5665_PWR_ANLG_1,
3111 RT5665_PWR_LM_BIT, 0, rt5665_lout_event,
3112 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
3113 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
3115 SND_SOC_DAPM_SUPPLY("Charge Pump", SND_SOC_NOPM, 0, 0,
3116 rt5665_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
3117 SND_SOC_DAPM_POST_PMD),
3119 SND_SOC_DAPM_SWITCH("Mono Playback", SND_SOC_NOPM, 0, 0,
3121 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
3123 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
3125 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
3127 SND_SOC_DAPM_SWITCH("PDM L Playback", SND_SOC_NOPM, 0, 0,
3129 SND_SOC_DAPM_SWITCH("PDM R Playback", SND_SOC_NOPM, 0, 0,
3133 SND_SOC_DAPM_SUPPLY("PDM Power", RT5665_PWR_DIG_2,
3134 RT5665_PWR_PDM1_BIT, 0, NULL, 0),
3135 SND_SOC_DAPM_MUX("PDM L Mux", SND_SOC_NOPM,
3136 0, 1, &rt5665_pdm_l_mux),
3137 SND_SOC_DAPM_MUX("PDM R Mux", SND_SOC_NOPM,
3138 0, 1, &rt5665_pdm_r_mux),
3141 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5665_CLK_DET, RT5665_SYS_CLK_DET,
3143 SND_SOC_DAPM_SUPPLY("CLKDET HP", RT5665_CLK_DET, RT5665_HP_CLK_DET,
3145 SND_SOC_DAPM_SUPPLY("CLKDET MONO", RT5665_CLK_DET, RT5665_MONO_CLK_DET,
3147 SND_SOC_DAPM_SUPPLY("CLKDET LOUT", RT5665_CLK_DET, RT5665_LOUT_CLK_DET,
3149 SND_SOC_DAPM_SUPPLY("CLKDET", RT5665_CLK_DET, RT5665_POW_CLK_DET,
3153 SND_SOC_DAPM_OUTPUT("HPOL"),
3154 SND_SOC_DAPM_OUTPUT("HPOR"),
3155 SND_SOC_DAPM_OUTPUT("LOUTL"),
3156 SND_SOC_DAPM_OUTPUT("LOUTR"),
3157 SND_SOC_DAPM_OUTPUT("MONOOUT"),
3158 SND_SOC_DAPM_OUTPUT("PDML"),
3159 SND_SOC_DAPM_OUTPUT("PDMR"),
3162 static const struct snd_soc_dapm_route rt5665_dapm_routes[] = {
3164 {"ADC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
3165 {"ADC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
3166 {"ADC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
3167 {"ADC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
3168 {"DAC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
3169 {"DAC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
3170 {"DAC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
3171 {"DAC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
3174 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
3175 {"ADC Mono Left Filter", NULL, "ADC Mono L ASRC", is_using_asrc},
3176 {"ADC Mono Right Filter", NULL, "ADC Mono R ASRC", is_using_asrc},
3177 {"DAC Mono Left Filter", NULL, "DAC Mono L ASRC", is_using_asrc},
3178 {"DAC Mono Right Filter", NULL, "DAC Mono R ASRC", is_using_asrc},
3179 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
3180 {"DAC Stereo2 Filter", NULL, "DAC STO2 ASRC", is_using_asrc},
3183 {"Mic Det Power", NULL, "Vref2"},
3184 {"MICBIAS1", NULL, "Vref1"},
3185 {"MICBIAS1", NULL, "Vref2"},
3186 {"MICBIAS2", NULL, "Vref1"},
3187 {"MICBIAS2", NULL, "Vref2"},
3188 {"MICBIAS3", NULL, "Vref1"},
3189 {"MICBIAS3", NULL, "Vref2"},
3191 {"Stereo1 DMIC L Mux", NULL, "DMIC STO1 ASRC"},
3192 {"Stereo1 DMIC R Mux", NULL, "DMIC STO1 ASRC"},
3193 {"Stereo2 DMIC L Mux", NULL, "DMIC STO2 ASRC"},
3194 {"Stereo2 DMIC R Mux", NULL, "DMIC STO2 ASRC"},
3195 {"Mono DMIC L Mux", NULL, "DMIC MONO L ASRC"},
3196 {"Mono DMIC R Mux", NULL, "DMIC MONO R ASRC"},
3198 {"I2S1_1", NULL, "I2S1 ASRC"},
3199 {"I2S1_2", NULL, "I2S1 ASRC"},
3200 {"I2S2_1", NULL, "I2S2 ASRC"},
3201 {"I2S2_2", NULL, "I2S2 ASRC"},
3202 {"I2S3", NULL, "I2S3 ASRC"},
3204 {"CLKDET SYS", NULL, "CLKDET"},
3205 {"CLKDET HP", NULL, "CLKDET"},
3206 {"CLKDET MONO", NULL, "CLKDET"},
3207 {"CLKDET LOUT", NULL, "CLKDET"},
3209 {"IN1P", NULL, "LDO2"},
3210 {"IN2P", NULL, "LDO2"},
3211 {"IN3P", NULL, "LDO2"},
3212 {"IN4P", NULL, "LDO2"},
3214 {"DMIC1", NULL, "DMIC L1"},
3215 {"DMIC1", NULL, "DMIC R1"},
3216 {"DMIC2", NULL, "DMIC L2"},
3217 {"DMIC2", NULL, "DMIC R2"},
3219 {"BST1", NULL, "IN1P"},
3220 {"BST1", NULL, "IN1N"},
3221 {"BST1", NULL, "BST1 Power"},
3222 {"BST1", NULL, "BST1P Power"},
3223 {"BST2", NULL, "IN2P"},
3224 {"BST2", NULL, "IN2N"},
3225 {"BST2", NULL, "BST2 Power"},
3226 {"BST2", NULL, "BST2P Power"},
3227 {"BST3", NULL, "IN3P"},
3228 {"BST3", NULL, "IN3N"},
3229 {"BST3", NULL, "BST3 Power"},
3230 {"BST3", NULL, "BST3P Power"},
3231 {"BST4", NULL, "IN4P"},
3232 {"BST4", NULL, "IN4N"},
3233 {"BST4", NULL, "BST4 Power"},
3234 {"BST4", NULL, "BST4P Power"},
3235 {"BST1 CBJ", NULL, "IN1P"},
3236 {"BST1 CBJ", NULL, "IN1N"},
3237 {"BST1 CBJ", NULL, "CBJ Power"},
3238 {"CBJ Power", NULL, "Vref2"},
3240 {"INL VOL", NULL, "IN3P"},
3241 {"INR VOL", NULL, "IN3N"},
3243 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
3244 {"RECMIX1L", "INL Switch", "INL VOL"},
3245 {"RECMIX1L", "INR Switch", "INR VOL"},
3246 {"RECMIX1L", "BST4 Switch", "BST4"},
3247 {"RECMIX1L", "BST3 Switch", "BST3"},
3248 {"RECMIX1L", "BST2 Switch", "BST2"},
3249 {"RECMIX1L", "BST1 Switch", "BST1"},
3250 {"RECMIX1L", NULL, "RECMIX1L Power"},
3252 {"RECMIX1R", "MONOVOL Switch", "MONOVOL"},
3253 {"RECMIX1R", "INR Switch", "INR VOL"},
3254 {"RECMIX1R", "BST4 Switch", "BST4"},
3255 {"RECMIX1R", "BST3 Switch", "BST3"},
3256 {"RECMIX1R", "BST2 Switch", "BST2"},
3257 {"RECMIX1R", "BST1 Switch", "BST1"},
3258 {"RECMIX1R", NULL, "RECMIX1R Power"},
3260 {"RECMIX2L", "CBJ Switch", "BST1 CBJ"},
3261 {"RECMIX2L", "INL Switch", "INL VOL"},
3262 {"RECMIX2L", "INR Switch", "INR VOL"},
3263 {"RECMIX2L", "BST4 Switch", "BST4"},
3264 {"RECMIX2L", "BST3 Switch", "BST3"},
3265 {"RECMIX2L", "BST2 Switch", "BST2"},
3266 {"RECMIX2L", "BST1 Switch", "BST1"},
3267 {"RECMIX2L", NULL, "RECMIX2L Power"},
3269 {"RECMIX2R", "MONOVOL Switch", "MONOVOL"},
3270 {"RECMIX2R", "INL Switch", "INL VOL"},
3271 {"RECMIX2R", "INR Switch", "INR VOL"},
3272 {"RECMIX2R", "BST4 Switch", "BST4"},
3273 {"RECMIX2R", "BST3 Switch", "BST3"},
3274 {"RECMIX2R", "BST2 Switch", "BST2"},
3275 {"RECMIX2R", "BST1 Switch", "BST1"},
3276 {"RECMIX2R", NULL, "RECMIX2R Power"},
3278 {"ADC1 L", NULL, "RECMIX1L"},
3279 {"ADC1 L", NULL, "ADC1 L Power"},
3280 {"ADC1 L", NULL, "ADC1 clock"},
3281 {"ADC1 R", NULL, "RECMIX1R"},
3282 {"ADC1 R", NULL, "ADC1 R Power"},
3283 {"ADC1 R", NULL, "ADC1 clock"},
3285 {"ADC2 L", NULL, "RECMIX2L"},
3286 {"ADC2 L", NULL, "ADC2 L Power"},
3287 {"ADC2 L", NULL, "ADC2 clock"},
3288 {"ADC2 R", NULL, "RECMIX2R"},
3289 {"ADC2 R", NULL, "ADC2 R Power"},
3290 {"ADC2 R", NULL, "ADC2 clock"},
3292 {"DMIC L1", NULL, "DMIC CLK"},
3293 {"DMIC L1", NULL, "DMIC1 Power"},
3294 {"DMIC R1", NULL, "DMIC CLK"},
3295 {"DMIC R1", NULL, "DMIC1 Power"},
3296 {"DMIC L2", NULL, "DMIC CLK"},
3297 {"DMIC L2", NULL, "DMIC2 Power"},
3298 {"DMIC R2", NULL, "DMIC CLK"},
3299 {"DMIC R2", NULL, "DMIC2 Power"},
3301 {"Stereo1 DMIC L Mux", "DMIC1", "DMIC L1"},
3302 {"Stereo1 DMIC L Mux", "DMIC2", "DMIC L2"},
3304 {"Stereo1 DMIC R Mux", "DMIC1", "DMIC R1"},
3305 {"Stereo1 DMIC R Mux", "DMIC2", "DMIC R2"},
3307 {"Mono DMIC L Mux", "DMIC1 L", "DMIC L1"},
3308 {"Mono DMIC L Mux", "DMIC2 L", "DMIC L2"},
3310 {"Mono DMIC R Mux", "DMIC1 R", "DMIC R1"},
3311 {"Mono DMIC R Mux", "DMIC2 R", "DMIC R2"},
3313 {"Stereo2 DMIC L Mux", "DMIC1", "DMIC L1"},
3314 {"Stereo2 DMIC L Mux", "DMIC2", "DMIC L2"},
3316 {"Stereo2 DMIC R Mux", "DMIC1", "DMIC R1"},
3317 {"Stereo2 DMIC R Mux", "DMIC2", "DMIC R2"},
3319 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
3320 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
3321 {"Stereo1 ADC L Mux", "ADC2 L", "ADC2 L"},
3322 {"Stereo1 ADC L Mux", "ADC2 R", "ADC2 R"},
3323 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
3324 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
3325 {"Stereo1 ADC R Mux", "ADC2 L", "ADC2 L"},
3326 {"Stereo1 ADC R Mux", "ADC2 R", "ADC2 R"},
3328 {"Stereo1 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3329 {"Stereo1 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3331 {"Stereo1 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3332 {"Stereo1 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3334 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
3335 {"Stereo1 ADC L1 Mux", "DD Mux", "Stereo1 DD L Mux"},
3336 {"Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC L Mux"},
3337 {"Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3339 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
3340 {"Stereo1 ADC R1 Mux", "DD Mux", "Stereo1 DD R Mux"},
3341 {"Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC R Mux"},
3342 {"Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3344 {"Mono ADC L Mux", "ADC1 L", "ADC1 L"},
3345 {"Mono ADC L Mux", "ADC1 R", "ADC1 R"},
3346 {"Mono ADC L Mux", "ADC2 L", "ADC2 L"},
3347 {"Mono ADC L Mux", "ADC2 R", "ADC2 R"},
3349 {"Mono ADC R Mux", "ADC1 L", "ADC1 L"},
3350 {"Mono ADC R Mux", "ADC1 R", "ADC1 R"},
3351 {"Mono ADC R Mux", "ADC2 L", "ADC2 L"},
3352 {"Mono ADC R Mux", "ADC2 R", "ADC2 R"},
3354 {"Mono DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3355 {"Mono DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3357 {"Mono DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3358 {"Mono DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3360 {"Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux"},
3361 {"Mono ADC L2 Mux", "DAC MIXL", "DAC MIXL"},
3362 {"Mono ADC L1 Mux", "DD Mux", "Mono DD L Mux"},
3363 {"Mono ADC L1 Mux", "ADC", "Mono ADC L Mux"},
3365 {"Mono ADC R1 Mux", "DD Mux", "Mono DD R Mux"},
3366 {"Mono ADC R1 Mux", "ADC", "Mono ADC R Mux"},
3367 {"Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux"},
3368 {"Mono ADC R2 Mux", "DAC MIXR", "DAC MIXR"},
3370 {"Stereo2 ADC L Mux", "ADC1 L", "ADC1 L"},
3371 {"Stereo2 ADC L Mux", "ADC2 L", "ADC2 L"},
3372 {"Stereo2 ADC L Mux", "ADC1 R", "ADC1 R"},
3373 {"Stereo2 ADC R Mux", "ADC1 L", "ADC1 L"},
3374 {"Stereo2 ADC R Mux", "ADC2 L", "ADC2 L"},
3375 {"Stereo2 ADC R Mux", "ADC1 R", "ADC1 R"},
3377 {"Stereo2 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3378 {"Stereo2 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3380 {"Stereo2 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3381 {"Stereo2 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3383 {"Stereo2 ADC L1 Mux", "ADC", "Stereo2 ADC L Mux"},
3384 {"Stereo2 ADC L1 Mux", "DD Mux", "Stereo2 DD L Mux"},
3385 {"Stereo2 ADC L2 Mux", "DMIC", "Stereo2 DMIC L Mux"},
3386 {"Stereo2 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3388 {"Stereo2 ADC R1 Mux", "ADC", "Stereo2 ADC R Mux"},
3389 {"Stereo2 ADC R1 Mux", "DD Mux", "Stereo2 DD R Mux"},
3390 {"Stereo2 ADC R2 Mux", "DMIC", "Stereo2 DMIC R Mux"},
3391 {"Stereo2 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3393 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
3394 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
3395 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
3397 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
3398 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
3399 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
3401 {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
3402 {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
3403 {"Mono ADC MIXL", NULL, "ADC Mono Left Filter"},
3405 {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
3406 {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
3407 {"Mono ADC MIXR", NULL, "ADC Mono Right Filter"},
3409 {"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
3410 {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
3411 {"Stereo2 ADC MIXL", NULL, "ADC Stereo2 Filter"},
3413 {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
3414 {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
3415 {"Stereo2 ADC MIXR", NULL, "ADC Stereo2 Filter"},
3417 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
3418 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
3419 {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL"},
3420 {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR"},
3421 {"Mono ADC MIX", NULL, "Mono ADC MIXL"},
3422 {"Mono ADC MIX", NULL, "Mono ADC MIXR"},
3424 {"IF1_1_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3425 {"IF1_1_ADC1 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3426 {"IF1_1_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3427 {"IF1_1_ADC2 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3428 {"IF1_1_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3429 {"IF1_1_ADC3 Mux", "IF3 DAC", "IF3 DAC"},
3430 {"IF1_1_ADC4", NULL, "DAC1 MIX"},
3432 {"IF1_2_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3433 {"IF1_2_ADC1 Mux", "IF1 DAC", "IF1 DAC1"},
3434 {"IF1_2_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3435 {"IF1_2_ADC2 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3436 {"IF1_2_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3437 {"IF1_2_ADC3 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3438 {"IF1_2_ADC4 Mux", "DAC1", "DAC1 MIX"},
3439 {"IF1_2_ADC4 Mux", "IF3 DAC", "IF3 DAC"},
3441 {"TDM1 slot 01 Data Mux", "1234", "IF1_1_ADC1 Mux"},
3442 {"TDM1 slot 01 Data Mux", "1243", "IF1_1_ADC1 Mux"},
3443 {"TDM1 slot 01 Data Mux", "1324", "IF1_1_ADC1 Mux"},
3444 {"TDM1 slot 01 Data Mux", "1342", "IF1_1_ADC1 Mux"},
3445 {"TDM1 slot 01 Data Mux", "1432", "IF1_1_ADC1 Mux"},
3446 {"TDM1 slot 01 Data Mux", "1423", "IF1_1_ADC1 Mux"},
3447 {"TDM1 slot 01 Data Mux", "2134", "IF1_1_ADC2 Mux"},
3448 {"TDM1 slot 01 Data Mux", "2143", "IF1_1_ADC2 Mux"},
3449 {"TDM1 slot 01 Data Mux", "2314", "IF1_1_ADC2 Mux"},
3450 {"TDM1 slot 01 Data Mux", "2341", "IF1_1_ADC2 Mux"},
3451 {"TDM1 slot 01 Data Mux", "2431", "IF1_1_ADC2 Mux"},
3452 {"TDM1 slot 01 Data Mux", "2413", "IF1_1_ADC2 Mux"},
3453 {"TDM1 slot 01 Data Mux", "3124", "IF1_1_ADC3 Mux"},
3454 {"TDM1 slot 01 Data Mux", "3142", "IF1_1_ADC3 Mux"},
3455 {"TDM1 slot 01 Data Mux", "3214", "IF1_1_ADC3 Mux"},
3456 {"TDM1 slot 01 Data Mux", "3241", "IF1_1_ADC3 Mux"},
3457 {"TDM1 slot 01 Data Mux", "3412", "IF1_1_ADC3 Mux"},
3458 {"TDM1 slot 01 Data Mux", "3421", "IF1_1_ADC3 Mux"},
3459 {"TDM1 slot 01 Data Mux", "4123", "IF1_1_ADC4"},
3460 {"TDM1 slot 01 Data Mux", "4132", "IF1_1_ADC4"},
3461 {"TDM1 slot 01 Data Mux", "4213", "IF1_1_ADC4"},
3462 {"TDM1 slot 01 Data Mux", "4231", "IF1_1_ADC4"},
3463 {"TDM1 slot 01 Data Mux", "4312", "IF1_1_ADC4"},
3464 {"TDM1 slot 01 Data Mux", "4321", "IF1_1_ADC4"},
3465 {"TDM1 slot 01 Data Mux", NULL, "I2S1_1"},
3467 {"TDM1 slot 23 Data Mux", "1234", "IF1_1_ADC2 Mux"},
3468 {"TDM1 slot 23 Data Mux", "1243", "IF1_1_ADC2 Mux"},
3469 {"TDM1 slot 23 Data Mux", "1324", "IF1_1_ADC3 Mux"},
3470 {"TDM1 slot 23 Data Mux", "1342", "IF1_1_ADC3 Mux"},
3471 {"TDM1 slot 23 Data Mux", "1432", "IF1_1_ADC4"},
3472 {"TDM1 slot 23 Data Mux", "1423", "IF1_1_ADC4"},
3473 {"TDM1 slot 23 Data Mux", "2134", "IF1_1_ADC1 Mux"},
3474 {"TDM1 slot 23 Data Mux", "2143", "IF1_1_ADC1 Mux"},
3475 {"TDM1 slot 23 Data Mux", "2314", "IF1_1_ADC3 Mux"},
3476 {"TDM1 slot 23 Data Mux", "2341", "IF1_1_ADC3 Mux"},
3477 {"TDM1 slot 23 Data Mux", "2431", "IF1_1_ADC4"},
3478 {"TDM1 slot 23 Data Mux", "2413", "IF1_1_ADC4"},
3479 {"TDM1 slot 23 Data Mux", "3124", "IF1_1_ADC1 Mux"},
3480 {"TDM1 slot 23 Data Mux", "3142", "IF1_1_ADC1 Mux"},
3481 {"TDM1 slot 23 Data Mux", "3214", "IF1_1_ADC2 Mux"},
3482 {"TDM1 slot 23 Data Mux", "3241", "IF1_1_ADC2 Mux"},
3483 {"TDM1 slot 23 Data Mux", "3412", "IF1_1_ADC4"},
3484 {"TDM1 slot 23 Data Mux", "3421", "IF1_1_ADC4"},
3485 {"TDM1 slot 23 Data Mux", "4123", "IF1_1_ADC1 Mux"},
3486 {"TDM1 slot 23 Data Mux", "4132", "IF1_1_ADC1 Mux"},
3487 {"TDM1 slot 23 Data Mux", "4213", "IF1_1_ADC2 Mux"},
3488 {"TDM1 slot 23 Data Mux", "4231", "IF1_1_ADC2 Mux"},
3489 {"TDM1 slot 23 Data Mux", "4312", "IF1_1_ADC3 Mux"},
3490 {"TDM1 slot 23 Data Mux", "4321", "IF1_1_ADC3 Mux"},
3491 {"TDM1 slot 23 Data Mux", NULL, "I2S1_1"},
3493 {"TDM1 slot 45 Data Mux", "1234", "IF1_1_ADC3 Mux"},
3494 {"TDM1 slot 45 Data Mux", "1243", "IF1_1_ADC4"},
3495 {"TDM1 slot 45 Data Mux", "1324", "IF1_1_ADC2 Mux"},
3496 {"TDM1 slot 45 Data Mux", "1342", "IF1_1_ADC4"},
3497 {"TDM1 slot 45 Data Mux", "1432", "IF1_1_ADC3 Mux"},
3498 {"TDM1 slot 45 Data Mux", "1423", "IF1_1_ADC2 Mux"},
3499 {"TDM1 slot 45 Data Mux", "2134", "IF1_1_ADC3 Mux"},
3500 {"TDM1 slot 45 Data Mux", "2143", "IF1_1_ADC4"},
3501 {"TDM1 slot 45 Data Mux", "2314", "IF1_1_ADC1 Mux"},
3502 {"TDM1 slot 45 Data Mux", "2341", "IF1_1_ADC4"},
3503 {"TDM1 slot 45 Data Mux", "2431", "IF1_1_ADC3 Mux"},
3504 {"TDM1 slot 45 Data Mux", "2413", "IF1_1_ADC1 Mux"},
3505 {"TDM1 slot 45 Data Mux", "3124", "IF1_1_ADC2 Mux"},
3506 {"TDM1 slot 45 Data Mux", "3142", "IF1_1_ADC4"},
3507 {"TDM1 slot 45 Data Mux", "3214", "IF1_1_ADC1 Mux"},
3508 {"TDM1 slot 45 Data Mux", "3241", "IF1_1_ADC4"},
3509 {"TDM1 slot 45 Data Mux", "3412", "IF1_1_ADC1 Mux"},
3510 {"TDM1 slot 45 Data Mux", "3421", "IF1_1_ADC2 Mux"},
3511 {"TDM1 slot 45 Data Mux", "4123", "IF1_1_ADC2 Mux"},
3512 {"TDM1 slot 45 Data Mux", "4132", "IF1_1_ADC3 Mux"},
3513 {"TDM1 slot 45 Data Mux", "4213", "IF1_1_ADC1 Mux"},
3514 {"TDM1 slot 45 Data Mux", "4231", "IF1_1_ADC3 Mux"},
3515 {"TDM1 slot 45 Data Mux", "4312", "IF1_1_ADC1 Mux"},
3516 {"TDM1 slot 45 Data Mux", "4321", "IF1_1_ADC2 Mux"},
3517 {"TDM1 slot 45 Data Mux", NULL, "I2S1_1"},
3519 {"TDM1 slot 67 Data Mux", "1234", "IF1_1_ADC4"},
3520 {"TDM1 slot 67 Data Mux", "1243", "IF1_1_ADC3 Mux"},
3521 {"TDM1 slot 67 Data Mux", "1324", "IF1_1_ADC4"},
3522 {"TDM1 slot 67 Data Mux", "1342", "IF1_1_ADC2 Mux"},
3523 {"TDM1 slot 67 Data Mux", "1432", "IF1_1_ADC2 Mux"},
3524 {"TDM1 slot 67 Data Mux", "1423", "IF1_1_ADC3 Mux"},
3525 {"TDM1 slot 67 Data Mux", "2134", "IF1_1_ADC4"},
3526 {"TDM1 slot 67 Data Mux", "2143", "IF1_1_ADC3 Mux"},
3527 {"TDM1 slot 67 Data Mux", "2314", "IF1_1_ADC4"},
3528 {"TDM1 slot 67 Data Mux", "2341", "IF1_1_ADC1 Mux"},
3529 {"TDM1 slot 67 Data Mux", "2431", "IF1_1_ADC1 Mux"},
3530 {"TDM1 slot 67 Data Mux", "2413", "IF1_1_ADC3 Mux"},
3531 {"TDM1 slot 67 Data Mux", "3124", "IF1_1_ADC4"},
3532 {"TDM1 slot 67 Data Mux", "3142", "IF1_1_ADC2 Mux"},
3533 {"TDM1 slot 67 Data Mux", "3214", "IF1_1_ADC4"},
3534 {"TDM1 slot 67 Data Mux", "3241", "IF1_1_ADC1 Mux"},
3535 {"TDM1 slot 67 Data Mux", "3412", "IF1_1_ADC2 Mux"},
3536 {"TDM1 slot 67 Data Mux", "3421", "IF1_1_ADC1 Mux"},
3537 {"TDM1 slot 67 Data Mux", "4123", "IF1_1_ADC3 Mux"},
3538 {"TDM1 slot 67 Data Mux", "4132", "IF1_1_ADC2 Mux"},
3539 {"TDM1 slot 67 Data Mux", "4213", "IF1_1_ADC3 Mux"},
3540 {"TDM1 slot 67 Data Mux", "4231", "IF1_1_ADC1 Mux"},
3541 {"TDM1 slot 67 Data Mux", "4312", "IF1_1_ADC2 Mux"},
3542 {"TDM1 slot 67 Data Mux", "4321", "IF1_1_ADC1 Mux"},
3543 {"TDM1 slot 67 Data Mux", NULL, "I2S1_1"},
3546 {"TDM2 slot 01 Data Mux", "1234", "IF1_2_ADC1 Mux"},
3547 {"TDM2 slot 01 Data Mux", "1243", "IF1_2_ADC1 Mux"},
3548 {"TDM2 slot 01 Data Mux", "1324", "IF1_2_ADC1 Mux"},
3549 {"TDM2 slot 01 Data Mux", "1342", "IF1_2_ADC1 Mux"},
3550 {"TDM2 slot 01 Data Mux", "1432", "IF1_2_ADC1 Mux"},
3551 {"TDM2 slot 01 Data Mux", "1423", "IF1_2_ADC1 Mux"},
3552 {"TDM2 slot 01 Data Mux", "2134", "IF1_2_ADC2 Mux"},
3553 {"TDM2 slot 01 Data Mux", "2143", "IF1_2_ADC2 Mux"},
3554 {"TDM2 slot 01 Data Mux", "2314", "IF1_2_ADC2 Mux"},
3555 {"TDM2 slot 01 Data Mux", "2341", "IF1_2_ADC2 Mux"},
3556 {"TDM2 slot 01 Data Mux", "2431", "IF1_2_ADC2 Mux"},
3557 {"TDM2 slot 01 Data Mux", "2413", "IF1_2_ADC2 Mux"},
3558 {"TDM2 slot 01 Data Mux", "3124", "IF1_2_ADC3 Mux"},
3559 {"TDM2 slot 01 Data Mux", "3142", "IF1_2_ADC3 Mux"},
3560 {"TDM2 slot 01 Data Mux", "3214", "IF1_2_ADC3 Mux"},
3561 {"TDM2 slot 01 Data Mux", "3241", "IF1_2_ADC3 Mux"},
3562 {"TDM2 slot 01 Data Mux", "3412", "IF1_2_ADC3 Mux"},
3563 {"TDM2 slot 01 Data Mux", "3421", "IF1_2_ADC3 Mux"},
3564 {"TDM2 slot 01 Data Mux", "4123", "IF1_2_ADC4 Mux"},
3565 {"TDM2 slot 01 Data Mux", "4132", "IF1_2_ADC4 Mux"},
3566 {"TDM2 slot 01 Data Mux", "4213", "IF1_2_ADC4 Mux"},
3567 {"TDM2 slot 01 Data Mux", "4231", "IF1_2_ADC4 Mux"},
3568 {"TDM2 slot 01 Data Mux", "4312", "IF1_2_ADC4 Mux"},
3569 {"TDM2 slot 01 Data Mux", "4321", "IF1_2_ADC4 Mux"},
3570 {"TDM2 slot 01 Data Mux", NULL, "I2S1_2"},
3572 {"TDM2 slot 23 Data Mux", "1234", "IF1_2_ADC2 Mux"},
3573 {"TDM2 slot 23 Data Mux", "1243", "IF1_2_ADC2 Mux"},
3574 {"TDM2 slot 23 Data Mux", "1324", "IF1_2_ADC3 Mux"},
3575 {"TDM2 slot 23 Data Mux", "1342", "IF1_2_ADC3 Mux"},
3576 {"TDM2 slot 23 Data Mux", "1432", "IF1_2_ADC4 Mux"},
3577 {"TDM2 slot 23 Data Mux", "1423", "IF1_2_ADC4 Mux"},
3578 {"TDM2 slot 23 Data Mux", "2134", "IF1_2_ADC1 Mux"},
3579 {"TDM2 slot 23 Data Mux", "2143", "IF1_2_ADC1 Mux"},
3580 {"TDM2 slot 23 Data Mux", "2314", "IF1_2_ADC3 Mux"},
3581 {"TDM2 slot 23 Data Mux", "2341", "IF1_2_ADC3 Mux"},
3582 {"TDM2 slot 23 Data Mux", "2431", "IF1_2_ADC4 Mux"},
3583 {"TDM2 slot 23 Data Mux", "2413", "IF1_2_ADC4 Mux"},
3584 {"TDM2 slot 23 Data Mux", "3124", "IF1_2_ADC1 Mux"},
3585 {"TDM2 slot 23 Data Mux", "3142", "IF1_2_ADC1 Mux"},
3586 {"TDM2 slot 23 Data Mux", "3214", "IF1_2_ADC2 Mux"},
3587 {"TDM2 slot 23 Data Mux", "3241", "IF1_2_ADC2 Mux"},
3588 {"TDM2 slot 23 Data Mux", "3412", "IF1_2_ADC4 Mux"},
3589 {"TDM2 slot 23 Data Mux", "3421", "IF1_2_ADC4 Mux"},
3590 {"TDM2 slot 23 Data Mux", "4123", "IF1_2_ADC1 Mux"},
3591 {"TDM2 slot 23 Data Mux", "4132", "IF1_2_ADC1 Mux"},
3592 {"TDM2 slot 23 Data Mux", "4213", "IF1_2_ADC2 Mux"},
3593 {"TDM2 slot 23 Data Mux", "4231", "IF1_2_ADC2 Mux"},
3594 {"TDM2 slot 23 Data Mux", "4312", "IF1_2_ADC3 Mux"},
3595 {"TDM2 slot 23 Data Mux", "4321", "IF1_2_ADC3 Mux"},
3596 {"TDM2 slot 23 Data Mux", NULL, "I2S1_2"},
3598 {"TDM2 slot 45 Data Mux", "1234", "IF1_2_ADC3 Mux"},
3599 {"TDM2 slot 45 Data Mux", "1243", "IF1_2_ADC4 Mux"},
3600 {"TDM2 slot 45 Data Mux", "1324", "IF1_2_ADC2 Mux"},
3601 {"TDM2 slot 45 Data Mux", "1342", "IF1_2_ADC4 Mux"},
3602 {"TDM2 slot 45 Data Mux", "1432", "IF1_2_ADC3 Mux"},
3603 {"TDM2 slot 45 Data Mux", "1423", "IF1_2_ADC2 Mux"},
3604 {"TDM2 slot 45 Data Mux", "2134", "IF1_2_ADC3 Mux"},
3605 {"TDM2 slot 45 Data Mux", "2143", "IF1_2_ADC4 Mux"},
3606 {"TDM2 slot 45 Data Mux", "2314", "IF1_2_ADC1 Mux"},
3607 {"TDM2 slot 45 Data Mux", "2341", "IF1_2_ADC4 Mux"},
3608 {"TDM2 slot 45 Data Mux", "2431", "IF1_2_ADC3 Mux"},
3609 {"TDM2 slot 45 Data Mux", "2413", "IF1_2_ADC1 Mux"},
3610 {"TDM2 slot 45 Data Mux", "3124", "IF1_2_ADC2 Mux"},
3611 {"TDM2 slot 45 Data Mux", "3142", "IF1_2_ADC4 Mux"},
3612 {"TDM2 slot 45 Data Mux", "3214", "IF1_2_ADC1 Mux"},
3613 {"TDM2 slot 45 Data Mux", "3241", "IF1_2_ADC4 Mux"},
3614 {"TDM2 slot 45 Data Mux", "3412", "IF1_2_ADC1 Mux"},
3615 {"TDM2 slot 45 Data Mux", "3421", "IF1_2_ADC2 Mux"},
3616 {"TDM2 slot 45 Data Mux", "4123", "IF1_2_ADC2 Mux"},
3617 {"TDM2 slot 45 Data Mux", "4132", "IF1_2_ADC3 Mux"},
3618 {"TDM2 slot 45 Data Mux", "4213", "IF1_2_ADC1 Mux"},
3619 {"TDM2 slot 45 Data Mux", "4231", "IF1_2_ADC3 Mux"},
3620 {"TDM2 slot 45 Data Mux", "4312", "IF1_2_ADC1 Mux"},
3621 {"TDM2 slot 45 Data Mux", "4321", "IF1_2_ADC2 Mux"},
3622 {"TDM2 slot 45 Data Mux", NULL, "I2S1_2"},
3624 {"TDM2 slot 67 Data Mux", "1234", "IF1_2_ADC4 Mux"},
3625 {"TDM2 slot 67 Data Mux", "1243", "IF1_2_ADC3 Mux"},
3626 {"TDM2 slot 67 Data Mux", "1324", "IF1_2_ADC4 Mux"},
3627 {"TDM2 slot 67 Data Mux", "1342", "IF1_2_ADC2 Mux"},
3628 {"TDM2 slot 67 Data Mux", "1432", "IF1_2_ADC2 Mux"},
3629 {"TDM2 slot 67 Data Mux", "1423", "IF1_2_ADC3 Mux"},
3630 {"TDM2 slot 67 Data Mux", "2134", "IF1_2_ADC4 Mux"},
3631 {"TDM2 slot 67 Data Mux", "2143", "IF1_2_ADC3 Mux"},
3632 {"TDM2 slot 67 Data Mux", "2314", "IF1_2_ADC4 Mux"},
3633 {"TDM2 slot 67 Data Mux", "2341", "IF1_2_ADC1 Mux"},
3634 {"TDM2 slot 67 Data Mux", "2431", "IF1_2_ADC1 Mux"},
3635 {"TDM2 slot 67 Data Mux", "2413", "IF1_2_ADC3 Mux"},
3636 {"TDM2 slot 67 Data Mux", "3124", "IF1_2_ADC4 Mux"},
3637 {"TDM2 slot 67 Data Mux", "3142", "IF1_2_ADC2 Mux"},
3638 {"TDM2 slot 67 Data Mux", "3214", "IF1_2_ADC4 Mux"},
3639 {"TDM2 slot 67 Data Mux", "3241", "IF1_2_ADC1 Mux"},
3640 {"TDM2 slot 67 Data Mux", "3412", "IF1_2_ADC2 Mux"},
3641 {"TDM2 slot 67 Data Mux", "3421", "IF1_2_ADC1 Mux"},
3642 {"TDM2 slot 67 Data Mux", "4123", "IF1_2_ADC3 Mux"},
3643 {"TDM2 slot 67 Data Mux", "4132", "IF1_2_ADC2 Mux"},
3644 {"TDM2 slot 67 Data Mux", "4213", "IF1_2_ADC3 Mux"},
3645 {"TDM2 slot 67 Data Mux", "4231", "IF1_2_ADC1 Mux"},
3646 {"TDM2 slot 67 Data Mux", "4312", "IF1_2_ADC2 Mux"},
3647 {"TDM2 slot 67 Data Mux", "4321", "IF1_2_ADC1 Mux"},
3648 {"TDM2 slot 67 Data Mux", NULL, "I2S1_2"},
3650 {"IF1_1 0 ADC Swap Mux", "L/R", "TDM1 slot 01 Data Mux"},
3651 {"IF1_1 0 ADC Swap Mux", "L/L", "TDM1 slot 01 Data Mux"},
3652 {"IF1_1 1 ADC Swap Mux", "R/L", "TDM1 slot 01 Data Mux"},
3653 {"IF1_1 1 ADC Swap Mux", "R/R", "TDM1 slot 01 Data Mux"},
3654 {"IF1_1 2 ADC Swap Mux", "L/R", "TDM1 slot 23 Data Mux"},
3655 {"IF1_1 2 ADC Swap Mux", "R/L", "TDM1 slot 23 Data Mux"},
3656 {"IF1_1 3 ADC Swap Mux", "L/L", "TDM1 slot 23 Data Mux"},
3657 {"IF1_1 3 ADC Swap Mux", "R/R", "TDM1 slot 23 Data Mux"},
3658 {"IF1_1 4 ADC Swap Mux", "L/R", "TDM1 slot 45 Data Mux"},
3659 {"IF1_1 4 ADC Swap Mux", "R/L", "TDM1 slot 45 Data Mux"},
3660 {"IF1_1 5 ADC Swap Mux", "L/L", "TDM1 slot 45 Data Mux"},
3661 {"IF1_1 5 ADC Swap Mux", "R/R", "TDM1 slot 45 Data Mux"},
3662 {"IF1_1 6 ADC Swap Mux", "L/R", "TDM1 slot 67 Data Mux"},
3663 {"IF1_1 6 ADC Swap Mux", "R/L", "TDM1 slot 67 Data Mux"},
3664 {"IF1_1 7 ADC Swap Mux", "L/L", "TDM1 slot 67 Data Mux"},
3665 {"IF1_1 7 ADC Swap Mux", "R/R", "TDM1 slot 67 Data Mux"},
3666 {"IF1_2 0 ADC Swap Mux", "L/R", "TDM2 slot 01 Data Mux"},
3667 {"IF1_2 0 ADC Swap Mux", "R/L", "TDM2 slot 01 Data Mux"},
3668 {"IF1_2 1 ADC Swap Mux", "L/L", "TDM2 slot 01 Data Mux"},
3669 {"IF1_2 1 ADC Swap Mux", "R/R", "TDM2 slot 01 Data Mux"},
3670 {"IF1_2 2 ADC Swap Mux", "L/R", "TDM2 slot 23 Data Mux"},
3671 {"IF1_2 2 ADC Swap Mux", "R/L", "TDM2 slot 23 Data Mux"},
3672 {"IF1_2 3 ADC Swap Mux", "L/L", "TDM2 slot 23 Data Mux"},
3673 {"IF1_2 3 ADC Swap Mux", "R/R", "TDM2 slot 23 Data Mux"},
3674 {"IF1_2 4 ADC Swap Mux", "L/R", "TDM2 slot 45 Data Mux"},
3675 {"IF1_2 4 ADC Swap Mux", "R/L", "TDM2 slot 45 Data Mux"},
3676 {"IF1_2 5 ADC Swap Mux", "L/L", "TDM2 slot 45 Data Mux"},
3677 {"IF1_2 5 ADC Swap Mux", "R/R", "TDM2 slot 45 Data Mux"},
3678 {"IF1_2 6 ADC Swap Mux", "L/R", "TDM2 slot 67 Data Mux"},
3679 {"IF1_2 6 ADC Swap Mux", "R/L", "TDM2 slot 67 Data Mux"},
3680 {"IF1_2 7 ADC Swap Mux", "L/L", "TDM2 slot 67 Data Mux"},
3681 {"IF1_2 7 ADC Swap Mux", "R/R", "TDM2 slot 67 Data Mux"},
3683 {"IF2_1 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3684 {"IF2_1 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3685 {"IF2_1 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3686 {"IF2_1 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3687 {"IF2_1 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3688 {"IF2_1 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3689 {"IF2_1 ADC Mux", "IF3 DAC", "IF3 DAC"},
3690 {"IF2_1 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3691 {"IF2_1 ADC", NULL, "IF2_1 ADC Mux"},
3692 {"IF2_1 ADC", NULL, "I2S2_1"},
3694 {"IF2_2 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3695 {"IF2_2 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3696 {"IF2_2 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3697 {"IF2_2 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3698 {"IF2_2 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3699 {"IF2_2 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3700 {"IF2_2 ADC Mux", "IF3 DAC", "IF3 DAC"},
3701 {"IF2_2 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3702 {"IF2_2 ADC", NULL, "IF2_2 ADC Mux"},
3703 {"IF2_2 ADC", NULL, "I2S2_2"},
3705 {"IF3 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3706 {"IF3 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3707 {"IF3 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3708 {"IF3 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3709 {"IF3 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3710 {"IF3 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3711 {"IF3 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3712 {"IF3 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3713 {"IF3 ADC", NULL, "IF3 ADC Mux"},
3714 {"IF3 ADC", NULL, "I2S3"},
3716 {"AIF1_1TX slot 0", NULL, "IF1_1 0 ADC Swap Mux"},
3717 {"AIF1_1TX slot 1", NULL, "IF1_1 1 ADC Swap Mux"},
3718 {"AIF1_1TX slot 2", NULL, "IF1_1 2 ADC Swap Mux"},
3719 {"AIF1_1TX slot 3", NULL, "IF1_1 3 ADC Swap Mux"},
3720 {"AIF1_1TX slot 4", NULL, "IF1_1 4 ADC Swap Mux"},
3721 {"AIF1_1TX slot 5", NULL, "IF1_1 5 ADC Swap Mux"},
3722 {"AIF1_1TX slot 6", NULL, "IF1_1 6 ADC Swap Mux"},
3723 {"AIF1_1TX slot 7", NULL, "IF1_1 7 ADC Swap Mux"},
3724 {"AIF1_2TX slot 0", NULL, "IF1_2 0 ADC Swap Mux"},
3725 {"AIF1_2TX slot 1", NULL, "IF1_2 1 ADC Swap Mux"},
3726 {"AIF1_2TX slot 2", NULL, "IF1_2 2 ADC Swap Mux"},
3727 {"AIF1_2TX slot 3", NULL, "IF1_2 3 ADC Swap Mux"},
3728 {"AIF1_2TX slot 4", NULL, "IF1_2 4 ADC Swap Mux"},
3729 {"AIF1_2TX slot 5", NULL, "IF1_2 5 ADC Swap Mux"},
3730 {"AIF1_2TX slot 6", NULL, "IF1_2 6 ADC Swap Mux"},
3731 {"AIF1_2TX slot 7", NULL, "IF1_2 7 ADC Swap Mux"},
3732 {"IF2_1 ADC Swap Mux", "L/R", "IF2_1 ADC"},
3733 {"IF2_1 ADC Swap Mux", "R/L", "IF2_1 ADC"},
3734 {"IF2_1 ADC Swap Mux", "L/L", "IF2_1 ADC"},
3735 {"IF2_1 ADC Swap Mux", "R/R", "IF2_1 ADC"},
3736 {"AIF2_1TX", NULL, "IF2_1 ADC Swap Mux"},
3737 {"IF2_2 ADC Swap Mux", "L/R", "IF2_2 ADC"},
3738 {"IF2_2 ADC Swap Mux", "R/L", "IF2_2 ADC"},
3739 {"IF2_2 ADC Swap Mux", "L/L", "IF2_2 ADC"},
3740 {"IF2_2 ADC Swap Mux", "R/R", "IF2_2 ADC"},
3741 {"AIF2_2TX", NULL, "IF2_2 ADC Swap Mux"},
3742 {"IF3 ADC Swap Mux", "L/R", "IF3 ADC"},
3743 {"IF3 ADC Swap Mux", "R/L", "IF3 ADC"},
3744 {"IF3 ADC Swap Mux", "L/L", "IF3 ADC"},
3745 {"IF3 ADC Swap Mux", "R/R", "IF3 ADC"},
3746 {"AIF3TX", NULL, "IF3 ADC Swap Mux"},
3748 {"IF1 DAC1", NULL, "AIF1RX"},
3749 {"IF1 DAC2", NULL, "AIF1RX"},
3750 {"IF1 DAC3", NULL, "AIF1RX"},
3751 {"IF2_1 DAC Swap Mux", "L/R", "AIF2_1RX"},
3752 {"IF2_1 DAC Swap Mux", "R/L", "AIF2_1RX"},
3753 {"IF2_1 DAC Swap Mux", "L/L", "AIF2_1RX"},
3754 {"IF2_1 DAC Swap Mux", "R/R", "AIF2_1RX"},
3755 {"IF2_2 DAC Swap Mux", "L/R", "AIF2_2RX"},
3756 {"IF2_2 DAC Swap Mux", "R/L", "AIF2_2RX"},
3757 {"IF2_2 DAC Swap Mux", "L/L", "AIF2_2RX"},
3758 {"IF2_2 DAC Swap Mux", "R/R", "AIF2_2RX"},
3759 {"IF2_1 DAC", NULL, "IF2_1 DAC Swap Mux"},
3760 {"IF2_2 DAC", NULL, "IF2_2 DAC Swap Mux"},
3761 {"IF3 DAC Swap Mux", "L/R", "AIF3RX"},
3762 {"IF3 DAC Swap Mux", "R/L", "AIF3RX"},
3763 {"IF3 DAC Swap Mux", "L/L", "AIF3RX"},
3764 {"IF3 DAC Swap Mux", "R/R", "AIF3RX"},
3765 {"IF3 DAC", NULL, "IF3 DAC Swap Mux"},
3767 {"IF1 DAC1", NULL, "I2S1_1"},
3768 {"IF1 DAC2", NULL, "I2S1_1"},
3769 {"IF1 DAC3", NULL, "I2S1_1"},
3770 {"IF2_1 DAC", NULL, "I2S2_1"},
3771 {"IF2_2 DAC", NULL, "I2S2_2"},
3772 {"IF3 DAC", NULL, "I2S3"},
3774 {"IF1 DAC1 L", NULL, "IF1 DAC1"},
3775 {"IF1 DAC1 R", NULL, "IF1 DAC1"},
3776 {"IF1 DAC2 L", NULL, "IF1 DAC2"},
3777 {"IF1 DAC2 R", NULL, "IF1 DAC2"},
3778 {"IF1 DAC3 L", NULL, "IF1 DAC3"},
3779 {"IF1 DAC3 R", NULL, "IF1 DAC3"},
3780 {"IF2_1 DAC L", NULL, "IF2_1 DAC"},
3781 {"IF2_1 DAC R", NULL, "IF2_1 DAC"},
3782 {"IF2_2 DAC L", NULL, "IF2_2 DAC"},
3783 {"IF2_2 DAC R", NULL, "IF2_2 DAC"},
3784 {"IF3 DAC L", NULL, "IF3 DAC"},
3785 {"IF3 DAC R", NULL, "IF3 DAC"},
3787 {"DAC L1 Mux", "IF1 DAC1", "IF1 DAC1 L"},
3788 {"DAC L1 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3789 {"DAC L1 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3790 {"DAC L1 Mux", "IF3 DAC", "IF3 DAC L"},
3791 {"DAC L1 Mux", NULL, "DAC Stereo1 Filter"},
3793 {"DAC R1 Mux", "IF1 DAC1", "IF1 DAC1 R"},
3794 {"DAC R1 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3795 {"DAC R1 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3796 {"DAC R1 Mux", "IF3 DAC", "IF3 DAC R"},
3797 {"DAC R1 Mux", NULL, "DAC Stereo1 Filter"},
3799 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
3800 {"DAC1 MIXL", "DAC1 Switch", "DAC L1 Mux"},
3801 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
3802 {"DAC1 MIXR", "DAC1 Switch", "DAC R1 Mux"},
3804 {"DAC1 MIX", NULL, "DAC1 MIXL"},
3805 {"DAC1 MIX", NULL, "DAC1 MIXR"},
3807 {"DAC L2 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3808 {"DAC L2 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3809 {"DAC L2 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3810 {"DAC L2 Mux", "IF3 DAC", "IF3 DAC L"},
3811 {"DAC L2 Mux", "Mono ADC MIX", "Mono ADC MIXL"},
3812 {"DAC L2 Mux", NULL, "DAC Mono Left Filter"},
3814 {"DAC R2 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3815 {"DAC R2 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3816 {"DAC R2 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3817 {"DAC R2 Mux", "IF3 DAC", "IF3 DAC R"},
3818 {"DAC R2 Mux", "Mono ADC MIX", "Mono ADC MIXR"},
3819 {"DAC R2 Mux", NULL, "DAC Mono Right Filter"},
3821 {"DAC L3 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3822 {"DAC L3 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3823 {"DAC L3 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3824 {"DAC L3 Mux", "IF3 DAC", "IF3 DAC L"},
3825 {"DAC L3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXL"},
3826 {"DAC L3 Mux", NULL, "DAC Stereo2 Filter"},
3828 {"DAC R3 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3829 {"DAC R3 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3830 {"DAC R3 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3831 {"DAC R3 Mux", "IF3 DAC", "IF3 DAC R"},
3832 {"DAC R3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXR"},
3833 {"DAC R3 Mux", NULL, "DAC Stereo2 Filter"},
3835 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3836 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
3837 {"Stereo1 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3838 {"Stereo1 DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3840 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3841 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
3842 {"Stereo1 DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3843 {"Stereo1 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3845 {"Stereo2 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3846 {"Stereo2 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3847 {"Stereo2 DAC MIXL", "DAC L3 Switch", "DAC L3 Mux"},
3849 {"Stereo2 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3850 {"Stereo2 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3851 {"Stereo2 DAC MIXR", "DAC R3 Switch", "DAC R3 Mux"},
3853 {"Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3854 {"Mono DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
3855 {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3856 {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3857 {"Mono DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
3858 {"Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3859 {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3860 {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3862 {"DAC MIXL", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
3863 {"DAC MIXL", "Stereo2 DAC Mixer", "Stereo2 DAC MIXL"},
3864 {"DAC MIXL", "Mono DAC Mixer", "Mono DAC MIXL"},
3865 {"DAC MIXR", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
3866 {"DAC MIXR", "Stereo2 DAC Mixer", "Stereo2 DAC MIXR"},
3867 {"DAC MIXR", "Mono DAC Mixer", "Mono DAC MIXR"},
3869 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
3870 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
3871 {"DAC L1 Source", "DMIC1", "DMIC L1"},
3872 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
3873 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
3874 {"DAC R1 Source", "DMIC1", "DMIC R1"},
3876 {"DAC L2 Source", "DAC2", "DAC L2 Mux"},
3877 {"DAC L2 Source", "Mono DAC Mixer", "Mono DAC MIXL"},
3878 {"DAC L2 Source", NULL, "DAC L2 Power"},
3879 {"DAC R2 Source", "DAC2", "DAC R2 Mux"},
3880 {"DAC R2 Source", "Mono DAC Mixer", "Mono DAC MIXR"},
3881 {"DAC R2 Source", NULL, "DAC R2 Power"},
3883 {"DAC L1", NULL, "DAC L1 Source"},
3884 {"DAC R1", NULL, "DAC R1 Source"},
3885 {"DAC L2", NULL, "DAC L2 Source"},
3886 {"DAC R2", NULL, "DAC R2 Source"},
3888 {"DAC L1", NULL, "DAC 1 Clock"},
3889 {"DAC R1", NULL, "DAC 1 Clock"},
3890 {"DAC L2", NULL, "DAC 2 Clock"},
3891 {"DAC R2", NULL, "DAC 2 Clock"},
3893 {"MONOVOL MIX", "DAC L2 Switch", "DAC L2"},
3894 {"MONOVOL MIX", "RECMIX2L Switch", "RECMIX2L"},
3895 {"MONOVOL MIX", "BST1 Switch", "BST1"},
3896 {"MONOVOL MIX", "BST2 Switch", "BST2"},
3897 {"MONOVOL MIX", "BST3 Switch", "BST3"},
3899 {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
3900 {"OUT MIXL", "INL Switch", "INL VOL"},
3901 {"OUT MIXL", "BST1 Switch", "BST1"},
3902 {"OUT MIXL", "BST2 Switch", "BST2"},
3903 {"OUT MIXL", "BST3 Switch", "BST3"},
3904 {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
3905 {"OUT MIXR", "INR Switch", "INR VOL"},
3906 {"OUT MIXR", "BST2 Switch", "BST2"},
3907 {"OUT MIXR", "BST3 Switch", "BST3"},
3908 {"OUT MIXR", "BST4 Switch", "BST4"},
3910 {"MONOVOL", "Switch", "MONOVOL MIX"},
3911 {"Mono MIX", "DAC L2 Switch", "DAC L2"},
3912 {"Mono MIX", "MONOVOL Switch", "MONOVOL"},
3913 {"Mono Amp", NULL, "Mono MIX"},
3914 {"Mono Amp", NULL, "Vref2"},
3915 {"Mono Amp", NULL, "CLKDET SYS"},
3916 {"Mono Amp", NULL, "CLKDET MONO"},
3917 {"Mono Playback", "Switch", "Mono Amp"},
3918 {"MONOOUT", NULL, "Mono Playback"},
3920 {"HP Amp", NULL, "DAC L1"},
3921 {"HP Amp", NULL, "DAC R1"},
3922 {"HP Amp", NULL, "Charge Pump"},
3923 {"HP Amp", NULL, "CLKDET SYS"},
3924 {"HP Amp", NULL, "CLKDET HP"},
3925 {"HP Amp", NULL, "CBJ Power"},
3926 {"HP Amp", NULL, "Vref2"},
3927 {"HPO Playback", "Switch", "HP Amp"},
3928 {"HPOL", NULL, "HPO Playback"},
3929 {"HPOR", NULL, "HPO Playback"},
3931 {"OUTVOL L", "Switch", "OUT MIXL"},
3932 {"OUTVOL R", "Switch", "OUT MIXR"},
3933 {"LOUT L MIX", "DAC L2 Switch", "DAC L2"},
3934 {"LOUT L MIX", "OUTVOL L Switch", "OUTVOL L"},
3935 {"LOUT R MIX", "DAC R2 Switch", "DAC R2"},
3936 {"LOUT R MIX", "OUTVOL R Switch", "OUTVOL R"},
3937 {"LOUT Amp", NULL, "LOUT L MIX"},
3938 {"LOUT Amp", NULL, "LOUT R MIX"},
3939 {"LOUT Amp", NULL, "Vref1"},
3940 {"LOUT Amp", NULL, "Vref2"},
3941 {"LOUT Amp", NULL, "CLKDET SYS"},
3942 {"LOUT Amp", NULL, "CLKDET LOUT"},
3943 {"LOUT L Playback", "Switch", "LOUT Amp"},
3944 {"LOUT R Playback", "Switch", "LOUT Amp"},
3945 {"LOUTL", NULL, "LOUT L Playback"},
3946 {"LOUTR", NULL, "LOUT R Playback"},
3948 {"PDM L Mux", "Mono DAC", "Mono DAC MIXL"},
3949 {"PDM L Mux", "Stereo1 DAC", "Stereo1 DAC MIXL"},
3950 {"PDM L Mux", "Stereo2 DAC", "Stereo2 DAC MIXL"},
3951 {"PDM L Mux", NULL, "PDM Power"},
3952 {"PDM R Mux", "Mono DAC", "Mono DAC MIXR"},
3953 {"PDM R Mux", "Stereo1 DAC", "Stereo1 DAC MIXR"},
3954 {"PDM R Mux", "Stereo2 DAC", "Stereo2 DAC MIXR"},
3955 {"PDM R Mux", NULL, "PDM Power"},
3956 {"PDM L Playback", "Switch", "PDM L Mux"},
3957 {"PDM R Playback", "Switch", "PDM R Mux"},
3958 {"PDML", NULL, "PDM L Playback"},
3959 {"PDMR", NULL, "PDM R Playback"},
3962 static int rt5665_hw_params(struct snd_pcm_substream *substream,
3963 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
3965 struct snd_soc_codec *codec = dai->codec;
3966 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
3967 unsigned int val_len = 0, val_clk, mask_clk, val_bits = 0x0100;
3968 int pre_div, frame_size;
3970 rt5665->lrck[dai->id] = params_rate(params);
3971 pre_div = rl6231_get_clk_info(rt5665->sysclk, rt5665->lrck[dai->id]);
3973 dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n",
3974 rt5665->lrck[dai->id], dai->id);
3977 frame_size = snd_soc_params_to_frame_size(params);
3978 if (frame_size < 0) {
3979 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
3983 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
3984 rt5665->lrck[dai->id], pre_div, dai->id);
3986 switch (params_width(params)) {
3991 val_len |= RT5665_I2S_DL_20;
3995 val_len |= RT5665_I2S_DL_24;
3999 val_len |= RT5665_I2S_DL_8;
4008 mask_clk = RT5665_I2S_PD1_MASK;
4009 val_clk = pre_div << RT5665_I2S_PD1_SFT;
4010 snd_soc_update_bits(codec, RT5665_I2S1_SDP,
4011 RT5665_I2S_DL_MASK, val_len);
4015 mask_clk = RT5665_I2S_PD2_MASK;
4016 val_clk = pre_div << RT5665_I2S_PD2_SFT;
4017 snd_soc_update_bits(codec, RT5665_I2S2_SDP,
4018 RT5665_I2S_DL_MASK, val_len);
4021 mask_clk = RT5665_I2S_PD3_MASK;
4022 val_clk = pre_div << RT5665_I2S_PD3_SFT;
4023 snd_soc_update_bits(codec, RT5665_I2S3_SDP,
4024 RT5665_I2S_DL_MASK, val_len);
4027 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
4031 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1, mask_clk, val_clk);
4032 snd_soc_update_bits(codec, RT5665_STO1_DAC_SIL_DET, 0x3700, val_bits);
4034 switch (rt5665->lrck[dai->id]) {
4036 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4037 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4038 RT5665_DAC_OSR_32 | RT5665_ADC_OSR_32);
4041 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4042 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4043 RT5665_DAC_OSR_64 | RT5665_ADC_OSR_64);
4046 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4047 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4048 RT5665_DAC_OSR_128 | RT5665_ADC_OSR_128);
4055 static int rt5665_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
4057 struct snd_soc_codec *codec = dai->codec;
4058 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4059 unsigned int reg_val = 0;
4061 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4062 case SND_SOC_DAIFMT_CBM_CFM:
4063 rt5665->master[dai->id] = 1;
4065 case SND_SOC_DAIFMT_CBS_CFS:
4066 reg_val |= RT5665_I2S_MS_S;
4067 rt5665->master[dai->id] = 0;
4073 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
4074 case SND_SOC_DAIFMT_NB_NF:
4076 case SND_SOC_DAIFMT_IB_NF:
4077 reg_val |= RT5665_I2S_BP_INV;
4083 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4084 case SND_SOC_DAIFMT_I2S:
4086 case SND_SOC_DAIFMT_LEFT_J:
4087 reg_val |= RT5665_I2S_DF_LEFT;
4089 case SND_SOC_DAIFMT_DSP_A:
4090 reg_val |= RT5665_I2S_DF_PCM_A;
4092 case SND_SOC_DAIFMT_DSP_B:
4093 reg_val |= RT5665_I2S_DF_PCM_B;
4102 snd_soc_update_bits(codec, RT5665_I2S1_SDP,
4103 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4104 RT5665_I2S_DF_MASK, reg_val);
4108 snd_soc_update_bits(codec, RT5665_I2S2_SDP,
4109 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4110 RT5665_I2S_DF_MASK, reg_val);
4113 snd_soc_update_bits(codec, RT5665_I2S3_SDP,
4114 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4115 RT5665_I2S_DF_MASK, reg_val);
4118 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
4124 static int rt5665_set_dai_sysclk(struct snd_soc_dai *dai,
4125 int clk_id, unsigned int freq, int dir)
4127 struct snd_soc_codec *codec = dai->codec;
4128 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4129 unsigned int reg_val = 0;
4131 if (freq == rt5665->sysclk && clk_id == rt5665->sysclk_src)
4135 case RT5665_SCLK_S_MCLK:
4136 reg_val |= RT5665_SCLK_SRC_MCLK;
4138 case RT5665_SCLK_S_PLL1:
4139 reg_val |= RT5665_SCLK_SRC_PLL1;
4141 case RT5665_SCLK_S_RCCLK:
4142 reg_val |= RT5665_SCLK_SRC_RCCLK;
4145 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
4148 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4149 RT5665_SCLK_SRC_MASK, reg_val);
4150 rt5665->sysclk = freq;
4151 rt5665->sysclk_src = clk_id;
4153 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4158 static int rt5665_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int Source,
4159 unsigned int freq_in, unsigned int freq_out)
4161 struct snd_soc_codec *codec = dai->codec;
4162 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4163 struct rl6231_pll_code pll_code;
4166 if (Source == rt5665->pll_src && freq_in == rt5665->pll_in &&
4167 freq_out == rt5665->pll_out)
4170 if (!freq_in || !freq_out) {
4171 dev_dbg(codec->dev, "PLL disabled\n");
4174 rt5665->pll_out = 0;
4175 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4176 RT5665_SCLK_SRC_MASK, RT5665_SCLK_SRC_MCLK);
4181 case RT5665_PLL1_S_MCLK:
4182 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4183 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_MCLK);
4185 case RT5665_PLL1_S_BCLK1:
4186 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4187 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK1);
4189 case RT5665_PLL1_S_BCLK2:
4190 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4191 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK2);
4193 case RT5665_PLL1_S_BCLK3:
4194 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4195 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK3);
4198 dev_err(codec->dev, "Unknown PLL Source %d\n", Source);
4202 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
4204 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
4208 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
4209 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4210 pll_code.n_code, pll_code.k_code);
4212 snd_soc_write(codec, RT5665_PLL_CTRL_1,
4213 pll_code.n_code << RT5665_PLL_N_SFT | pll_code.k_code);
4214 snd_soc_write(codec, RT5665_PLL_CTRL_2,
4215 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5665_PLL_M_SFT |
4216 pll_code.m_bp << RT5665_PLL_M_BP_SFT);
4218 rt5665->pll_in = freq_in;
4219 rt5665->pll_out = freq_out;
4220 rt5665->pll_src = Source;
4225 static int rt5665_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4226 unsigned int rx_mask, int slots, int slot_width)
4228 struct snd_soc_codec *codec = dai->codec;
4229 unsigned int val = 0;
4231 if (rx_mask || tx_mask)
4232 val |= RT5665_I2S1_MODE_TDM;
4236 val |= RT5665_TDM_IN_CH_4;
4237 val |= RT5665_TDM_OUT_CH_4;
4240 val |= RT5665_TDM_IN_CH_6;
4241 val |= RT5665_TDM_OUT_CH_6;
4244 val |= RT5665_TDM_IN_CH_8;
4245 val |= RT5665_TDM_OUT_CH_8;
4253 switch (slot_width) {
4255 val |= RT5665_TDM_IN_LEN_20;
4256 val |= RT5665_TDM_OUT_LEN_20;
4259 val |= RT5665_TDM_IN_LEN_24;
4260 val |= RT5665_TDM_OUT_LEN_24;
4263 val |= RT5665_TDM_IN_LEN_32;
4264 val |= RT5665_TDM_OUT_LEN_32;
4272 snd_soc_update_bits(codec, RT5665_TDM_CTRL_1,
4273 RT5665_I2S1_MODE_MASK | RT5665_TDM_IN_CH_MASK |
4274 RT5665_TDM_OUT_CH_MASK | RT5665_TDM_IN_LEN_MASK |
4275 RT5665_TDM_OUT_LEN_MASK, val);
4280 static int rt5665_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
4282 struct snd_soc_codec *codec = dai->codec;
4283 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4285 dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio);
4287 rt5665->bclk[dai->id] = ratio;
4293 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4294 RT5665_I2S_BCLK_MS2_MASK,
4295 RT5665_I2S_BCLK_MS2_64);
4298 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4299 RT5665_I2S_BCLK_MS3_MASK,
4300 RT5665_I2S_BCLK_MS3_64);
4308 static int rt5665_set_bias_level(struct snd_soc_codec *codec,
4309 enum snd_soc_bias_level level)
4311 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4314 case SND_SOC_BIAS_PREPARE:
4315 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
4316 RT5665_DIG_GATE_CTRL, RT5665_DIG_GATE_CTRL);
4319 case SND_SOC_BIAS_STANDBY:
4320 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
4321 RT5665_PWR_LDO, RT5665_PWR_LDO);
4322 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4323 RT5665_PWR_MB, RT5665_PWR_MB);
4324 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
4325 RT5665_DIG_GATE_CTRL, 0);
4327 case SND_SOC_BIAS_OFF:
4328 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
4330 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4341 static int rt5665_probe(struct snd_soc_codec *codec)
4343 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4345 rt5665->codec = codec;
4347 schedule_delayed_work(&rt5665->calibrate_work, msecs_to_jiffies(100));
4352 static int rt5665_remove(struct snd_soc_codec *codec)
4354 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4356 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4362 static int rt5665_suspend(struct snd_soc_codec *codec)
4364 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4366 regcache_cache_only(rt5665->regmap, true);
4367 regcache_mark_dirty(rt5665->regmap);
4371 static int rt5665_resume(struct snd_soc_codec *codec)
4373 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4375 regcache_cache_only(rt5665->regmap, false);
4376 regcache_sync(rt5665->regmap);
4381 #define rt5665_suspend NULL
4382 #define rt5665_resume NULL
4385 #define RT5665_STEREO_RATES SNDRV_PCM_RATE_8000_192000
4386 #define RT5665_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4387 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4389 static const struct snd_soc_dai_ops rt5665_aif_dai_ops = {
4390 .hw_params = rt5665_hw_params,
4391 .set_fmt = rt5665_set_dai_fmt,
4392 .set_sysclk = rt5665_set_dai_sysclk,
4393 .set_tdm_slot = rt5665_set_tdm_slot,
4394 .set_pll = rt5665_set_dai_pll,
4395 .set_bclk_ratio = rt5665_set_bclk_ratio,
4398 static struct snd_soc_dai_driver rt5665_dai[] = {
4400 .name = "rt5665-aif1_1",
4401 .id = RT5665_AIF1_1,
4403 .stream_name = "AIF1 Playback",
4406 .rates = RT5665_STEREO_RATES,
4407 .formats = RT5665_FORMATS,
4410 .stream_name = "AIF1_1 Capture",
4413 .rates = RT5665_STEREO_RATES,
4414 .formats = RT5665_FORMATS,
4416 .ops = &rt5665_aif_dai_ops,
4419 .name = "rt5665-aif1_2",
4420 .id = RT5665_AIF1_2,
4422 .stream_name = "AIF1_2 Capture",
4425 .rates = RT5665_STEREO_RATES,
4426 .formats = RT5665_FORMATS,
4428 .ops = &rt5665_aif_dai_ops,
4431 .name = "rt5665-aif2_1",
4432 .id = RT5665_AIF2_1,
4434 .stream_name = "AIF2_1 Playback",
4437 .rates = RT5665_STEREO_RATES,
4438 .formats = RT5665_FORMATS,
4441 .stream_name = "AIF2_1 Capture",
4444 .rates = RT5665_STEREO_RATES,
4445 .formats = RT5665_FORMATS,
4447 .ops = &rt5665_aif_dai_ops,
4450 .name = "rt5665-aif2_2",
4451 .id = RT5665_AIF2_2,
4453 .stream_name = "AIF2_2 Playback",
4456 .rates = RT5665_STEREO_RATES,
4457 .formats = RT5665_FORMATS,
4460 .stream_name = "AIF2_2 Capture",
4463 .rates = RT5665_STEREO_RATES,
4464 .formats = RT5665_FORMATS,
4466 .ops = &rt5665_aif_dai_ops,
4469 .name = "rt5665-aif3",
4472 .stream_name = "AIF3 Playback",
4475 .rates = RT5665_STEREO_RATES,
4476 .formats = RT5665_FORMATS,
4479 .stream_name = "AIF3 Capture",
4482 .rates = RT5665_STEREO_RATES,
4483 .formats = RT5665_FORMATS,
4485 .ops = &rt5665_aif_dai_ops,
4489 static struct snd_soc_codec_driver soc_codec_dev_rt5665 = {
4490 .probe = rt5665_probe,
4491 .remove = rt5665_remove,
4492 .suspend = rt5665_suspend,
4493 .resume = rt5665_resume,
4494 .set_bias_level = rt5665_set_bias_level,
4495 .idle_bias_off = true,
4496 .component_driver = {
4497 .controls = rt5665_snd_controls,
4498 .num_controls = ARRAY_SIZE(rt5665_snd_controls),
4499 .dapm_widgets = rt5665_dapm_widgets,
4500 .num_dapm_widgets = ARRAY_SIZE(rt5665_dapm_widgets),
4501 .dapm_routes = rt5665_dapm_routes,
4502 .num_dapm_routes = ARRAY_SIZE(rt5665_dapm_routes),
4507 static const struct regmap_config rt5665_regmap = {
4510 .max_register = 0x0400,
4511 .volatile_reg = rt5665_volatile_register,
4512 .readable_reg = rt5665_readable_register,
4513 .cache_type = REGCACHE_RBTREE,
4514 .reg_defaults = rt5665_reg,
4515 .num_reg_defaults = ARRAY_SIZE(rt5665_reg),
4516 .use_single_rw = true,
4519 static const struct i2c_device_id rt5665_i2c_id[] = {
4523 MODULE_DEVICE_TABLE(i2c, rt5665_i2c_id);
4525 static int rt5665_parse_dt(struct rt5665_priv *rt5665, struct device *dev)
4527 rt5665->pdata.in1_diff = of_property_read_bool(dev->of_node,
4528 "realtek,in1-differential");
4529 rt5665->pdata.in2_diff = of_property_read_bool(dev->of_node,
4530 "realtek,in2-differential");
4531 rt5665->pdata.in3_diff = of_property_read_bool(dev->of_node,
4532 "realtek,in3-differential");
4533 rt5665->pdata.in4_diff = of_property_read_bool(dev->of_node,
4534 "realtek,in4-differential");
4536 of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin",
4537 &rt5665->pdata.dmic1_data_pin);
4538 of_property_read_u32(dev->of_node, "realtek,dmic2-data-pin",
4539 &rt5665->pdata.dmic2_data_pin);
4540 of_property_read_u32(dev->of_node, "realtek,jd-src",
4541 &rt5665->pdata.jd_src);
4543 rt5665->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
4544 "realtek,ldo1-en-gpios", 0);
4549 static void rt5665_calibrate(struct rt5665_priv *rt5665)
4553 mutex_lock(&rt5665->calibrate_mutex);
4555 regcache_cache_bypass(rt5665->regmap, true);
4557 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4558 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
4559 regmap_write(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1, 0x0c26);
4560 regmap_write(rt5665->regmap, RT5665_MONOMIX_IN_GAIN, 0x021f);
4561 regmap_write(rt5665->regmap, RT5665_MONO_OUT, 0x480a);
4562 regmap_write(rt5665->regmap, RT5665_PWR_MIXER, 0x083f);
4563 regmap_write(rt5665->regmap, RT5665_PWR_DIG_1, 0x0180);
4564 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_1, 0x4040);
4565 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0000);
4566 regmap_write(rt5665->regmap, RT5665_DIG_MISC, 0x0001);
4567 regmap_write(rt5665->regmap, RT5665_MICBIAS_2, 0x0380);
4568 regmap_write(rt5665->regmap, RT5665_GLB_CLK, 0x8000);
4569 regmap_write(rt5665->regmap, RT5665_ADDA_CLK_1, 0x1000);
4570 regmap_write(rt5665->regmap, RT5665_CHOP_DAC, 0x3030);
4571 regmap_write(rt5665->regmap, RT5665_CALIB_ADC_CTRL, 0x3c05);
4572 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xaa3e);
4573 usleep_range(15000, 20000);
4574 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xfe7e);
4575 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_2, 0x0321);
4577 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_1, 0xfc00);
4580 regmap_read(rt5665->regmap, RT5665_HP_CALIB_STA_1, &value);
4582 usleep_range(10000, 10005);
4587 pr_err("HP Calibration Failure\n");
4588 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4589 regcache_cache_bypass(rt5665->regmap, false);
4596 regmap_write(rt5665->regmap, RT5665_MONO_AMP_CALIB_CTRL_1, 0x9e24);
4599 regmap_read(rt5665->regmap, RT5665_MONO_AMP_CALIB_STA1, &value);
4601 usleep_range(10000, 10005);
4606 pr_err("MONO Calibration Failure\n");
4607 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4608 regcache_cache_bypass(rt5665->regmap, false);
4615 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4616 regcache_cache_bypass(rt5665->regmap, false);
4618 regcache_mark_dirty(rt5665->regmap);
4619 regcache_sync(rt5665->regmap);
4621 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
4622 regmap_write(rt5665->regmap, RT5665_ASRC_8, 0x0120);
4625 mutex_unlock(&rt5665->calibrate_mutex);
4628 static void rt5665_calibrate_handler(struct work_struct *work)
4630 struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
4631 calibrate_work.work);
4633 while (!rt5665->codec->component.card->instantiated) {
4634 pr_debug("%s\n", __func__);
4635 usleep_range(10000, 15000);
4638 rt5665_calibrate(rt5665);
4641 static int rt5665_i2c_probe(struct i2c_client *i2c,
4642 const struct i2c_device_id *id)
4644 struct rt5665_platform_data *pdata = dev_get_platdata(&i2c->dev);
4645 struct rt5665_priv *rt5665;
4649 rt5665 = devm_kzalloc(&i2c->dev, sizeof(struct rt5665_priv),
4655 i2c_set_clientdata(i2c, rt5665);
4658 rt5665->pdata = *pdata;
4660 rt5665_parse_dt(rt5665, &i2c->dev);
4662 for (i = 0; i < ARRAY_SIZE(rt5665->supplies); i++)
4663 rt5665->supplies[i].supply = rt5665_supply_names[i];
4665 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5665->supplies),
4668 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
4672 ret = regulator_bulk_enable(ARRAY_SIZE(rt5665->supplies),
4675 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
4679 if (gpio_is_valid(rt5665->pdata.ldo1_en)) {
4680 if (devm_gpio_request_one(&i2c->dev, rt5665->pdata.ldo1_en,
4681 GPIOF_OUT_INIT_HIGH, "rt5665"))
4682 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
4685 /* Sleep for 300 ms miniumum */
4686 usleep_range(300000, 350000);
4688 rt5665->regmap = devm_regmap_init_i2c(i2c, &rt5665_regmap);
4689 if (IS_ERR(rt5665->regmap)) {
4690 ret = PTR_ERR(rt5665->regmap);
4691 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4696 regmap_read(rt5665->regmap, RT5665_DEVICE_ID, &val);
4697 if (val != DEVICE_ID) {
4699 "Device with ID register %x is not rt5665\n", val);
4703 regmap_read(rt5665->regmap, RT5665_RESET, &val);
4706 rt5665->id = CODEC_5666;
4709 rt5665->id = CODEC_5668;
4713 rt5665->id = CODEC_5665;
4717 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4719 /* line in diff mode*/
4720 if (rt5665->pdata.in1_diff)
4721 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
4722 RT5665_IN1_DF_MASK, RT5665_IN1_DF_MASK);
4723 if (rt5665->pdata.in2_diff)
4724 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
4725 RT5665_IN2_DF_MASK, RT5665_IN2_DF_MASK);
4726 if (rt5665->pdata.in3_diff)
4727 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
4728 RT5665_IN3_DF_MASK, RT5665_IN3_DF_MASK);
4729 if (rt5665->pdata.in4_diff)
4730 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
4731 RT5665_IN4_DF_MASK, RT5665_IN4_DF_MASK);
4734 if (rt5665->pdata.dmic1_data_pin != RT5665_DMIC1_NULL ||
4735 rt5665->pdata.dmic2_data_pin != RT5665_DMIC2_NULL) {
4736 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
4737 RT5665_GP9_PIN_MASK, RT5665_GP9_PIN_DMIC1_SCL);
4738 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4739 RT5665_GP8_PIN_MASK, RT5665_GP8_PIN_DMIC2_SCL);
4740 switch (rt5665->pdata.dmic1_data_pin) {
4741 case RT5665_DMIC1_DATA_IN2N:
4742 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4743 RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_IN2N);
4746 case RT5665_DMIC1_DATA_GPIO4:
4747 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4748 RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_GPIO4);
4749 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4750 RT5665_GP4_PIN_MASK, RT5665_GP4_PIN_DMIC1_SDA);
4754 dev_dbg(&i2c->dev, "no DMIC1\n");
4758 switch (rt5665->pdata.dmic2_data_pin) {
4759 case RT5665_DMIC2_DATA_IN2P:
4760 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4761 RT5665_DMIC_2_DP_MASK, RT5665_DMIC_2_DP_IN2P);
4764 case RT5665_DMIC2_DATA_GPIO5:
4765 regmap_update_bits(rt5665->regmap,
4767 RT5665_DMIC_2_DP_MASK,
4768 RT5665_DMIC_2_DP_GPIO5);
4769 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4770 RT5665_GP5_PIN_MASK, RT5665_GP5_PIN_DMIC2_SDA);
4774 dev_dbg(&i2c->dev, "no DMIC2\n");
4780 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0002);
4781 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
4782 0xf000 | RT5665_VREF_POW_MASK, 0xd000 | RT5665_VREF_POW_REG);
4783 /* Work around for pow_pump */
4784 regmap_update_bits(rt5665->regmap, RT5665_STO1_DAC_SIL_DET,
4785 RT5665_DEB_STO_DAC_MASK, RT5665_DEB_80_MS);
4787 regmap_update_bits(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1,
4788 RT5665_PM_HP_MASK, RT5665_PM_HP_HV);
4790 /* Set GPIO4,8 as input for combo jack */
4791 if (rt5665->id == CODEC_5666) {
4792 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
4793 RT5665_GP4_PF_MASK, RT5665_GP4_PF_IN);
4794 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_3,
4795 RT5665_GP8_PF_MASK, RT5665_GP8_PF_IN);
4798 /* Enhance performance*/
4799 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4800 RT5665_HP_DRIVER_MASK | RT5665_LDO1_DVO_MASK,
4801 RT5665_HP_DRIVER_5X | RT5665_LDO1_DVO_09);
4803 INIT_DELAYED_WORK(&rt5665->jack_detect_work,
4804 rt5665_jack_detect_handler);
4805 INIT_DELAYED_WORK(&rt5665->calibrate_work,
4806 rt5665_calibrate_handler);
4807 INIT_DELAYED_WORK(&rt5665->jd_check_work,
4808 rt5665_jd_check_handler);
4810 mutex_init(&rt5665->calibrate_mutex);
4813 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
4814 rt5665_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
4815 | IRQF_ONESHOT, "rt5665", rt5665);
4817 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
4821 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5665,
4822 rt5665_dai, ARRAY_SIZE(rt5665_dai));
4825 static int rt5665_i2c_remove(struct i2c_client *i2c)
4827 snd_soc_unregister_codec(&i2c->dev);
4832 static void rt5665_i2c_shutdown(struct i2c_client *client)
4834 struct rt5665_priv *rt5665 = i2c_get_clientdata(client);
4836 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4840 static const struct of_device_id rt5665_of_match[] = {
4841 {.compatible = "realtek,rt5665"},
4842 {.compatible = "realtek,rt5666"},
4843 {.compatible = "realtek,rt5668"},
4846 MODULE_DEVICE_TABLE(of, rt5665_of_match);
4850 static struct acpi_device_id rt5665_acpi_match[] = {
4856 MODULE_DEVICE_TABLE(acpi, rt5665_acpi_match);
4859 struct i2c_driver rt5665_i2c_driver = {
4862 .of_match_table = of_match_ptr(rt5665_of_match),
4863 .acpi_match_table = ACPI_PTR(rt5665_acpi_match),
4865 .probe = rt5665_i2c_probe,
4866 .remove = rt5665_i2c_remove,
4867 .shutdown = rt5665_i2c_shutdown,
4868 .id_table = rt5665_i2c_id,
4870 module_i2c_driver(rt5665_i2c_driver);
4872 MODULE_DESCRIPTION("ASoC RT5665 driver");
4873 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
4874 MODULE_LICENSE("GPL v2");
git.samba.org / sfrench / cifs-2.6.git / blob