sound/pci/rme9652/hdsp.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *   ALSA driver for RME Hammerfall DSP audio interface(s)
   4  *
   5  *      Copyright (c) 2002  Paul Davis
   6  *                          Marcus Andersson
   7  *                          Thomas Charbonnel
   8  */
   9
  10 #include <linux/init.h>
  11 #include <linux/delay.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/pci.h>
  14 #include <linux/firmware.h>
  15 #include <linux/module.h>
  16 #include <linux/math64.h>
  17 #include <linux/vmalloc.h>
  18 #include <linux/io.h>
  19 #include <linux/nospec.h>
  20
  21 #include <sound/core.h>
  22 #include <sound/control.h>
  23 #include <sound/pcm.h>
  24 #include <sound/info.h>
  25 #include <sound/asoundef.h>
  26 #include <sound/rawmidi.h>
  27 #include <sound/hwdep.h>
  28 #include <sound/initval.h>
  29 #include <sound/hdsp.h>
  30
  31 #include <asm/byteorder.h>
  32 #include <asm/current.h>
  33
  34 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
  35 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
  36 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable this card */
  37
  38 module_param_array(index, int, NULL, 0444);
  39 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
  40 module_param_array(id, charp, NULL, 0444);
  41 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
  42 module_param_array(enable, bool, NULL, 0444);
  43 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
  44 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
  45 MODULE_DESCRIPTION("RME Hammerfall DSP");
  46 MODULE_LICENSE("GPL");
  47 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
  48                 "{RME HDSP-9652},"
  49                 "{RME HDSP-9632}}");
  50 MODULE_FIRMWARE("rpm_firmware.bin");
  51 MODULE_FIRMWARE("multiface_firmware.bin");
  52 MODULE_FIRMWARE("multiface_firmware_rev11.bin");
  53 MODULE_FIRMWARE("digiface_firmware.bin");
  54 MODULE_FIRMWARE("digiface_firmware_rev11.bin");
  55
  56 #define HDSP_MAX_CHANNELS        26
  57 #define HDSP_MAX_DS_CHANNELS     14
  58 #define HDSP_MAX_QS_CHANNELS     8
  59 #define DIGIFACE_SS_CHANNELS     26
  60 #define DIGIFACE_DS_CHANNELS     14
  61 #define MULTIFACE_SS_CHANNELS    18
  62 #define MULTIFACE_DS_CHANNELS    14
  63 #define H9652_SS_CHANNELS        26
  64 #define H9652_DS_CHANNELS        14
  65 /* This does not include possible Analog Extension Boards
  66    AEBs are detected at card initialization
  67 */
  68 #define H9632_SS_CHANNELS        12
  69 #define H9632_DS_CHANNELS        8
  70 #define H9632_QS_CHANNELS        4
  71 #define RPM_CHANNELS             6
  72
  73 /* Write registers. These are defined as byte-offsets from the iobase value.
  74  */
  75 #define HDSP_resetPointer               0
  76 #define HDSP_freqReg                    0
  77 #define HDSP_outputBufferAddress        32
  78 #define HDSP_inputBufferAddress         36
  79 #define HDSP_controlRegister            64
  80 #define HDSP_interruptConfirmation      96
  81 #define HDSP_outputEnable               128
  82 #define HDSP_control2Reg                256
  83 #define HDSP_midiDataOut0               352
  84 #define HDSP_midiDataOut1               356
  85 #define HDSP_fifoData                   368
  86 #define HDSP_inputEnable                384
  87
  88 /* Read registers. These are defined as byte-offsets from the iobase value
  89  */
  90
  91 #define HDSP_statusRegister    0
  92 #define HDSP_timecode        128
  93 #define HDSP_status2Register 192
  94 #define HDSP_midiDataIn0     360
  95 #define HDSP_midiDataIn1     364
  96 #define HDSP_midiStatusOut0  384
  97 #define HDSP_midiStatusOut1  388
  98 #define HDSP_midiStatusIn0   392
  99 #define HDSP_midiStatusIn1   396
 100 #define HDSP_fifoStatus      400
 101
 102 /* the meters are regular i/o-mapped registers, but offset
 103    considerably from the rest. the peak registers are reset
 104    when read; the least-significant 4 bits are full-scale counters;
 105    the actual peak value is in the most-significant 24 bits.
 106 */
 107
 108 #define HDSP_playbackPeakLevel  4096  /* 26 * 32 bit values */
 109 #define HDSP_inputPeakLevel     4224  /* 26 * 32 bit values */
 110 #define HDSP_outputPeakLevel    4352  /* (26+2) * 32 bit values */
 111 #define HDSP_playbackRmsLevel   4612  /* 26 * 64 bit values */
 112 #define HDSP_inputRmsLevel      4868  /* 26 * 64 bit values */
 113
 114
 115 /* This is for H9652 cards
 116    Peak values are read downward from the base
 117    Rms values are read upward
 118    There are rms values for the outputs too
 119    26*3 values are read in ss mode
 120    14*3 in ds mode, with no gap between values
 121 */
 122 #define HDSP_9652_peakBase      7164
 123 #define HDSP_9652_rmsBase       4096
 124
 125 /* c.f. the hdsp_9632_meters_t struct */
 126 #define HDSP_9632_metersBase    4096
 127
 128 #define HDSP_IO_EXTENT     7168
 129
 130 /* control2 register bits */
 131
 132 #define HDSP_TMS                0x01
 133 #define HDSP_TCK                0x02
 134 #define HDSP_TDI                0x04
 135 #define HDSP_JTAG               0x08
 136 #define HDSP_PWDN               0x10
 137 #define HDSP_PROGRAM            0x020
 138 #define HDSP_CONFIG_MODE_0      0x040
 139 #define HDSP_CONFIG_MODE_1      0x080
 140 #define HDSP_VERSION_BIT        (0x100 | HDSP_S_LOAD)
 141 #define HDSP_BIGENDIAN_MODE     0x200
 142 #define HDSP_RD_MULTIPLE        0x400
 143 #define HDSP_9652_ENABLE_MIXER  0x800
 144 #define HDSP_S200               0x800
 145 #define HDSP_S300               (0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */
 146 #define HDSP_CYCLIC_MODE        0x1000
 147 #define HDSP_TDO                0x10000000
 148
 149 #define HDSP_S_PROGRAM      (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
 150 #define HDSP_S_LOAD         (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
 151
 152 /* Control Register bits */
 153
 154 #define HDSP_Start                (1<<0)  /* start engine */
 155 #define HDSP_Latency0             (1<<1)  /* buffer size = 2^n where n is defined by Latency{2,1,0} */
 156 #define HDSP_Latency1             (1<<2)  /* [ see above ] */
 157 #define HDSP_Latency2             (1<<3)  /* [ see above ] */
 158 #define HDSP_ClockModeMaster      (1<<4)  /* 1=Master, 0=Slave/Autosync */
 159 #define HDSP_AudioInterruptEnable (1<<5)  /* what do you think ? */
 160 #define HDSP_Frequency0           (1<<6)  /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
 161 #define HDSP_Frequency1           (1<<7)  /* 0=32kHz/64kHz/128kHz */
 162 #define HDSP_DoubleSpeed          (1<<8)  /* 0=normal speed, 1=double speed */
 163 #define HDSP_SPDIFProfessional    (1<<9)  /* 0=consumer, 1=professional */
 164 #define HDSP_SPDIFEmphasis        (1<<10) /* 0=none, 1=on */
 165 #define HDSP_SPDIFNonAudio        (1<<11) /* 0=off, 1=on */
 166 #define HDSP_SPDIFOpticalOut      (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
 167 #define HDSP_SyncRef2             (1<<13)
 168 #define HDSP_SPDIFInputSelect0    (1<<14)
 169 #define HDSP_SPDIFInputSelect1    (1<<15)
 170 #define HDSP_SyncRef0             (1<<16)
 171 #define HDSP_SyncRef1             (1<<17)
 172 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
 173 #define HDSP_XLRBreakoutCable     (1<<20) /* For H9632 cards */
 174 #define HDSP_Midi0InterruptEnable (1<<22)
 175 #define HDSP_Midi1InterruptEnable (1<<23)
 176 #define HDSP_LineOut              (1<<24)
 177 #define HDSP_ADGain0              (1<<25) /* From here : H9632 specific */
 178 #define HDSP_ADGain1              (1<<26)
 179 #define HDSP_DAGain0              (1<<27)
 180 #define HDSP_DAGain1              (1<<28)
 181 #define HDSP_PhoneGain0           (1<<29)
 182 #define HDSP_PhoneGain1           (1<<30)
 183 #define HDSP_QuadSpeed            (1<<31)
 184
 185 /* RPM uses some of the registers for special purposes */
 186 #define HDSP_RPM_Inp12            0x04A00
 187 #define HDSP_RPM_Inp12_Phon_6dB   0x00800  /* Dolby */
 188 #define HDSP_RPM_Inp12_Phon_0dB   0x00000  /* .. */
 189 #define HDSP_RPM_Inp12_Phon_n6dB  0x04000  /* inp_0 */
 190 #define HDSP_RPM_Inp12_Line_0dB   0x04200  /* Dolby+PRO */
 191 #define HDSP_RPM_Inp12_Line_n6dB  0x00200  /* PRO */
 192
 193 #define HDSP_RPM_Inp34            0x32000
 194 #define HDSP_RPM_Inp34_Phon_6dB   0x20000  /* SyncRef1 */
 195 #define HDSP_RPM_Inp34_Phon_0dB   0x00000  /* .. */
 196 #define HDSP_RPM_Inp34_Phon_n6dB  0x02000  /* SyncRef2 */
 197 #define HDSP_RPM_Inp34_Line_0dB   0x30000  /* SyncRef1+SyncRef0 */
 198 #define HDSP_RPM_Inp34_Line_n6dB  0x10000  /* SyncRef0 */
 199
 200 #define HDSP_RPM_Bypass           0x01000
 201
 202 #define HDSP_RPM_Disconnect       0x00001
 203
 204 #define HDSP_ADGainMask       (HDSP_ADGain0|HDSP_ADGain1)
 205 #define HDSP_ADGainMinus10dBV  HDSP_ADGainMask
 206 #define HDSP_ADGainPlus4dBu   (HDSP_ADGain0)
 207 #define HDSP_ADGainLowGain     0
 208
 209 #define HDSP_DAGainMask         (HDSP_DAGain0|HDSP_DAGain1)
 210 #define HDSP_DAGainHighGain      HDSP_DAGainMask
 211 #define HDSP_DAGainPlus4dBu     (HDSP_DAGain0)
 212 #define HDSP_DAGainMinus10dBV    0
 213
 214 #define HDSP_PhoneGainMask      (HDSP_PhoneGain0|HDSP_PhoneGain1)
 215 #define HDSP_PhoneGain0dB        HDSP_PhoneGainMask
 216 #define HDSP_PhoneGainMinus6dB  (HDSP_PhoneGain0)
 217 #define HDSP_PhoneGainMinus12dB  0
 218
 219 #define HDSP_LatencyMask    (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
 220 #define HDSP_FrequencyMask  (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
 221
 222 #define HDSP_SPDIFInputMask    (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
 223 #define HDSP_SPDIFInputADAT1    0
 224 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
 225 #define HDSP_SPDIFInputCdrom   (HDSP_SPDIFInputSelect1)
 226 #define HDSP_SPDIFInputAES     (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
 227
 228 #define HDSP_SyncRefMask        (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
 229 #define HDSP_SyncRef_ADAT1       0
 230 #define HDSP_SyncRef_ADAT2      (HDSP_SyncRef0)
 231 #define HDSP_SyncRef_ADAT3      (HDSP_SyncRef1)
 232 #define HDSP_SyncRef_SPDIF      (HDSP_SyncRef0|HDSP_SyncRef1)
 233 #define HDSP_SyncRef_WORD       (HDSP_SyncRef2)
 234 #define HDSP_SyncRef_ADAT_SYNC  (HDSP_SyncRef0|HDSP_SyncRef2)
 235
 236 /* Sample Clock Sources */
 237
 238 #define HDSP_CLOCK_SOURCE_AUTOSYNC           0
 239 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ     1
 240 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ   2
 241 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ     3
 242 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ     4
 243 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ   5
 244 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ     6
 245 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ    7
 246 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ  8
 247 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ    9
 248
 249 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
 250
 251 #define HDSP_SYNC_FROM_WORD      0
 252 #define HDSP_SYNC_FROM_SPDIF     1
 253 #define HDSP_SYNC_FROM_ADAT1     2
 254 #define HDSP_SYNC_FROM_ADAT_SYNC 3
 255 #define HDSP_SYNC_FROM_ADAT2     4
 256 #define HDSP_SYNC_FROM_ADAT3     5
 257
 258 /* SyncCheck status */
 259
 260 #define HDSP_SYNC_CHECK_NO_LOCK 0
 261 #define HDSP_SYNC_CHECK_LOCK    1
 262 #define HDSP_SYNC_CHECK_SYNC    2
 263
 264 /* AutoSync references - used by "autosync_ref" control switch */
 265
 266 #define HDSP_AUTOSYNC_FROM_WORD      0
 267 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
 268 #define HDSP_AUTOSYNC_FROM_SPDIF     2
 269 #define HDSP_AUTOSYNC_FROM_NONE      3
 270 #define HDSP_AUTOSYNC_FROM_ADAT1     4
 271 #define HDSP_AUTOSYNC_FROM_ADAT2     5
 272 #define HDSP_AUTOSYNC_FROM_ADAT3     6
 273
 274 /* Possible sources of S/PDIF input */
 275
 276 #define HDSP_SPDIFIN_OPTICAL  0 /* optical  (ADAT1) */
 277 #define HDSP_SPDIFIN_COAXIAL  1 /* coaxial (RCA) */
 278 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
 279 #define HDSP_SPDIFIN_AES      3 /* xlr for H9632 (AES)*/
 280
 281 #define HDSP_Frequency32KHz    HDSP_Frequency0
 282 #define HDSP_Frequency44_1KHz  HDSP_Frequency1
 283 #define HDSP_Frequency48KHz    (HDSP_Frequency1|HDSP_Frequency0)
 284 #define HDSP_Frequency64KHz    (HDSP_DoubleSpeed|HDSP_Frequency0)
 285 #define HDSP_Frequency88_2KHz  (HDSP_DoubleSpeed|HDSP_Frequency1)
 286 #define HDSP_Frequency96KHz    (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
 287 /* For H9632 cards */
 288 #define HDSP_Frequency128KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
 289 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
 290 #define HDSP_Frequency192KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
 291 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
 292         return 104857600000000 / rate; // 100 MHz
 293         return 110100480000000 / rate; // 105 MHz
 294 */
 295 #define DDS_NUMERATOR 104857600000000ULL;  /*  =  2^20 * 10^8 */
 296
 297 #define hdsp_encode_latency(x)       (((x)<<1) & HDSP_LatencyMask)
 298 #define hdsp_decode_latency(x)       (((x) & HDSP_LatencyMask)>>1)
 299
 300 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
 301 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
 302
 303 /* Status Register bits */
 304
 305 #define HDSP_audioIRQPending    (1<<0)
 306 #define HDSP_Lock2              (1<<1)     /* this is for Digiface and H9652 */
 307 #define HDSP_spdifFrequency3    HDSP_Lock2 /* this is for H9632 only */
 308 #define HDSP_Lock1              (1<<2)
 309 #define HDSP_Lock0              (1<<3)
 310 #define HDSP_SPDIFSync          (1<<4)
 311 #define HDSP_TimecodeLock       (1<<5)
 312 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
 313 #define HDSP_Sync2              (1<<16)
 314 #define HDSP_Sync1              (1<<17)
 315 #define HDSP_Sync0              (1<<18)
 316 #define HDSP_DoubleSpeedStatus  (1<<19)
 317 #define HDSP_ConfigError        (1<<20)
 318 #define HDSP_DllError           (1<<21)
 319 #define HDSP_spdifFrequency0    (1<<22)
 320 #define HDSP_spdifFrequency1    (1<<23)
 321 #define HDSP_spdifFrequency2    (1<<24)
 322 #define HDSP_SPDIFErrorFlag     (1<<25)
 323 #define HDSP_BufferID           (1<<26)
 324 #define HDSP_TimecodeSync       (1<<27)
 325 #define HDSP_AEBO               (1<<28) /* H9632 specific Analog Extension Boards */
 326 #define HDSP_AEBI               (1<<29) /* 0 = present, 1 = absent */
 327 #define HDSP_midi0IRQPending    (1<<30)
 328 #define HDSP_midi1IRQPending    (1<<31)
 329
 330 #define HDSP_spdifFrequencyMask    (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
 331 #define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\
 332                                       HDSP_spdifFrequency1|\
 333                                       HDSP_spdifFrequency2|\
 334                                       HDSP_spdifFrequency3)
 335
 336 #define HDSP_spdifFrequency32KHz   (HDSP_spdifFrequency0)
 337 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
 338 #define HDSP_spdifFrequency48KHz   (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
 339
 340 #define HDSP_spdifFrequency64KHz   (HDSP_spdifFrequency2)
 341 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
 342 #define HDSP_spdifFrequency96KHz   (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
 343
 344 /* This is for H9632 cards */
 345 #define HDSP_spdifFrequency128KHz   (HDSP_spdifFrequency0|\
 346                                      HDSP_spdifFrequency1|\
 347                                      HDSP_spdifFrequency2)
 348 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
 349 #define HDSP_spdifFrequency192KHz   (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
 350
 351 /* Status2 Register bits */
 352
 353 #define HDSP_version0     (1<<0)
 354 #define HDSP_version1     (1<<1)
 355 #define HDSP_version2     (1<<2)
 356 #define HDSP_wc_lock      (1<<3)
 357 #define HDSP_wc_sync      (1<<4)
 358 #define HDSP_inp_freq0    (1<<5)
 359 #define HDSP_inp_freq1    (1<<6)
 360 #define HDSP_inp_freq2    (1<<7)
 361 #define HDSP_SelSyncRef0  (1<<8)
 362 #define HDSP_SelSyncRef1  (1<<9)
 363 #define HDSP_SelSyncRef2  (1<<10)
 364
 365 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
 366
 367 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
 368 #define HDSP_systemFrequency32   (HDSP_inp_freq0)
 369 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
 370 #define HDSP_systemFrequency48   (HDSP_inp_freq0|HDSP_inp_freq1)
 371 #define HDSP_systemFrequency64   (HDSP_inp_freq2)
 372 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
 373 #define HDSP_systemFrequency96   (HDSP_inp_freq1|HDSP_inp_freq2)
 374 /* FIXME : more values for 9632 cards ? */
 375
 376 #define HDSP_SelSyncRefMask        (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
 377 #define HDSP_SelSyncRef_ADAT1      0
 378 #define HDSP_SelSyncRef_ADAT2      (HDSP_SelSyncRef0)
 379 #define HDSP_SelSyncRef_ADAT3      (HDSP_SelSyncRef1)
 380 #define HDSP_SelSyncRef_SPDIF      (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
 381 #define HDSP_SelSyncRef_WORD       (HDSP_SelSyncRef2)
 382 #define HDSP_SelSyncRef_ADAT_SYNC  (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
 383
 384 /* Card state flags */
 385
 386 #define HDSP_InitializationComplete  (1<<0)
 387 #define HDSP_FirmwareLoaded          (1<<1)
 388 #define HDSP_FirmwareCached          (1<<2)
 389
 390 /* FIFO wait times, defined in terms of 1/10ths of msecs */
 391
 392 #define HDSP_LONG_WAIT   5000
 393 #define HDSP_SHORT_WAIT  30
 394
 395 #define UNITY_GAIN                       32768
 396 #define MINUS_INFINITY_GAIN              0
 397
 398 /* the size of a substream (1 mono data stream) */
 399
 400 #define HDSP_CHANNEL_BUFFER_SAMPLES  (16*1024)
 401 #define HDSP_CHANNEL_BUFFER_BYTES    (4*HDSP_CHANNEL_BUFFER_SAMPLES)
 402
 403 /* the size of the area we need to allocate for DMA transfers. the
 404    size is the same regardless of the number of channels - the
 405    Multiface still uses the same memory area.
 406
 407    Note that we allocate 1 more channel than is apparently needed
 408    because the h/w seems to write 1 byte beyond the end of the last
 409    page. Sigh.
 410 */
 411
 412 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
 413 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
 414
 415 #define HDSP_FIRMWARE_SIZE      (24413 * 4)
 416
 417 struct hdsp_9632_meters {
 418     u32 input_peak[16];
 419     u32 playback_peak[16];
 420     u32 output_peak[16];
 421     u32 xxx_peak[16];
 422     u32 padding[64];
 423     u32 input_rms_low[16];
 424     u32 playback_rms_low[16];
 425     u32 output_rms_low[16];
 426     u32 xxx_rms_low[16];
 427     u32 input_rms_high[16];
 428     u32 playback_rms_high[16];
 429     u32 output_rms_high[16];
 430     u32 xxx_rms_high[16];
 431 };
 432
 433 struct hdsp_midi {
 434     struct hdsp             *hdsp;
 435     int                      id;
 436     struct snd_rawmidi           *rmidi;
 437     struct snd_rawmidi_substream *input;
 438     struct snd_rawmidi_substream *output;
 439     char                     istimer; /* timer in use */
 440     struct timer_list        timer;
 441     spinlock_t               lock;
 442     int                      pending;
 443 };
 444
 445 struct hdsp {
 446         spinlock_t            lock;
 447         struct snd_pcm_substream *capture_substream;
 448         struct snd_pcm_substream *playback_substream;
 449         struct hdsp_midi      midi[2];
 450         struct work_struct    midi_work;
 451         int                   use_midi_work;
 452         int                   precise_ptr;
 453         u32                   control_register;      /* cached value */
 454         u32                   control2_register;     /* cached value */
 455         u32                   creg_spdif;
 456         u32                   creg_spdif_stream;
 457         int                   clock_source_locked;
 458         char                 *card_name;         /* digiface/multiface/rpm */
 459         enum HDSP_IO_Type     io_type;               /* ditto, but for code use */
 460         unsigned short        firmware_rev;
 461         unsigned short        state;                 /* stores state bits */
 462         const struct firmware *firmware;
 463         u32                  *fw_uploaded;
 464         size_t                period_bytes;          /* guess what this is */
 465         unsigned char         max_channels;
 466         unsigned char         qs_in_channels;        /* quad speed mode for H9632 */
 467         unsigned char         ds_in_channels;
 468         unsigned char         ss_in_channels;       /* different for multiface/digiface */
 469         unsigned char         qs_out_channels;
 470         unsigned char         ds_out_channels;
 471         unsigned char         ss_out_channels;
 472         u32                   io_loopback;          /* output loopback channel states*/
 473
 474         struct snd_dma_buffer capture_dma_buf;
 475         struct snd_dma_buffer playback_dma_buf;
 476         unsigned char        *capture_buffer;       /* suitably aligned address */
 477         unsigned char        *playback_buffer;      /* suitably aligned address */
 478
 479         pid_t                 capture_pid;
 480         pid_t                 playback_pid;
 481         int                   running;
 482         int                   system_sample_rate;
 483         const char           *channel_map;
 484         int                   dev;
 485         int                   irq;
 486         unsigned long         port;
 487         void __iomem         *iobase;
 488         struct snd_card *card;
 489         struct snd_pcm *pcm;
 490         struct snd_hwdep          *hwdep;
 491         struct pci_dev       *pci;
 492         struct snd_kcontrol *spdif_ctl;
 493         unsigned short        mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
 494         unsigned int          dds_value; /* last value written to freq register */
 495 };
 496
 497 /* These tables map the ALSA channels 1..N to the channels that we
 498    need to use in order to find the relevant channel buffer. RME
 499    refer to this kind of mapping as between "the ADAT channel and
 500    the DMA channel." We index it using the logical audio channel,
 501    and the value is the DMA channel (i.e. channel buffer number)
 502    where the data for that channel can be read/written from/to.
 503 */
 504
 505 static const char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
 506         0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
 507         18, 19, 20, 21, 22, 23, 24, 25
 508 };
 509
 510 static const char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
 511         /* Analog */
 512         0, 1, 2, 3, 4, 5, 6, 7,
 513         /* ADAT 2 */
 514         16, 17, 18, 19, 20, 21, 22, 23,
 515         /* SPDIF */
 516         24, 25,
 517         -1, -1, -1, -1, -1, -1, -1, -1
 518 };
 519
 520 static const char channel_map_ds[HDSP_MAX_CHANNELS] = {
 521         /* ADAT channels are remapped */
 522         1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
 523         /* channels 12 and 13 are S/PDIF */
 524         24, 25,
 525         /* others don't exist */
 526         -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
 527 };
 528
 529 static const char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
 530         /* ADAT channels */
 531         0, 1, 2, 3, 4, 5, 6, 7,
 532         /* SPDIF */
 533         8, 9,
 534         /* Analog */
 535         10, 11,
 536         /* AO4S-192 and AI4S-192 extension boards */
 537         12, 13, 14, 15,
 538         /* others don't exist */
 539         -1, -1, -1, -1, -1, -1, -1, -1,
 540         -1, -1
 541 };
 542
 543 static const char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
 544         /* ADAT */
 545         1, 3, 5, 7,
 546         /* SPDIF */
 547         8, 9,
 548         /* Analog */
 549         10, 11,
 550         /* AO4S-192 and AI4S-192 extension boards */
 551         12, 13, 14, 15,
 552         /* others don't exist */
 553         -1, -1, -1, -1, -1, -1, -1, -1,
 554         -1, -1, -1, -1, -1, -1
 555 };
 556
 557 static const char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
 558         /* ADAT is disabled in this mode */
 559         /* SPDIF */
 560         8, 9,
 561         /* Analog */
 562         10, 11,
 563         /* AO4S-192 and AI4S-192 extension boards */
 564         12, 13, 14, 15,
 565         /* others don't exist */
 566         -1, -1, -1, -1, -1, -1, -1, -1,
 567         -1, -1, -1, -1, -1, -1, -1, -1,
 568         -1, -1
 569 };
 570
 571 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
 572 {
 573         return snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, size, dmab);
 574 }
 575
 576 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
 577 {
 578         if (dmab->area)
 579                 snd_dma_free_pages(dmab);
 580 }
 581
 582
 583 static const struct pci_device_id snd_hdsp_ids[] = {
 584         {
 585                 .vendor = PCI_VENDOR_ID_XILINX,
 586                 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
 587                 .subvendor = PCI_ANY_ID,
 588                 .subdevice = PCI_ANY_ID,
 589         }, /* RME Hammerfall-DSP */
 590         { 0, },
 591 };
 592
 593 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
 594
 595 /* prototypes */
 596 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
 597 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
 598 static int snd_hdsp_enable_io (struct hdsp *hdsp);
 599 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
 600 static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
 601 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
 602 static int hdsp_autosync_ref(struct hdsp *hdsp);
 603 static int snd_hdsp_set_defaults(struct hdsp *hdsp);
 604 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
 605
 606 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
 607 {
 608         switch (hdsp->io_type) {
 609         case Multiface:
 610         case Digiface:
 611         case RPM:
 612         default:
 613                 if (hdsp->firmware_rev == 0xa)
 614                         return (64 * out) + (32 + (in));
 615                 else
 616                         return (52 * out) + (26 + (in));
 617         case H9632:
 618                 return (32 * out) + (16 + (in));
 619         case H9652:
 620                 return (52 * out) + (26 + (in));
 621         }
 622 }
 623
 624 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
 625 {
 626         switch (hdsp->io_type) {
 627         case Multiface:
 628         case Digiface:
 629         case RPM:
 630         default:
 631                 if (hdsp->firmware_rev == 0xa)
 632                         return (64 * out) + in;
 633                 else
 634                         return (52 * out) + in;
 635         case H9632:
 636                 return (32 * out) + in;
 637         case H9652:
 638                 return (52 * out) + in;
 639         }
 640 }
 641
 642 static void hdsp_write(struct hdsp *hdsp, int reg, int val)
 643 {
 644         writel(val, hdsp->iobase + reg);
 645 }
 646
 647 static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
 648 {
 649         return readl (hdsp->iobase + reg);
 650 }
 651
 652 static int hdsp_check_for_iobox (struct hdsp *hdsp)
 653 {
 654         int i;
 655
 656         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
 657         for (i = 0; i < 500; i++) {
 658                 if (0 == (hdsp_read(hdsp, HDSP_statusRegister) &
 659                                         HDSP_ConfigError)) {
 660                         if (i) {
 661                                 dev_dbg(hdsp->card->dev,
 662                                         "IO box found after %d ms\n",
 663                                                 (20 * i));
 664                         }
 665                         return 0;
 666                 }
 667                 msleep(20);
 668         }
 669         dev_err(hdsp->card->dev, "no IO box connected!\n");
 670         hdsp->state &= ~HDSP_FirmwareLoaded;
 671         return -EIO;
 672 }
 673
 674 static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops,
 675                                unsigned int delay)
 676 {
 677         unsigned int i;
 678
 679         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
 680                 return 0;
 681
 682         for (i = 0; i != loops; ++i) {
 683                 if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError)
 684                         msleep(delay);
 685                 else {
 686                         dev_dbg(hdsp->card->dev, "iobox found after %ums!\n",
 687                                    i * delay);
 688                         return 0;
 689                 }
 690         }
 691
 692         dev_info(hdsp->card->dev, "no IO box connected!\n");
 693         hdsp->state &= ~HDSP_FirmwareLoaded;
 694         return -EIO;
 695 }
 696
 697 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
 698
 699         int i;
 700         unsigned long flags;
 701         const u32 *cache;
 702
 703         if (hdsp->fw_uploaded)
 704                 cache = hdsp->fw_uploaded;
 705         else {
 706                 if (!hdsp->firmware)
 707                         return -ENODEV;
 708                 cache = (u32 *)hdsp->firmware->data;
 709                 if (!cache)
 710                         return -ENODEV;
 711         }
 712
 713         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 714
 715                 dev_info(hdsp->card->dev, "loading firmware\n");
 716
 717                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
 718                 hdsp_write (hdsp, HDSP_fifoData, 0);
 719
 720                 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
 721                         dev_info(hdsp->card->dev,
 722                                  "timeout waiting for download preparation\n");
 723                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
 724                         return -EIO;
 725                 }
 726
 727                 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 728
 729                 for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) {
 730                         hdsp_write(hdsp, HDSP_fifoData, cache[i]);
 731                         if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
 732                                 dev_info(hdsp->card->dev,
 733                                          "timeout during firmware loading\n");
 734                                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
 735                                 return -EIO;
 736                         }
 737                 }
 738
 739                 hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT);
 740                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
 741
 742                 ssleep(3);
 743 #ifdef SNDRV_BIG_ENDIAN
 744                 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
 745 #else
 746                 hdsp->control2_register = 0;
 747 #endif
 748                 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
 749                 dev_info(hdsp->card->dev, "finished firmware loading\n");
 750
 751         }
 752         if (hdsp->state & HDSP_InitializationComplete) {
 753                 dev_info(hdsp->card->dev,
 754                          "firmware loaded from cache, restoring defaults\n");
 755                 spin_lock_irqsave(&hdsp->lock, flags);
 756                 snd_hdsp_set_defaults(hdsp);
 757                 spin_unlock_irqrestore(&hdsp->lock, flags);
 758         }
 759
 760         hdsp->state |= HDSP_FirmwareLoaded;
 761
 762         return 0;
 763 }
 764
 765 static int hdsp_get_iobox_version (struct hdsp *hdsp)
 766 {
 767         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 768
 769                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 770                 hdsp_write(hdsp, HDSP_fifoData, 0);
 771
 772                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
 773                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
 774                         hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 775                 }
 776
 777                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM);
 778                 hdsp_write (hdsp, HDSP_fifoData, 0);
 779                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
 780                         goto set_multi;
 781
 782                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 783                 hdsp_write(hdsp, HDSP_fifoData, 0);
 784                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
 785                         hdsp->io_type = Digiface;
 786                         dev_info(hdsp->card->dev, "Digiface found\n");
 787                         return 0;
 788                 }
 789
 790                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
 791                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 792                 hdsp_write(hdsp, HDSP_fifoData, 0);
 793                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0)
 794                         goto set_multi;
 795
 796                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
 797                 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
 798                 hdsp_write(hdsp, HDSP_fifoData, 0);
 799                 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
 800                         goto set_multi;
 801
 802                 hdsp->io_type = RPM;
 803                 dev_info(hdsp->card->dev, "RPM found\n");
 804                 return 0;
 805         } else {
 806                 /* firmware was already loaded, get iobox type */
 807                 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
 808                         hdsp->io_type = RPM;
 809                 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
 810                         hdsp->io_type = Multiface;
 811                 else
 812                         hdsp->io_type = Digiface;
 813         }
 814         return 0;
 815
 816 set_multi:
 817         hdsp->io_type = Multiface;
 818         dev_info(hdsp->card->dev, "Multiface found\n");
 819         return 0;
 820 }
 821
 822
 823 static int hdsp_request_fw_loader(struct hdsp *hdsp);
 824
 825 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
 826 {
 827         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
 828                 return 0;
 829         if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
 830                 hdsp->state &= ~HDSP_FirmwareLoaded;
 831                 if (! load_on_demand)
 832                         return -EIO;
 833                 dev_err(hdsp->card->dev, "firmware not present.\n");
 834                 /* try to load firmware */
 835                 if (! (hdsp->state & HDSP_FirmwareCached)) {
 836                         if (! hdsp_request_fw_loader(hdsp))
 837                                 return 0;
 838                         dev_err(hdsp->card->dev,
 839                                    "No firmware loaded nor cached, please upload firmware.\n");
 840                         return -EIO;
 841                 }
 842                 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
 843                         dev_err(hdsp->card->dev,
 844                                    "Firmware loading from cache failed, please upload manually.\n");
 845                         return -EIO;
 846                 }
 847         }
 848         return 0;
 849 }
 850
 851
 852 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
 853 {
 854         int i;
 855
 856         /* the fifoStatus registers reports on how many words
 857            are available in the command FIFO.
 858         */
 859
 860         for (i = 0; i < timeout; i++) {
 861
 862                 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
 863                         return 0;
 864
 865                 /* not very friendly, but we only do this during a firmware
 866                    load and changing the mixer, so we just put up with it.
 867                 */
 868
 869                 udelay (100);
 870         }
 871
 872         dev_warn(hdsp->card->dev,
 873                  "wait for FIFO status <= %d failed after %d iterations\n",
 874                     count, timeout);
 875         return -1;
 876 }
 877
 878 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
 879 {
 880         if (addr >= HDSP_MATRIX_MIXER_SIZE)
 881                 return 0;
 882
 883         return hdsp->mixer_matrix[addr];
 884 }
 885
 886 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
 887 {
 888         unsigned int ad;
 889
 890         if (addr >= HDSP_MATRIX_MIXER_SIZE)
 891                 return -1;
 892
 893         if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
 894
 895                 /* from martin bjornsen:
 896
 897                    "You can only write dwords to the
 898                    mixer memory which contain two
 899                    mixer values in the low and high
 900                    word. So if you want to change
 901                    value 0 you have to read value 1
 902                    from the cache and write both to
 903                    the first dword in the mixer
 904                    memory."
 905                 */
 906
 907                 if (hdsp->io_type == H9632 && addr >= 512)
 908                         return 0;
 909
 910                 if (hdsp->io_type == H9652 && addr >= 1352)
 911                         return 0;
 912
 913                 hdsp->mixer_matrix[addr] = data;
 914
 915
 916                 /* `addr' addresses a 16-bit wide address, but
 917                    the address space accessed via hdsp_write
 918                    uses byte offsets. put another way, addr
 919                    varies from 0 to 1351, but to access the
 920                    corresponding memory location, we need
 921                    to access 0 to 2703 ...
 922                 */
 923                 ad = addr/2;
 924
 925                 hdsp_write (hdsp, 4096 + (ad*4),
 926                             (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
 927                             hdsp->mixer_matrix[addr&0x7fe]);
 928
 929                 return 0;
 930
 931         } else {
 932
 933                 ad = (addr << 16) + data;
 934
 935                 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
 936                         return -1;
 937
 938                 hdsp_write (hdsp, HDSP_fifoData, ad);
 939                 hdsp->mixer_matrix[addr] = data;
 940
 941         }
 942
 943         return 0;
 944 }
 945
 946 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
 947 {
 948         unsigned long flags;
 949         int ret = 1;
 950
 951         spin_lock_irqsave(&hdsp->lock, flags);
 952         if ((hdsp->playback_pid != hdsp->capture_pid) &&
 953             (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
 954                 ret = 0;
 955         spin_unlock_irqrestore(&hdsp->lock, flags);
 956         return ret;
 957 }
 958
 959 static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
 960 {
 961         unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
 962         unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
 963
 964         /* For the 9632, the mask is different */
 965         if (hdsp->io_type == H9632)
 966                  rate_bits = (status & HDSP_spdifFrequencyMask_9632);
 967
 968         if (status & HDSP_SPDIFErrorFlag)
 969                 return 0;
 970
 971         switch (rate_bits) {
 972         case HDSP_spdifFrequency32KHz: return 32000;
 973         case HDSP_spdifFrequency44_1KHz: return 44100;
 974         case HDSP_spdifFrequency48KHz: return 48000;
 975         case HDSP_spdifFrequency64KHz: return 64000;
 976         case HDSP_spdifFrequency88_2KHz: return 88200;
 977         case HDSP_spdifFrequency96KHz: return 96000;
 978         case HDSP_spdifFrequency128KHz:
 979                 if (hdsp->io_type == H9632) return 128000;
 980                 break;
 981         case HDSP_spdifFrequency176_4KHz:
 982                 if (hdsp->io_type == H9632) return 176400;
 983                 break;
 984         case HDSP_spdifFrequency192KHz:
 985                 if (hdsp->io_type == H9632) return 192000;
 986                 break;
 987         default:
 988                 break;
 989         }
 990         dev_warn(hdsp->card->dev,
 991                  "unknown spdif frequency status; bits = 0x%x, status = 0x%x\n",
 992                  rate_bits, status);
 993         return 0;
 994 }
 995
 996 static int hdsp_external_sample_rate(struct hdsp *hdsp)
 997 {
 998         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
 999         unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
1000
1001         /* For the 9632 card, there seems to be no bit for indicating external
1002          * sample rate greater than 96kHz. The card reports the corresponding
1003          * single speed. So the best means seems to get spdif rate when
1004          * autosync reference is spdif */
1005         if (hdsp->io_type == H9632 &&
1006             hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)
1007                  return hdsp_spdif_sample_rate(hdsp);
1008
1009         switch (rate_bits) {
1010         case HDSP_systemFrequency32:   return 32000;
1011         case HDSP_systemFrequency44_1: return 44100;
1012         case HDSP_systemFrequency48:   return 48000;
1013         case HDSP_systemFrequency64:   return 64000;
1014         case HDSP_systemFrequency88_2: return 88200;
1015         case HDSP_systemFrequency96:   return 96000;
1016         default:
1017                 return 0;
1018         }
1019 }
1020
1021 static void hdsp_compute_period_size(struct hdsp *hdsp)
1022 {
1023         hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
1024 }
1025
1026 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
1027 {
1028         int position;
1029
1030         position = hdsp_read(hdsp, HDSP_statusRegister);
1031
1032         if (!hdsp->precise_ptr)
1033                 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
1034
1035         position &= HDSP_BufferPositionMask;
1036         position /= 4;
1037         position &= (hdsp->period_bytes/2) - 1;
1038         return position;
1039 }
1040
1041 static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
1042 {
1043         hdsp_write (hdsp, HDSP_resetPointer, 0);
1044         if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1045                 /* HDSP_resetPointer = HDSP_freqReg, which is strange and
1046                  * requires (?) to write again DDS value after a reset pointer
1047                  * (at least, it works like this) */
1048                 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
1049 }
1050
1051 static void hdsp_start_audio(struct hdsp *s)
1052 {
1053         s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
1054         hdsp_write(s, HDSP_controlRegister, s->control_register);
1055 }
1056
1057 static void hdsp_stop_audio(struct hdsp *s)
1058 {
1059         s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
1060         hdsp_write(s, HDSP_controlRegister, s->control_register);
1061 }
1062
1063 static void hdsp_silence_playback(struct hdsp *hdsp)
1064 {
1065         memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
1066 }
1067
1068 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
1069 {
1070         int n;
1071
1072         spin_lock_irq(&s->lock);
1073
1074         frames >>= 7;
1075         n = 0;
1076         while (frames) {
1077                 n++;
1078                 frames >>= 1;
1079         }
1080
1081         s->control_register &= ~HDSP_LatencyMask;
1082         s->control_register |= hdsp_encode_latency(n);
1083
1084         hdsp_write(s, HDSP_controlRegister, s->control_register);
1085
1086         hdsp_compute_period_size(s);
1087
1088         spin_unlock_irq(&s->lock);
1089
1090         return 0;
1091 }
1092
1093 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1094 {
1095         u64 n;
1096
1097         if (rate >= 112000)
1098                 rate /= 4;
1099         else if (rate >= 56000)
1100                 rate /= 2;
1101
1102         n = DDS_NUMERATOR;
1103         n = div_u64(n, rate);
1104         /* n should be less than 2^32 for being written to FREQ register */
1105         snd_BUG_ON(n >> 32);
1106         /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1107            value to write it after a reset */
1108         hdsp->dds_value = n;
1109         hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1110 }
1111
1112 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1113 {
1114         int reject_if_open = 0;
1115         int current_rate;
1116         int rate_bits;
1117
1118         /* ASSUMPTION: hdsp->lock is either held, or
1119            there is no need for it (e.g. during module
1120            initialization).
1121         */
1122
1123         if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1124                 if (called_internally) {
1125                         /* request from ctl or card initialization */
1126                         dev_err(hdsp->card->dev,
1127                                 "device is not running as a clock master: cannot set sample rate.\n");
1128                         return -1;
1129                 } else {
1130                         /* hw_param request while in AutoSync mode */
1131                         int external_freq = hdsp_external_sample_rate(hdsp);
1132                         int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1133
1134                         if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1135                                 dev_info(hdsp->card->dev,
1136                                          "Detected ADAT in double speed mode\n");
1137                         else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1138                                 dev_info(hdsp->card->dev,
1139                                          "Detected ADAT in quad speed mode\n");
1140                         else if (rate != external_freq) {
1141                                 dev_info(hdsp->card->dev,
1142                                          "No AutoSync source for requested rate\n");
1143                                 return -1;
1144                         }
1145                 }
1146         }
1147
1148         current_rate = hdsp->system_sample_rate;
1149
1150         /* Changing from a "single speed" to a "double speed" rate is
1151            not allowed if any substreams are open. This is because
1152            such a change causes a shift in the location of
1153            the DMA buffers and a reduction in the number of available
1154            buffers.
1155
1156            Note that a similar but essentially insoluble problem
1157            exists for externally-driven rate changes. All we can do
1158            is to flag rate changes in the read/write routines.  */
1159
1160         if (rate > 96000 && hdsp->io_type != H9632)
1161                 return -EINVAL;
1162
1163         switch (rate) {
1164         case 32000:
1165                 if (current_rate > 48000)
1166                         reject_if_open = 1;
1167                 rate_bits = HDSP_Frequency32KHz;
1168                 break;
1169         case 44100:
1170                 if (current_rate > 48000)
1171                         reject_if_open = 1;
1172                 rate_bits = HDSP_Frequency44_1KHz;
1173                 break;
1174         case 48000:
1175                 if (current_rate > 48000)
1176                         reject_if_open = 1;
1177                 rate_bits = HDSP_Frequency48KHz;
1178                 break;
1179         case 64000:
1180                 if (current_rate <= 48000 || current_rate > 96000)
1181                         reject_if_open = 1;
1182                 rate_bits = HDSP_Frequency64KHz;
1183                 break;
1184         case 88200:
1185                 if (current_rate <= 48000 || current_rate > 96000)
1186                         reject_if_open = 1;
1187                 rate_bits = HDSP_Frequency88_2KHz;
1188                 break;
1189         case 96000:
1190                 if (current_rate <= 48000 || current_rate > 96000)
1191                         reject_if_open = 1;
1192                 rate_bits = HDSP_Frequency96KHz;
1193                 break;
1194         case 128000:
1195                 if (current_rate < 128000)
1196                         reject_if_open = 1;
1197                 rate_bits = HDSP_Frequency128KHz;
1198                 break;
1199         case 176400:
1200                 if (current_rate < 128000)
1201                         reject_if_open = 1;
1202                 rate_bits = HDSP_Frequency176_4KHz;
1203                 break;
1204         case 192000:
1205                 if (current_rate < 128000)
1206                         reject_if_open = 1;
1207                 rate_bits = HDSP_Frequency192KHz;
1208                 break;
1209         default:
1210                 return -EINVAL;
1211         }
1212
1213         if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1214                 dev_warn(hdsp->card->dev,
1215                          "cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1216                             hdsp->capture_pid,
1217                             hdsp->playback_pid);
1218                 return -EBUSY;
1219         }
1220
1221         hdsp->control_register &= ~HDSP_FrequencyMask;
1222         hdsp->control_register |= rate_bits;
1223         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1224
1225         /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1226         if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1227                 hdsp_set_dds_value(hdsp, rate);
1228
1229         if (rate >= 128000) {
1230                 hdsp->channel_map = channel_map_H9632_qs;
1231         } else if (rate > 48000) {
1232                 if (hdsp->io_type == H9632)
1233                         hdsp->channel_map = channel_map_H9632_ds;
1234                 else
1235                         hdsp->channel_map = channel_map_ds;
1236         } else {
1237                 switch (hdsp->io_type) {
1238                 case RPM:
1239                 case Multiface:
1240                         hdsp->channel_map = channel_map_mf_ss;
1241                         break;
1242                 case Digiface:
1243                 case H9652:
1244                         hdsp->channel_map = channel_map_df_ss;
1245                         break;
1246                 case H9632:
1247                         hdsp->channel_map = channel_map_H9632_ss;
1248                         break;
1249                 default:
1250                         /* should never happen */
1251                         break;
1252                 }
1253         }
1254
1255         hdsp->system_sample_rate = rate;
1256
1257         return 0;
1258 }
1259
1260 /*----------------------------------------------------------------------------
1261    MIDI
1262   ----------------------------------------------------------------------------*/
1263
1264 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1265 {
1266         /* the hardware already does the relevant bit-mask with 0xff */
1267         if (id)
1268                 return hdsp_read(hdsp, HDSP_midiDataIn1);
1269         else
1270                 return hdsp_read(hdsp, HDSP_midiDataIn0);
1271 }
1272
1273 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1274 {
1275         /* the hardware already does the relevant bit-mask with 0xff */
1276         if (id)
1277                 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1278         else
1279                 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1280 }
1281
1282 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1283 {
1284         if (id)
1285                 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1286         else
1287                 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1288 }
1289
1290 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1291 {
1292         int fifo_bytes_used;
1293
1294         if (id)
1295                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1296         else
1297                 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1298
1299         if (fifo_bytes_used < 128)
1300                 return  128 - fifo_bytes_used;
1301         else
1302                 return 0;
1303 }
1304
1305 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1306 {
1307         while (snd_hdsp_midi_input_available (hdsp, id))
1308                 snd_hdsp_midi_read_byte (hdsp, id);
1309 }
1310
1311 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1312 {
1313         unsigned long flags;
1314         int n_pending;
1315         int to_write;
1316         int i;
1317         unsigned char buf[128];
1318
1319         /* Output is not interrupt driven */
1320
1321         spin_lock_irqsave (&hmidi->lock, flags);
1322         if (hmidi->output) {
1323                 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1324                         if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1325                                 if (n_pending > (int)sizeof (buf))
1326                                         n_pending = sizeof (buf);
1327
1328                                 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1329                                         for (i = 0; i < to_write; ++i)
1330                                                 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1331                                 }
1332                         }
1333                 }
1334         }
1335         spin_unlock_irqrestore (&hmidi->lock, flags);
1336         return 0;
1337 }
1338
1339 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1340 {
1341         unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1342         unsigned long flags;
1343         int n_pending;
1344         int i;
1345
1346         spin_lock_irqsave (&hmidi->lock, flags);
1347         if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1348                 if (hmidi->input) {
1349                         if (n_pending > (int)sizeof (buf))
1350                                 n_pending = sizeof (buf);
1351                         for (i = 0; i < n_pending; ++i)
1352                                 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1353                         if (n_pending)
1354                                 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1355                 } else {
1356                         /* flush the MIDI input FIFO */
1357                         while (--n_pending)
1358                                 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1359                 }
1360         }
1361         hmidi->pending = 0;
1362         if (hmidi->id)
1363                 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1364         else
1365                 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1366         hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1367         spin_unlock_irqrestore (&hmidi->lock, flags);
1368         return snd_hdsp_midi_output_write (hmidi);
1369 }
1370
1371 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1372 {
1373         struct hdsp *hdsp;
1374         struct hdsp_midi *hmidi;
1375         unsigned long flags;
1376         u32 ie;
1377
1378         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1379         hdsp = hmidi->hdsp;
1380         ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1381         spin_lock_irqsave (&hdsp->lock, flags);
1382         if (up) {
1383                 if (!(hdsp->control_register & ie)) {
1384                         snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1385                         hdsp->control_register |= ie;
1386                 }
1387         } else {
1388                 hdsp->control_register &= ~ie;
1389         }
1390
1391         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1392         spin_unlock_irqrestore (&hdsp->lock, flags);
1393 }
1394
1395 static void snd_hdsp_midi_output_timer(struct timer_list *t)
1396 {
1397         struct hdsp_midi *hmidi = from_timer(hmidi, t, timer);
1398         unsigned long flags;
1399
1400         snd_hdsp_midi_output_write(hmidi);
1401         spin_lock_irqsave (&hmidi->lock, flags);
1402
1403         /* this does not bump hmidi->istimer, because the
1404            kernel automatically removed the timer when it
1405            expired, and we are now adding it back, thus
1406            leaving istimer wherever it was set before.
1407         */
1408
1409         if (hmidi->istimer)
1410                 mod_timer(&hmidi->timer, 1 + jiffies);
1411
1412         spin_unlock_irqrestore (&hmidi->lock, flags);
1413 }
1414
1415 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1416 {
1417         struct hdsp_midi *hmidi;
1418         unsigned long flags;
1419
1420         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1421         spin_lock_irqsave (&hmidi->lock, flags);
1422         if (up) {
1423                 if (!hmidi->istimer) {
1424                         timer_setup(&hmidi->timer, snd_hdsp_midi_output_timer,
1425                                     0);
1426                         mod_timer(&hmidi->timer, 1 + jiffies);
1427                         hmidi->istimer++;
1428                 }
1429         } else {
1430                 if (hmidi->istimer && --hmidi->istimer <= 0)
1431                         del_timer (&hmidi->timer);
1432         }
1433         spin_unlock_irqrestore (&hmidi->lock, flags);
1434         if (up)
1435                 snd_hdsp_midi_output_write(hmidi);
1436 }
1437
1438 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1439 {
1440         struct hdsp_midi *hmidi;
1441
1442         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1443         spin_lock_irq (&hmidi->lock);
1444         snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1445         hmidi->input = substream;
1446         spin_unlock_irq (&hmidi->lock);
1447
1448         return 0;
1449 }
1450
1451 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1452 {
1453         struct hdsp_midi *hmidi;
1454
1455         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1456         spin_lock_irq (&hmidi->lock);
1457         hmidi->output = substream;
1458         spin_unlock_irq (&hmidi->lock);
1459
1460         return 0;
1461 }
1462
1463 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1464 {
1465         struct hdsp_midi *hmidi;
1466
1467         snd_hdsp_midi_input_trigger (substream, 0);
1468
1469         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1470         spin_lock_irq (&hmidi->lock);
1471         hmidi->input = NULL;
1472         spin_unlock_irq (&hmidi->lock);
1473
1474         return 0;
1475 }
1476
1477 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1478 {
1479         struct hdsp_midi *hmidi;
1480
1481         snd_hdsp_midi_output_trigger (substream, 0);
1482
1483         hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1484         spin_lock_irq (&hmidi->lock);
1485         hmidi->output = NULL;
1486         spin_unlock_irq (&hmidi->lock);
1487
1488         return 0;
1489 }
1490
1491 static const struct snd_rawmidi_ops snd_hdsp_midi_output =
1492 {
1493         .open =         snd_hdsp_midi_output_open,
1494         .close =        snd_hdsp_midi_output_close,
1495         .trigger =      snd_hdsp_midi_output_trigger,
1496 };
1497
1498 static const struct snd_rawmidi_ops snd_hdsp_midi_input =
1499 {
1500         .open =         snd_hdsp_midi_input_open,
1501         .close =        snd_hdsp_midi_input_close,
1502         .trigger =      snd_hdsp_midi_input_trigger,
1503 };
1504
1505 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1506 {
1507         char buf[40];
1508
1509         hdsp->midi[id].id = id;
1510         hdsp->midi[id].rmidi = NULL;
1511         hdsp->midi[id].input = NULL;
1512         hdsp->midi[id].output = NULL;
1513         hdsp->midi[id].hdsp = hdsp;
1514         hdsp->midi[id].istimer = 0;
1515         hdsp->midi[id].pending = 0;
1516         spin_lock_init (&hdsp->midi[id].lock);
1517
1518         snprintf(buf, sizeof(buf), "%s MIDI %d", card->shortname, id + 1);
1519         if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1520                 return -1;
1521
1522         sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1);
1523         hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1524
1525         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1526         snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1527
1528         hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1529                 SNDRV_RAWMIDI_INFO_INPUT |
1530                 SNDRV_RAWMIDI_INFO_DUPLEX;
1531
1532         return 0;
1533 }
1534
1535 /*-----------------------------------------------------------------------------
1536   Control Interface
1537   ----------------------------------------------------------------------------*/
1538
1539 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1540 {
1541         u32 val = 0;
1542         val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1543         val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1544         if (val & HDSP_SPDIFProfessional)
1545                 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1546         else
1547                 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1548         return val;
1549 }
1550
1551 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1552 {
1553         aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1554                          ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1555         if (val & HDSP_SPDIFProfessional)
1556                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1557         else
1558                 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1559 }
1560
1561 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1562 {
1563         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1564         uinfo->count = 1;
1565         return 0;
1566 }
1567
1568 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1569 {
1570         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1571
1572         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1573         return 0;
1574 }
1575
1576 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1577 {
1578         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1579         int change;
1580         u32 val;
1581
1582         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1583         spin_lock_irq(&hdsp->lock);
1584         change = val != hdsp->creg_spdif;
1585         hdsp->creg_spdif = val;
1586         spin_unlock_irq(&hdsp->lock);
1587         return change;
1588 }
1589
1590 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1591 {
1592         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1593         uinfo->count = 1;
1594         return 0;
1595 }
1596
1597 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1598 {
1599         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1600
1601         snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1602         return 0;
1603 }
1604
1605 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1606 {
1607         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1608         int change;
1609         u32 val;
1610
1611         val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1612         spin_lock_irq(&hdsp->lock);
1613         change = val != hdsp->creg_spdif_stream;
1614         hdsp->creg_spdif_stream = val;
1615         hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1616         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1617         spin_unlock_irq(&hdsp->lock);
1618         return change;
1619 }
1620
1621 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1622 {
1623         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1624         uinfo->count = 1;
1625         return 0;
1626 }
1627
1628 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1629 {
1630         ucontrol->value.iec958.status[0] = kcontrol->private_value;
1631         return 0;
1632 }
1633
1634 #define HDSP_SPDIF_IN(xname, xindex) \
1635 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1636   .name = xname, \
1637   .index = xindex, \
1638   .info = snd_hdsp_info_spdif_in, \
1639   .get = snd_hdsp_get_spdif_in, \
1640   .put = snd_hdsp_put_spdif_in }
1641
1642 static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1643 {
1644         return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1645 }
1646
1647 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1648 {
1649         hdsp->control_register &= ~HDSP_SPDIFInputMask;
1650         hdsp->control_register |= hdsp_encode_spdif_in(in);
1651         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1652         return 0;
1653 }
1654
1655 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1656 {
1657         static const char * const texts[4] = {
1658                 "Optical", "Coaxial", "Internal", "AES"
1659         };
1660         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1661
1662         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 4 : 3,
1663                                  texts);
1664 }
1665
1666 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1667 {
1668         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1669
1670         ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1671         return 0;
1672 }
1673
1674 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1675 {
1676         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1677         int change;
1678         unsigned int val;
1679
1680         if (!snd_hdsp_use_is_exclusive(hdsp))
1681                 return -EBUSY;
1682         val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1683         spin_lock_irq(&hdsp->lock);
1684         change = val != hdsp_spdif_in(hdsp);
1685         if (change)
1686                 hdsp_set_spdif_input(hdsp, val);
1687         spin_unlock_irq(&hdsp->lock);
1688         return change;
1689 }
1690
1691 #define HDSP_TOGGLE_SETTING(xname, xindex) \
1692 {   .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1693         .name = xname, \
1694         .private_value = xindex, \
1695         .info = snd_hdsp_info_toggle_setting, \
1696         .get = snd_hdsp_get_toggle_setting, \
1697         .put = snd_hdsp_put_toggle_setting \
1698 }
1699
1700 static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask)
1701 {
1702         return (hdsp->control_register & regmask) ? 1 : 0;
1703 }
1704
1705 static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out)
1706 {
1707         if (out)
1708                 hdsp->control_register |= regmask;
1709         else
1710                 hdsp->control_register &= ~regmask;
1711         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1712
1713         return 0;
1714 }
1715
1716 #define snd_hdsp_info_toggle_setting               snd_ctl_boolean_mono_info
1717
1718 static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol,
1719                 struct snd_ctl_elem_value *ucontrol)
1720 {
1721         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1722         u32 regmask = kcontrol->private_value;
1723
1724         spin_lock_irq(&hdsp->lock);
1725         ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask);
1726         spin_unlock_irq(&hdsp->lock);
1727         return 0;
1728 }
1729
1730 static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol,
1731                 struct snd_ctl_elem_value *ucontrol)
1732 {
1733         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1734         u32 regmask = kcontrol->private_value;
1735         int change;
1736         unsigned int val;
1737
1738         if (!snd_hdsp_use_is_exclusive(hdsp))
1739                 return -EBUSY;
1740         val = ucontrol->value.integer.value[0] & 1;
1741         spin_lock_irq(&hdsp->lock);
1742         change = (int) val != hdsp_toggle_setting(hdsp, regmask);
1743         if (change)
1744                 hdsp_set_toggle_setting(hdsp, regmask, val);
1745         spin_unlock_irq(&hdsp->lock);
1746         return change;
1747 }
1748
1749 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1750 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1751   .name = xname, \
1752   .index = xindex, \
1753   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1754   .info = snd_hdsp_info_spdif_sample_rate, \
1755   .get = snd_hdsp_get_spdif_sample_rate \
1756 }
1757
1758 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1759 {
1760         static const char * const texts[] = {
1761                 "32000", "44100", "48000", "64000", "88200", "96000",
1762                 "None", "128000", "176400", "192000"
1763         };
1764         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1765
1766         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1767                                  texts);
1768 }
1769
1770 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1771 {
1772         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1773
1774         switch (hdsp_spdif_sample_rate(hdsp)) {
1775         case 32000:
1776                 ucontrol->value.enumerated.item[0] = 0;
1777                 break;
1778         case 44100:
1779                 ucontrol->value.enumerated.item[0] = 1;
1780                 break;
1781         case 48000:
1782                 ucontrol->value.enumerated.item[0] = 2;
1783                 break;
1784         case 64000:
1785                 ucontrol->value.enumerated.item[0] = 3;
1786                 break;
1787         case 88200:
1788                 ucontrol->value.enumerated.item[0] = 4;
1789                 break;
1790         case 96000:
1791                 ucontrol->value.enumerated.item[0] = 5;
1792                 break;
1793         case 128000:
1794                 ucontrol->value.enumerated.item[0] = 7;
1795                 break;
1796         case 176400:
1797                 ucontrol->value.enumerated.item[0] = 8;
1798                 break;
1799         case 192000:
1800                 ucontrol->value.enumerated.item[0] = 9;
1801                 break;
1802         default:
1803                 ucontrol->value.enumerated.item[0] = 6;
1804         }
1805         return 0;
1806 }
1807
1808 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1809 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1810   .name = xname, \
1811   .index = xindex, \
1812   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1813   .info = snd_hdsp_info_system_sample_rate, \
1814   .get = snd_hdsp_get_system_sample_rate \
1815 }
1816
1817 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1818 {
1819         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1820         uinfo->count = 1;
1821         return 0;
1822 }
1823
1824 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1825 {
1826         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1827
1828         ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1829         return 0;
1830 }
1831
1832 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1833 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1834   .name = xname, \
1835   .index = xindex, \
1836   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1837   .info = snd_hdsp_info_autosync_sample_rate, \
1838   .get = snd_hdsp_get_autosync_sample_rate \
1839 }
1840
1841 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1842 {
1843         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1844         static const char * const texts[] = {
1845                 "32000", "44100", "48000", "64000", "88200", "96000",
1846                 "None", "128000", "176400", "192000"
1847         };
1848
1849         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1850                                  texts);
1851 }
1852
1853 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1854 {
1855         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1856
1857         switch (hdsp_external_sample_rate(hdsp)) {
1858         case 32000:
1859                 ucontrol->value.enumerated.item[0] = 0;
1860                 break;
1861         case 44100:
1862                 ucontrol->value.enumerated.item[0] = 1;
1863                 break;
1864         case 48000:
1865                 ucontrol->value.enumerated.item[0] = 2;
1866                 break;
1867         case 64000:
1868                 ucontrol->value.enumerated.item[0] = 3;
1869                 break;
1870         case 88200:
1871                 ucontrol->value.enumerated.item[0] = 4;
1872                 break;
1873         case 96000:
1874                 ucontrol->value.enumerated.item[0] = 5;
1875                 break;
1876         case 128000:
1877                 ucontrol->value.enumerated.item[0] = 7;
1878                 break;
1879         case 176400:
1880                 ucontrol->value.enumerated.item[0] = 8;
1881                 break;
1882         case 192000:
1883                 ucontrol->value.enumerated.item[0] = 9;
1884                 break;
1885         default:
1886                 ucontrol->value.enumerated.item[0] = 6;
1887         }
1888         return 0;
1889 }
1890
1891 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1892 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1893   .name = xname, \
1894   .index = xindex, \
1895   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1896   .info = snd_hdsp_info_system_clock_mode, \
1897   .get = snd_hdsp_get_system_clock_mode \
1898 }
1899
1900 static int hdsp_system_clock_mode(struct hdsp *hdsp)
1901 {
1902         if (hdsp->control_register & HDSP_ClockModeMaster)
1903                 return 0;
1904         else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1905                         return 0;
1906         return 1;
1907 }
1908
1909 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1910 {
1911         static const char * const texts[] = {"Master", "Slave" };
1912
1913         return snd_ctl_enum_info(uinfo, 1, 2, texts);
1914 }
1915
1916 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1917 {
1918         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1919
1920         ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1921         return 0;
1922 }
1923
1924 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1925 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1926   .name = xname, \
1927   .index = xindex, \
1928   .info = snd_hdsp_info_clock_source, \
1929   .get = snd_hdsp_get_clock_source, \
1930   .put = snd_hdsp_put_clock_source \
1931 }
1932
1933 static int hdsp_clock_source(struct hdsp *hdsp)
1934 {
1935         if (hdsp->control_register & HDSP_ClockModeMaster) {
1936                 switch (hdsp->system_sample_rate) {
1937                 case 32000:
1938                         return 1;
1939                 case 44100:
1940                         return 2;
1941                 case 48000:
1942                         return 3;
1943                 case 64000:
1944                         return 4;
1945                 case 88200:
1946                         return 5;
1947                 case 96000:
1948                         return 6;
1949                 case 128000:
1950                         return 7;
1951                 case 176400:
1952                         return 8;
1953                 case 192000:
1954                         return 9;
1955                 default:
1956                         return 3;
1957                 }
1958         } else {
1959                 return 0;
1960         }
1961 }
1962
1963 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
1964 {
1965         int rate;
1966         switch (mode) {
1967         case HDSP_CLOCK_SOURCE_AUTOSYNC:
1968                 if (hdsp_external_sample_rate(hdsp) != 0) {
1969                     if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
1970                         hdsp->control_register &= ~HDSP_ClockModeMaster;
1971                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1972                         return 0;
1973                     }
1974                 }
1975                 return -1;
1976         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
1977                 rate = 32000;
1978                 break;
1979         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
1980                 rate = 44100;
1981                 break;
1982         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
1983                 rate = 48000;
1984                 break;
1985         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
1986                 rate = 64000;
1987                 break;
1988         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
1989                 rate = 88200;
1990                 break;
1991         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
1992                 rate = 96000;
1993                 break;
1994         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
1995                 rate = 128000;
1996                 break;
1997         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
1998                 rate = 176400;
1999                 break;
2000         case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2001                 rate = 192000;
2002                 break;
2003         default:
2004                 rate = 48000;
2005         }
2006         hdsp->control_register |= HDSP_ClockModeMaster;
2007         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2008         hdsp_set_rate(hdsp, rate, 1);
2009         return 0;
2010 }
2011
2012 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2013 {
2014         static const char * const texts[] = {
2015                 "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz",
2016                 "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz",
2017                 "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz",
2018                 "Internal 192.0 KHz"
2019         };
2020         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2021
2022         return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
2023                                  texts);
2024 }
2025
2026 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2027 {
2028         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2029
2030         ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2031         return 0;
2032 }
2033
2034 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2035 {
2036         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2037         int change;
2038         int val;
2039
2040         if (!snd_hdsp_use_is_exclusive(hdsp))
2041                 return -EBUSY;
2042         val = ucontrol->value.enumerated.item[0];
2043         if (val < 0) val = 0;
2044         if (hdsp->io_type == H9632) {
2045                 if (val > 9)
2046                         val = 9;
2047         } else {
2048                 if (val > 6)
2049                         val = 6;
2050         }
2051         spin_lock_irq(&hdsp->lock);
2052         if (val != hdsp_clock_source(hdsp))
2053                 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2054         else
2055                 change = 0;
2056         spin_unlock_irq(&hdsp->lock);
2057         return change;
2058 }
2059
2060 #define snd_hdsp_info_clock_source_lock         snd_ctl_boolean_mono_info
2061
2062 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2063 {
2064         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2065
2066         ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2067         return 0;
2068 }
2069
2070 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2071 {
2072         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2073         int change;
2074
2075         change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2076         if (change)
2077                 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];
2078         return change;
2079 }
2080
2081 #define HDSP_DA_GAIN(xname, xindex) \
2082 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2083   .name = xname, \
2084   .index = xindex, \
2085   .info = snd_hdsp_info_da_gain, \
2086   .get = snd_hdsp_get_da_gain, \
2087   .put = snd_hdsp_put_da_gain \
2088 }
2089
2090 static int hdsp_da_gain(struct hdsp *hdsp)
2091 {
2092         switch (hdsp->control_register & HDSP_DAGainMask) {
2093         case HDSP_DAGainHighGain:
2094                 return 0;
2095         case HDSP_DAGainPlus4dBu:
2096                 return 1;
2097         case HDSP_DAGainMinus10dBV:
2098                 return 2;
2099         default:
2100                 return 1;
2101         }
2102 }
2103
2104 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2105 {
2106         hdsp->control_register &= ~HDSP_DAGainMask;
2107         switch (mode) {
2108         case 0:
2109                 hdsp->control_register |= HDSP_DAGainHighGain;
2110                 break;
2111         case 1:
2112                 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2113                 break;
2114         case 2:
2115                 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2116                 break;
2117         default:
2118                 return -1;
2119
2120         }
2121         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2122         return 0;
2123 }
2124
2125 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2126 {
2127         static const char * const texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2128
2129         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2130 }
2131
2132 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2133 {
2134         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2135
2136         ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2137         return 0;
2138 }
2139
2140 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2141 {
2142         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2143         int change;
2144         int val;
2145
2146         if (!snd_hdsp_use_is_exclusive(hdsp))
2147                 return -EBUSY;
2148         val = ucontrol->value.enumerated.item[0];
2149         if (val < 0) val = 0;
2150         if (val > 2) val = 2;
2151         spin_lock_irq(&hdsp->lock);
2152         if (val != hdsp_da_gain(hdsp))
2153                 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2154         else
2155                 change = 0;
2156         spin_unlock_irq(&hdsp->lock);
2157         return change;
2158 }
2159
2160 #define HDSP_AD_GAIN(xname, xindex) \
2161 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2162   .name = xname, \
2163   .index = xindex, \
2164   .info = snd_hdsp_info_ad_gain, \
2165   .get = snd_hdsp_get_ad_gain, \
2166   .put = snd_hdsp_put_ad_gain \
2167 }
2168
2169 static int hdsp_ad_gain(struct hdsp *hdsp)
2170 {
2171         switch (hdsp->control_register & HDSP_ADGainMask) {
2172         case HDSP_ADGainMinus10dBV:
2173                 return 0;
2174         case HDSP_ADGainPlus4dBu:
2175                 return 1;
2176         case HDSP_ADGainLowGain:
2177                 return 2;
2178         default:
2179                 return 1;
2180         }
2181 }
2182
2183 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2184 {
2185         hdsp->control_register &= ~HDSP_ADGainMask;
2186         switch (mode) {
2187         case 0:
2188                 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2189                 break;
2190         case 1:
2191                 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2192                 break;
2193         case 2:
2194                 hdsp->control_register |= HDSP_ADGainLowGain;
2195                 break;
2196         default:
2197                 return -1;
2198
2199         }
2200         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2201         return 0;
2202 }
2203
2204 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2205 {
2206         static const char * const texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2207
2208         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2209 }
2210
2211 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2212 {
2213         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2214
2215         ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2216         return 0;
2217 }
2218
2219 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2220 {
2221         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2222         int change;
2223         int val;
2224
2225         if (!snd_hdsp_use_is_exclusive(hdsp))
2226                 return -EBUSY;
2227         val = ucontrol->value.enumerated.item[0];
2228         if (val < 0) val = 0;
2229         if (val > 2) val = 2;
2230         spin_lock_irq(&hdsp->lock);
2231         if (val != hdsp_ad_gain(hdsp))
2232                 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2233         else
2234                 change = 0;
2235         spin_unlock_irq(&hdsp->lock);
2236         return change;
2237 }
2238
2239 #define HDSP_PHONE_GAIN(xname, xindex) \
2240 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2241   .name = xname, \
2242   .index = xindex, \
2243   .info = snd_hdsp_info_phone_gain, \
2244   .get = snd_hdsp_get_phone_gain, \
2245   .put = snd_hdsp_put_phone_gain \
2246 }
2247
2248 static int hdsp_phone_gain(struct hdsp *hdsp)
2249 {
2250         switch (hdsp->control_register & HDSP_PhoneGainMask) {
2251         case HDSP_PhoneGain0dB:
2252                 return 0;
2253         case HDSP_PhoneGainMinus6dB:
2254                 return 1;
2255         case HDSP_PhoneGainMinus12dB:
2256                 return 2;
2257         default:
2258                 return 0;
2259         }
2260 }
2261
2262 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2263 {
2264         hdsp->control_register &= ~HDSP_PhoneGainMask;
2265         switch (mode) {
2266         case 0:
2267                 hdsp->control_register |= HDSP_PhoneGain0dB;
2268                 break;
2269         case 1:
2270                 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2271                 break;
2272         case 2:
2273                 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2274                 break;
2275         default:
2276                 return -1;
2277
2278         }
2279         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2280         return 0;
2281 }
2282
2283 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2284 {
2285         static const char * const texts[] = {"0 dB", "-6 dB", "-12 dB"};
2286
2287         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2288 }
2289
2290 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2291 {
2292         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2293
2294         ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2295         return 0;
2296 }
2297
2298 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2299 {
2300         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2301         int change;
2302         int val;
2303
2304         if (!snd_hdsp_use_is_exclusive(hdsp))
2305                 return -EBUSY;
2306         val = ucontrol->value.enumerated.item[0];
2307         if (val < 0) val = 0;
2308         if (val > 2) val = 2;
2309         spin_lock_irq(&hdsp->lock);
2310         if (val != hdsp_phone_gain(hdsp))
2311                 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2312         else
2313                 change = 0;
2314         spin_unlock_irq(&hdsp->lock);
2315         return change;
2316 }
2317
2318 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2319 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2320   .name = xname, \
2321   .index = xindex, \
2322   .info = snd_hdsp_info_pref_sync_ref, \
2323   .get = snd_hdsp_get_pref_sync_ref, \
2324   .put = snd_hdsp_put_pref_sync_ref \
2325 }
2326
2327 static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2328 {
2329         /* Notice that this looks at the requested sync source,
2330            not the one actually in use.
2331         */
2332
2333         switch (hdsp->control_register & HDSP_SyncRefMask) {
2334         case HDSP_SyncRef_ADAT1:
2335                 return HDSP_SYNC_FROM_ADAT1;
2336         case HDSP_SyncRef_ADAT2:
2337                 return HDSP_SYNC_FROM_ADAT2;
2338         case HDSP_SyncRef_ADAT3:
2339                 return HDSP_SYNC_FROM_ADAT3;
2340         case HDSP_SyncRef_SPDIF:
2341                 return HDSP_SYNC_FROM_SPDIF;
2342         case HDSP_SyncRef_WORD:
2343                 return HDSP_SYNC_FROM_WORD;
2344         case HDSP_SyncRef_ADAT_SYNC:
2345                 return HDSP_SYNC_FROM_ADAT_SYNC;
2346         default:
2347                 return HDSP_SYNC_FROM_WORD;
2348         }
2349         return 0;
2350 }
2351
2352 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2353 {
2354         hdsp->control_register &= ~HDSP_SyncRefMask;
2355         switch (pref) {
2356         case HDSP_SYNC_FROM_ADAT1:
2357                 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2358                 break;
2359         case HDSP_SYNC_FROM_ADAT2:
2360                 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2361                 break;
2362         case HDSP_SYNC_FROM_ADAT3:
2363                 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2364                 break;
2365         case HDSP_SYNC_FROM_SPDIF:
2366                 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2367                 break;
2368         case HDSP_SYNC_FROM_WORD:
2369                 hdsp->control_register |= HDSP_SyncRef_WORD;
2370                 break;
2371         case HDSP_SYNC_FROM_ADAT_SYNC:
2372                 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2373                 break;
2374         default:
2375                 return -1;
2376         }
2377         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2378         return 0;
2379 }
2380
2381 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2382 {
2383         static const char * const texts[] = {
2384                 "Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3"
2385         };
2386         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2387         int num_items;
2388
2389         switch (hdsp->io_type) {
2390         case Digiface:
2391         case H9652:
2392                 num_items = 6;
2393                 break;
2394         case Multiface:
2395                 num_items = 4;
2396                 break;
2397         case H9632:
2398                 num_items = 3;
2399                 break;
2400         default:
2401                 return -EINVAL;
2402         }
2403
2404         return snd_ctl_enum_info(uinfo, 1, num_items, texts);
2405 }
2406
2407 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2408 {
2409         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2410
2411         ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2412         return 0;
2413 }
2414
2415 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2416 {
2417         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2418         int change, max;
2419         unsigned int val;
2420
2421         if (!snd_hdsp_use_is_exclusive(hdsp))
2422                 return -EBUSY;
2423
2424         switch (hdsp->io_type) {
2425         case Digiface:
2426         case H9652:
2427                 max = 6;
2428                 break;
2429         case Multiface:
2430                 max = 4;
2431                 break;
2432         case H9632:
2433                 max = 3;
2434                 break;
2435         default:
2436                 return -EIO;
2437         }
2438
2439         val = ucontrol->value.enumerated.item[0] % max;
2440         spin_lock_irq(&hdsp->lock);
2441         change = (int)val != hdsp_pref_sync_ref(hdsp);
2442         hdsp_set_pref_sync_ref(hdsp, val);
2443         spin_unlock_irq(&hdsp->lock);
2444         return change;
2445 }
2446
2447 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2448 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2449   .name = xname, \
2450   .index = xindex, \
2451   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2452   .info = snd_hdsp_info_autosync_ref, \
2453   .get = snd_hdsp_get_autosync_ref, \
2454 }
2455
2456 static int hdsp_autosync_ref(struct hdsp *hdsp)
2457 {
2458         /* This looks at the autosync selected sync reference */
2459         unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2460
2461         switch (status2 & HDSP_SelSyncRefMask) {
2462         case HDSP_SelSyncRef_WORD:
2463                 return HDSP_AUTOSYNC_FROM_WORD;
2464         case HDSP_SelSyncRef_ADAT_SYNC:
2465                 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2466         case HDSP_SelSyncRef_SPDIF:
2467                 return HDSP_AUTOSYNC_FROM_SPDIF;
2468         case HDSP_SelSyncRefMask:
2469                 return HDSP_AUTOSYNC_FROM_NONE;
2470         case HDSP_SelSyncRef_ADAT1:
2471                 return HDSP_AUTOSYNC_FROM_ADAT1;
2472         case HDSP_SelSyncRef_ADAT2:
2473                 return HDSP_AUTOSYNC_FROM_ADAT2;
2474         case HDSP_SelSyncRef_ADAT3:
2475                 return HDSP_AUTOSYNC_FROM_ADAT3;
2476         default:
2477                 return HDSP_AUTOSYNC_FROM_WORD;
2478         }
2479         return 0;
2480 }
2481
2482 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2483 {
2484         static const char * const texts[] = {
2485                 "Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3"
2486         };
2487
2488         return snd_ctl_enum_info(uinfo, 1, 7, texts);
2489 }
2490
2491 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2492 {
2493         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2494
2495         ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2496         return 0;
2497 }
2498
2499 #define HDSP_PRECISE_POINTER(xname, xindex) \
2500 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2501   .name = xname, \
2502   .index = xindex, \
2503   .info = snd_hdsp_info_precise_pointer, \
2504   .get = snd_hdsp_get_precise_pointer, \
2505   .put = snd_hdsp_put_precise_pointer \
2506 }
2507
2508 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2509 {
2510         if (precise)
2511                 hdsp->precise_ptr = 1;
2512         else
2513                 hdsp->precise_ptr = 0;
2514         return 0;
2515 }
2516
2517 #define snd_hdsp_info_precise_pointer           snd_ctl_boolean_mono_info
2518
2519 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2520 {
2521         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2522
2523         spin_lock_irq(&hdsp->lock);
2524         ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2525         spin_unlock_irq(&hdsp->lock);
2526         return 0;
2527 }
2528
2529 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2530 {
2531         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2532         int change;
2533         unsigned int val;
2534
2535         if (!snd_hdsp_use_is_exclusive(hdsp))
2536                 return -EBUSY;
2537         val = ucontrol->value.integer.value[0] & 1;
2538         spin_lock_irq(&hdsp->lock);
2539         change = (int)val != hdsp->precise_ptr;
2540         hdsp_set_precise_pointer(hdsp, val);
2541         spin_unlock_irq(&hdsp->lock);
2542         return change;
2543 }
2544
2545 #define HDSP_USE_MIDI_WORK(xname, xindex) \
2546 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2547   .name = xname, \
2548   .index = xindex, \
2549   .info = snd_hdsp_info_use_midi_work, \
2550   .get = snd_hdsp_get_use_midi_work, \
2551   .put = snd_hdsp_put_use_midi_work \
2552 }
2553
2554 static int hdsp_set_use_midi_work(struct hdsp *hdsp, int use_work)
2555 {
2556         if (use_work)
2557                 hdsp->use_midi_work = 1;
2558         else
2559                 hdsp->use_midi_work = 0;
2560         return 0;
2561 }
2562
2563 #define snd_hdsp_info_use_midi_work             snd_ctl_boolean_mono_info
2564
2565 static int snd_hdsp_get_use_midi_work(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2566 {
2567         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2568
2569         spin_lock_irq(&hdsp->lock);
2570         ucontrol->value.integer.value[0] = hdsp->use_midi_work;
2571         spin_unlock_irq(&hdsp->lock);
2572         return 0;
2573 }
2574
2575 static int snd_hdsp_put_use_midi_work(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2576 {
2577         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2578         int change;
2579         unsigned int val;
2580
2581         if (!snd_hdsp_use_is_exclusive(hdsp))
2582                 return -EBUSY;
2583         val = ucontrol->value.integer.value[0] & 1;
2584         spin_lock_irq(&hdsp->lock);
2585         change = (int)val != hdsp->use_midi_work;
2586         hdsp_set_use_midi_work(hdsp, val);
2587         spin_unlock_irq(&hdsp->lock);
2588         return change;
2589 }
2590
2591 #define HDSP_MIXER(xname, xindex) \
2592 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2593   .name = xname, \
2594   .index = xindex, \
2595   .device = 0, \
2596   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2597                  SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2598   .info = snd_hdsp_info_mixer, \
2599   .get = snd_hdsp_get_mixer, \
2600   .put = snd_hdsp_put_mixer \
2601 }
2602
2603 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2604 {
2605         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2606         uinfo->count = 3;
2607         uinfo->value.integer.min = 0;
2608         uinfo->value.integer.max = 65536;
2609         uinfo->value.integer.step = 1;
2610         return 0;
2611 }
2612
2613 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2614 {
2615         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2616         int source;
2617         int destination;
2618         int addr;
2619
2620         source = ucontrol->value.integer.value[0];
2621         destination = ucontrol->value.integer.value[1];
2622
2623         if (source >= hdsp->max_channels)
2624                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2625         else
2626                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2627
2628         spin_lock_irq(&hdsp->lock);
2629         ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2630         spin_unlock_irq(&hdsp->lock);
2631         return 0;
2632 }
2633
2634 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2635 {
2636         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2637         int change;
2638         int source;
2639         int destination;
2640         int gain;
2641         int addr;
2642
2643         if (!snd_hdsp_use_is_exclusive(hdsp))
2644                 return -EBUSY;
2645
2646         source = ucontrol->value.integer.value[0];
2647         destination = ucontrol->value.integer.value[1];
2648
2649         if (source >= hdsp->max_channels)
2650                 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2651         else
2652                 addr = hdsp_input_to_output_key(hdsp,source, destination);
2653
2654         gain = ucontrol->value.integer.value[2];
2655
2656         spin_lock_irq(&hdsp->lock);
2657         change = gain != hdsp_read_gain(hdsp, addr);
2658         if (change)
2659                 hdsp_write_gain(hdsp, addr, gain);
2660         spin_unlock_irq(&hdsp->lock);
2661         return change;
2662 }
2663
2664 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2665 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2666   .name = xname, \
2667   .index = xindex, \
2668   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2669   .info = snd_hdsp_info_sync_check, \
2670   .get = snd_hdsp_get_wc_sync_check \
2671 }
2672
2673 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2674 {
2675         static const char * const texts[] = {"No Lock", "Lock", "Sync" };
2676
2677         return snd_ctl_enum_info(uinfo, 1, 3, texts);
2678 }
2679
2680 static int hdsp_wc_sync_check(struct hdsp *hdsp)
2681 {
2682         int status2 = hdsp_read(hdsp, HDSP_status2Register);
2683         if (status2 & HDSP_wc_lock) {
2684                 if (status2 & HDSP_wc_sync)
2685                         return 2;
2686                 else
2687                          return 1;
2688         } else
2689                 return 0;
2690         return 0;
2691 }
2692
2693 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2694 {
2695         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2696
2697         ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2698         return 0;
2699 }
2700
2701 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2702 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2703   .name = xname, \
2704   .index = xindex, \
2705   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2706   .info = snd_hdsp_info_sync_check, \
2707   .get = snd_hdsp_get_spdif_sync_check \
2708 }
2709
2710 static int hdsp_spdif_sync_check(struct hdsp *hdsp)
2711 {
2712         int status = hdsp_read(hdsp, HDSP_statusRegister);
2713         if (status & HDSP_SPDIFErrorFlag)
2714                 return 0;
2715         else {
2716                 if (status & HDSP_SPDIFSync)
2717                         return 2;
2718                 else
2719                         return 1;
2720         }
2721         return 0;
2722 }
2723
2724 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2725 {
2726         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2727
2728         ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2729         return 0;
2730 }
2731
2732 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2733 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2734   .name = xname, \
2735   .index = xindex, \
2736   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2737   .info = snd_hdsp_info_sync_check, \
2738   .get = snd_hdsp_get_adatsync_sync_check \
2739 }
2740
2741 static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
2742 {
2743         int status = hdsp_read(hdsp, HDSP_statusRegister);
2744         if (status & HDSP_TimecodeLock) {
2745                 if (status & HDSP_TimecodeSync)
2746                         return 2;
2747                 else
2748                         return 1;
2749         } else
2750                 return 0;
2751 }
2752
2753 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2754 {
2755         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2756
2757         ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
2758         return 0;
2759 }
2760
2761 #define HDSP_ADAT_SYNC_CHECK \
2762 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2763   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2764   .info = snd_hdsp_info_sync_check, \
2765   .get = snd_hdsp_get_adat_sync_check \
2766 }
2767
2768 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
2769 {
2770         int status = hdsp_read(hdsp, HDSP_statusRegister);
2771
2772         if (status & (HDSP_Lock0>>idx)) {
2773                 if (status & (HDSP_Sync0>>idx))
2774                         return 2;
2775                 else
2776                         return 1;
2777         } else
2778                 return 0;
2779 }
2780
2781 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2782 {
2783         int offset;
2784         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2785
2786         offset = ucontrol->id.index - 1;
2787         if (snd_BUG_ON(offset < 0))
2788                 return -EINVAL;
2789
2790         switch (hdsp->io_type) {
2791         case Digiface:
2792         case H9652:
2793                 if (offset >= 3)
2794                         return -EINVAL;
2795                 break;
2796         case Multiface:
2797         case H9632:
2798                 if (offset >= 1)
2799                         return -EINVAL;
2800                 break;
2801         default:
2802                 return -EIO;
2803         }
2804
2805         ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
2806         return 0;
2807 }
2808
2809 #define HDSP_DDS_OFFSET(xname, xindex) \
2810 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2811   .name = xname, \
2812   .index = xindex, \
2813   .info = snd_hdsp_info_dds_offset, \
2814   .get = snd_hdsp_get_dds_offset, \
2815   .put = snd_hdsp_put_dds_offset \
2816 }
2817
2818 static int hdsp_dds_offset(struct hdsp *hdsp)
2819 {
2820         u64 n;
2821         unsigned int dds_value = hdsp->dds_value;
2822         int system_sample_rate = hdsp->system_sample_rate;
2823
2824         if (!dds_value)
2825                 return 0;
2826
2827         n = DDS_NUMERATOR;
2828         /*
2829          * dds_value = n / rate
2830          * rate = n / dds_value
2831          */
2832         n = div_u64(n, dds_value);
2833         if (system_sample_rate >= 112000)
2834                 n *= 4;
2835         else if (system_sample_rate >= 56000)
2836                 n *= 2;
2837         return ((int)n) - system_sample_rate;
2838 }
2839
2840 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
2841 {
2842         int rate = hdsp->system_sample_rate + offset_hz;
2843         hdsp_set_dds_value(hdsp, rate);
2844         return 0;
2845 }
2846
2847 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2848 {
2849         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2850         uinfo->count = 1;
2851         uinfo->value.integer.min = -5000;
2852         uinfo->value.integer.max = 5000;
2853         return 0;
2854 }
2855
2856 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2857 {
2858         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2859
2860         ucontrol->value.integer.value[0] = hdsp_dds_offset(hdsp);
2861         return 0;
2862 }
2863
2864 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2865 {
2866         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2867         int change;
2868         int val;
2869
2870         if (!snd_hdsp_use_is_exclusive(hdsp))
2871                 return -EBUSY;
2872         val = ucontrol->value.integer.value[0];
2873         spin_lock_irq(&hdsp->lock);
2874         if (val != hdsp_dds_offset(hdsp))
2875                 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
2876         else
2877                 change = 0;
2878         spin_unlock_irq(&hdsp->lock);
2879         return change;
2880 }
2881
2882 static const struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
2883 HDSP_DA_GAIN("DA Gain", 0),
2884 HDSP_AD_GAIN("AD Gain", 0),
2885 HDSP_PHONE_GAIN("Phones Gain", 0),
2886 HDSP_TOGGLE_SETTING("XLR Breakout Cable", HDSP_XLRBreakoutCable),
2887 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
2888 };
2889
2890 static const struct snd_kcontrol_new snd_hdsp_controls[] = {
2891 {
2892         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2893         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2894         .info =         snd_hdsp_control_spdif_info,
2895         .get =          snd_hdsp_control_spdif_get,
2896         .put =          snd_hdsp_control_spdif_put,
2897 },
2898 {
2899         .access =       SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2900         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2901         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2902         .info =         snd_hdsp_control_spdif_stream_info,
2903         .get =          snd_hdsp_control_spdif_stream_get,
2904         .put =          snd_hdsp_control_spdif_stream_put,
2905 },
2906 {
2907         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2908         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2909         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2910         .info =         snd_hdsp_control_spdif_mask_info,
2911         .get =          snd_hdsp_control_spdif_mask_get,
2912         .private_value = IEC958_AES0_NONAUDIO |
2913                          IEC958_AES0_PROFESSIONAL |
2914                          IEC958_AES0_CON_EMPHASIS,
2915 },
2916 {
2917         .access =       SNDRV_CTL_ELEM_ACCESS_READ,
2918         .iface =        SNDRV_CTL_ELEM_IFACE_PCM,
2919         .name =         SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2920         .info =         snd_hdsp_control_spdif_mask_info,
2921         .get =          snd_hdsp_control_spdif_mask_get,
2922         .private_value = IEC958_AES0_NONAUDIO |
2923                          IEC958_AES0_PROFESSIONAL |
2924                          IEC958_AES0_PRO_EMPHASIS,
2925 },
2926 HDSP_MIXER("Mixer", 0),
2927 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
2928 HDSP_TOGGLE_SETTING("IEC958 Output also on ADAT1", HDSP_SPDIFOpticalOut),
2929 HDSP_TOGGLE_SETTING("IEC958 Professional Bit", HDSP_SPDIFProfessional),
2930 HDSP_TOGGLE_SETTING("IEC958 Emphasis Bit", HDSP_SPDIFEmphasis),
2931 HDSP_TOGGLE_SETTING("IEC958 Non-audio Bit", HDSP_SPDIFNonAudio),
2932 /* 'Sample Clock Source' complies with the alsa control naming scheme */
2933 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
2934 {
2935         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2936         .name = "Sample Clock Source Locking",
2937         .info = snd_hdsp_info_clock_source_lock,
2938         .get = snd_hdsp_get_clock_source_lock,
2939         .put = snd_hdsp_put_clock_source_lock,
2940 },
2941 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2942 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
2943 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
2944 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
2945 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2946 /* 'External Rate' complies with the alsa control naming scheme */
2947 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2948 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2949 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
2950 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
2951 HDSP_TOGGLE_SETTING("Line Out", HDSP_LineOut),
2952 HDSP_PRECISE_POINTER("Precise Pointer", 0),
2953 HDSP_USE_MIDI_WORK("Use Midi Tasklet", 0),
2954 };
2955
2956
2957 static int hdsp_rpm_input12(struct hdsp *hdsp)
2958 {
2959         switch (hdsp->control_register & HDSP_RPM_Inp12) {
2960         case HDSP_RPM_Inp12_Phon_6dB:
2961                 return 0;
2962         case HDSP_RPM_Inp12_Phon_n6dB:
2963                 return 2;
2964         case HDSP_RPM_Inp12_Line_0dB:
2965                 return 3;
2966         case HDSP_RPM_Inp12_Line_n6dB:
2967                 return 4;
2968         }
2969         return 1;
2970 }
2971
2972
2973 static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2974 {
2975         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2976
2977         ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp);
2978         return 0;
2979 }
2980
2981
2982 static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode)
2983 {
2984         hdsp->control_register &= ~HDSP_RPM_Inp12;
2985         switch (mode) {
2986         case 0:
2987                 hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB;
2988                 break;
2989         case 1:
2990                 break;
2991         case 2:
2992                 hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB;
2993                 break;
2994         case 3:
2995                 hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB;
2996                 break;
2997         case 4:
2998                 hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB;
2999                 break;
3000         default:
3001                 return -1;
3002         }
3003
3004         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3005         return 0;
3006 }
3007
3008
3009 static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3010 {
3011         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3012         int change;
3013         int val;
3014
3015         if (!snd_hdsp_use_is_exclusive(hdsp))
3016                 return -EBUSY;
3017         val = ucontrol->value.enumerated.item[0];
3018         if (val < 0)
3019                 val = 0;
3020         if (val > 4)
3021                 val = 4;
3022         spin_lock_irq(&hdsp->lock);
3023         if (val != hdsp_rpm_input12(hdsp))
3024                 change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0;
3025         else
3026                 change = 0;
3027         spin_unlock_irq(&hdsp->lock);
3028         return change;
3029 }
3030
3031
3032 static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3033 {
3034         static const char * const texts[] = {
3035                 "Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB"
3036         };
3037
3038         return snd_ctl_enum_info(uinfo, 1, 5, texts);
3039 }
3040
3041
3042 static int hdsp_rpm_input34(struct hdsp *hdsp)
3043 {
3044         switch (hdsp->control_register & HDSP_RPM_Inp34) {
3045         case HDSP_RPM_Inp34_Phon_6dB:
3046                 return 0;
3047         case HDSP_RPM_Inp34_Phon_n6dB:
3048                 return 2;
3049         case HDSP_RPM_Inp34_Line_0dB:
3050                 return 3;
3051         case HDSP_RPM_Inp34_Line_n6dB:
3052                 return 4;
3053         }
3054         return 1;
3055 }
3056
3057
3058 static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3059 {
3060         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3061
3062         ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp);
3063         return 0;
3064 }
3065
3066
3067 static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode)
3068 {
3069         hdsp->control_register &= ~HDSP_RPM_Inp34;
3070         switch (mode) {
3071         case 0:
3072                 hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB;
3073                 break;
3074         case 1:
3075                 break;
3076         case 2:
3077                 hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB;
3078                 break;
3079         case 3:
3080                 hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB;
3081                 break;
3082         case 4:
3083                 hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB;
3084                 break;
3085         default:
3086                 return -1;
3087         }
3088
3089         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3090         return 0;
3091 }
3092
3093
3094 static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3095 {
3096         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3097         int change;
3098         int val;
3099
3100         if (!snd_hdsp_use_is_exclusive(hdsp))
3101                 return -EBUSY;
3102         val = ucontrol->value.enumerated.item[0];
3103         if (val < 0)
3104                 val = 0;
3105         if (val > 4)
3106                 val = 4;
3107         spin_lock_irq(&hdsp->lock);
3108         if (val != hdsp_rpm_input34(hdsp))
3109                 change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0;
3110         else
3111                 change = 0;
3112         spin_unlock_irq(&hdsp->lock);
3113         return change;
3114 }
3115
3116
3117 /* RPM Bypass switch */
3118 static int hdsp_rpm_bypass(struct hdsp *hdsp)
3119 {
3120         return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0;
3121 }
3122
3123
3124 static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3125 {
3126         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3127
3128         ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp);
3129         return 0;
3130 }
3131
3132
3133 static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on)
3134 {
3135         if (on)
3136                 hdsp->control_register |= HDSP_RPM_Bypass;
3137         else
3138                 hdsp->control_register &= ~HDSP_RPM_Bypass;
3139         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3140         return 0;
3141 }
3142
3143
3144 static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3145 {
3146         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3147         int change;
3148         unsigned int val;
3149
3150         if (!snd_hdsp_use_is_exclusive(hdsp))
3151                 return -EBUSY;
3152         val = ucontrol->value.integer.value[0] & 1;
3153         spin_lock_irq(&hdsp->lock);
3154         change = (int)val != hdsp_rpm_bypass(hdsp);
3155         hdsp_set_rpm_bypass(hdsp, val);
3156         spin_unlock_irq(&hdsp->lock);
3157         return change;
3158 }
3159
3160
3161 static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3162 {
3163         static const char * const texts[] = {"On", "Off"};
3164
3165         return snd_ctl_enum_info(uinfo, 1, 2, texts);
3166 }
3167
3168
3169 /* RPM Disconnect switch */
3170 static int hdsp_rpm_disconnect(struct hdsp *hdsp)
3171 {
3172         return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0;
3173 }
3174
3175
3176 static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3177 {
3178         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3179
3180         ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp);
3181         return 0;
3182 }
3183
3184
3185 static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on)
3186 {
3187         if (on)
3188                 hdsp->control_register |= HDSP_RPM_Disconnect;
3189         else
3190                 hdsp->control_register &= ~HDSP_RPM_Disconnect;
3191         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3192         return 0;
3193 }
3194
3195
3196 static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3197 {
3198         struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3199         int change;
3200         unsigned int val;
3201
3202         if (!snd_hdsp_use_is_exclusive(hdsp))
3203                 return -EBUSY;
3204         val = ucontrol->value.integer.value[0] & 1;
3205         spin_lock_irq(&hdsp->lock);
3206         change = (int)val != hdsp_rpm_disconnect(hdsp);
3207         hdsp_set_rpm_disconnect(hdsp, val);
3208         spin_unlock_irq(&hdsp->lock);
3209         return change;
3210 }
3211
3212 static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3213 {
3214         static const char * const texts[] = {"On", "Off"};
3215
3216         return snd_ctl_enum_info(uinfo, 1, 2, texts);
3217 }
3218
3219 static const struct snd_kcontrol_new snd_hdsp_rpm_controls[] = {
3220         {
3221                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3222                 .name = "RPM Bypass",
3223                 .get = snd_hdsp_get_rpm_bypass,
3224                 .put = snd_hdsp_put_rpm_bypass,
3225                 .info = snd_hdsp_info_rpm_bypass
3226         },
3227         {
3228                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3229                 .name = "RPM Disconnect",
3230                 .get = snd_hdsp_get_rpm_disconnect,
3231                 .put = snd_hdsp_put_rpm_disconnect,
3232                 .info = snd_hdsp_info_rpm_disconnect
3233         },
3234         {
3235                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3236                 .name = "Input 1/2",
3237                 .get = snd_hdsp_get_rpm_input12,
3238                 .put = snd_hdsp_put_rpm_input12,
3239                 .info = snd_hdsp_info_rpm_input
3240         },
3241         {
3242                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3243                 .name = "Input 3/4",
3244                 .get = snd_hdsp_get_rpm_input34,
3245                 .put = snd_hdsp_put_rpm_input34,
3246                 .info = snd_hdsp_info_rpm_input
3247         },
3248         HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3249         HDSP_MIXER("Mixer", 0)
3250 };
3251
3252 static const struct snd_kcontrol_new snd_hdsp_96xx_aeb =
3253         HDSP_TOGGLE_SETTING("Analog Extension Board",
3254                         HDSP_AnalogExtensionBoard);
3255 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3256
3257
3258 static bool hdsp_loopback_get(struct hdsp *const hdsp, const u8 channel)
3259 {
3260         return hdsp->io_loopback & (1 << channel);
3261 }
3262
3263 static int hdsp_loopback_set(struct hdsp *const hdsp, const u8 channel, const bool enable)
3264 {
3265         if (hdsp_loopback_get(hdsp, channel) == enable)
3266                 return 0;
3267
3268         hdsp->io_loopback ^= (1 << channel);
3269
3270         hdsp_write(hdsp, HDSP_inputEnable + (4 * (hdsp->max_channels + channel)), enable);
3271
3272         return 1;
3273 }
3274
3275 static int snd_hdsp_loopback_get(struct snd_kcontrol *const kcontrol,
3276                                  struct snd_ctl_elem_value *const ucontrol)
3277 {
3278         struct hdsp *const hdsp = snd_kcontrol_chip(kcontrol);
3279         const u8 channel = snd_ctl_get_ioff(kcontrol, &ucontrol->id);
3280
3281         if (channel >= hdsp->max_channels)
3282                 return -ENOENT;
3283
3284         ucontrol->value.integer.value[0] = hdsp_loopback_get(hdsp, channel);
3285
3286         return 0;
3287 }
3288
3289 static int snd_hdsp_loopback_put(struct snd_kcontrol *const kcontrol,
3290                                  struct snd_ctl_elem_value *const ucontrol)
3291 {
3292         struct hdsp *const hdsp = snd_kcontrol_chip(kcontrol);
3293         const u8 channel = snd_ctl_get_ioff(kcontrol, &ucontrol->id);
3294         const bool enable = ucontrol->value.integer.value[0] & 1;
3295
3296         if (channel >= hdsp->max_channels)
3297                 return -ENOENT;
3298
3299         return hdsp_loopback_set(hdsp, channel, enable);
3300 }
3301
3302 static struct snd_kcontrol_new snd_hdsp_loopback_control = {
3303         .iface = SNDRV_CTL_ELEM_IFACE_HWDEP,
3304         .name = "Output Loopback",
3305         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
3306         .info = snd_ctl_boolean_mono_info,
3307         .get = snd_hdsp_loopback_get,
3308         .put = snd_hdsp_loopback_put
3309 };
3310
3311 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3312 {
3313         unsigned int idx;
3314         int err;
3315         struct snd_kcontrol *kctl;
3316
3317         if (hdsp->io_type == RPM) {
3318                 /* RPM Bypass, Disconnect and Input switches */
3319                 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) {
3320                         err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp));
3321                         if (err < 0)
3322                                 return err;
3323                 }
3324                 return 0;
3325         }
3326
3327         for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3328                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0)
3329                         return err;
3330                 if (idx == 1)   /* IEC958 (S/PDIF) Stream */
3331                         hdsp->spdif_ctl = kctl;
3332         }
3333
3334         /* ADAT SyncCheck status */
3335         snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3336         snd_hdsp_adat_sync_check.index = 1;
3337         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3338                 return err;
3339         if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3340                 for (idx = 1; idx < 3; ++idx) {
3341                         snd_hdsp_adat_sync_check.index = idx+1;
3342                         if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3343                                 return err;
3344                 }
3345         }
3346
3347         /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3348         if (hdsp->io_type == H9632) {
3349                 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3350                         if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0)
3351                                 return err;
3352                 }
3353         }
3354
3355         /* Output loopback controls for H9632 cards */
3356         if (hdsp->io_type == H9632) {
3357                 snd_hdsp_loopback_control.count = hdsp->max_channels;
3358                 kctl = snd_ctl_new1(&snd_hdsp_loopback_control, hdsp);
3359                 if (kctl == NULL)
3360                         return -ENOMEM;
3361                 err = snd_ctl_add(card, kctl);
3362                 if (err < 0)
3363                         return err;
3364         }
3365
3366         /* AEB control for H96xx card */
3367         if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3368                 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0)
3369                                 return err;
3370         }
3371
3372         return 0;
3373 }
3374
3375 /*------------------------------------------------------------
3376    /proc interface
3377  ------------------------------------------------------------*/
3378
3379 static void
3380 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3381 {
3382         struct hdsp *hdsp = entry->private_data;
3383         unsigned int status;
3384         unsigned int status2;
3385         char *pref_sync_ref;
3386         char *autosync_ref;
3387         char *system_clock_mode;
3388         char *clock_source;
3389         int x;
3390
3391         status = hdsp_read(hdsp, HDSP_statusRegister);
3392         status2 = hdsp_read(hdsp, HDSP_status2Register);
3393
3394         snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name,
3395                     hdsp->card->number + 1);
3396         snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3397                     hdsp->capture_buffer, hdsp->playback_buffer);
3398         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3399                     hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3400         snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3401         snd_iprintf(buffer, "Control2 register: 0x%x\n",
3402                     hdsp->control2_register);
3403         snd_iprintf(buffer, "Status register: 0x%x\n", status);
3404         snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3405
3406         if (hdsp_check_for_iobox(hdsp)) {
3407                 snd_iprintf(buffer, "No I/O box connected.\n"
3408                             "Please connect one and upload firmware.\n");
3409                 return;
3410         }
3411
3412         if (hdsp_check_for_firmware(hdsp, 0)) {
3413                 if (hdsp->state & HDSP_FirmwareCached) {
3414                         if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3415                                 snd_iprintf(buffer, "Firmware loading from "
3416                                             "cache failed, "
3417                                             "please upload manually.\n");
3418                                 return;
3419                         }
3420                 } else {
3421                         int err;
3422
3423                         err = hdsp_request_fw_loader(hdsp);
3424                         if (err < 0) {
3425                                 snd_iprintf(buffer,
3426                                             "No firmware loaded nor cached, "
3427                                             "please upload firmware.\n");
3428                                 return;
3429                         }
3430                 }
3431         }
3432
3433         snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3434         snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3435         snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3436         snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3437         snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3438         snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_work ? "on" : "off");
3439
3440         snd_iprintf(buffer, "\n");
3441
3442         x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3443
3444         snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3445         snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3446         snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3447         snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3448
3449         snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3450
3451         snd_iprintf(buffer, "\n");
3452
3453         switch (hdsp_clock_source(hdsp)) {
3454         case HDSP_CLOCK_SOURCE_AUTOSYNC:
3455                 clock_source = "AutoSync";
3456                 break;
3457         case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3458                 clock_source = "Internal 32 kHz";
3459                 break;
3460         case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3461                 clock_source = "Internal 44.1 kHz";
3462                 break;
3463         case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3464                 clock_source = "Internal 48 kHz";
3465                 break;
3466         case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3467                 clock_source = "Internal 64 kHz";
3468                 break;
3469         case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3470                 clock_source = "Internal 88.2 kHz";
3471                 break;
3472         case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3473                 clock_source = "Internal 96 kHz";
3474                 break;
3475         case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3476                 clock_source = "Internal 128 kHz";
3477                 break;
3478         case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3479                 clock_source = "Internal 176.4 kHz";
3480                 break;
3481                 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3482                 clock_source = "Internal 192 kHz";
3483                 break;
3484         default:
3485                 clock_source = "Error";
3486         }
3487         snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3488
3489         if (hdsp_system_clock_mode(hdsp))
3490                 system_clock_mode = "Slave";
3491         else
3492                 system_clock_mode = "Master";
3493
3494         switch (hdsp_pref_sync_ref (hdsp)) {
3495         case HDSP_SYNC_FROM_WORD:
3496                 pref_sync_ref = "Word Clock";
3497                 break;
3498         case HDSP_SYNC_FROM_ADAT_SYNC:
3499                 pref_sync_ref = "ADAT Sync";
3500                 break;
3501         case HDSP_SYNC_FROM_SPDIF:
3502                 pref_sync_ref = "SPDIF";
3503                 break;
3504         case HDSP_SYNC_FROM_ADAT1:
3505                 pref_sync_ref = "ADAT1";
3506                 break;
3507         case HDSP_SYNC_FROM_ADAT2:
3508                 pref_sync_ref = "ADAT2";
3509                 break;
3510         case HDSP_SYNC_FROM_ADAT3:
3511                 pref_sync_ref = "ADAT3";
3512                 break;
3513         default:
3514                 pref_sync_ref = "Word Clock";
3515                 break;
3516         }
3517         snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3518
3519         switch (hdsp_autosync_ref (hdsp)) {
3520         case HDSP_AUTOSYNC_FROM_WORD:
3521                 autosync_ref = "Word Clock";
3522                 break;
3523         case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3524                 autosync_ref = "ADAT Sync";
3525                 break;
3526         case HDSP_AUTOSYNC_FROM_SPDIF:
3527                 autosync_ref = "SPDIF";
3528                 break;
3529         case HDSP_AUTOSYNC_FROM_NONE:
3530                 autosync_ref = "None";
3531                 break;
3532         case HDSP_AUTOSYNC_FROM_ADAT1:
3533                 autosync_ref = "ADAT1";
3534                 break;
3535         case HDSP_AUTOSYNC_FROM_ADAT2:
3536                 autosync_ref = "ADAT2";
3537                 break;
3538         case HDSP_AUTOSYNC_FROM_ADAT3:
3539                 autosync_ref = "ADAT3";
3540                 break;
3541         default:
3542                 autosync_ref = "---";
3543                 break;
3544         }
3545         snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3546
3547         snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3548
3549         snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3550
3551         snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3552         snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3553
3554         snd_iprintf(buffer, "\n");
3555
3556         if (hdsp->io_type != RPM) {
3557                 switch (hdsp_spdif_in(hdsp)) {
3558                 case HDSP_SPDIFIN_OPTICAL:
3559                         snd_iprintf(buffer, "IEC958 input: Optical\n");
3560                         break;
3561                 case HDSP_SPDIFIN_COAXIAL:
3562                         snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3563                         break;
3564                 case HDSP_SPDIFIN_INTERNAL:
3565                         snd_iprintf(buffer, "IEC958 input: Internal\n");
3566                         break;
3567                 case HDSP_SPDIFIN_AES:
3568                         snd_iprintf(buffer, "IEC958 input: AES\n");
3569                         break;
3570                 default:
3571                         snd_iprintf(buffer, "IEC958 input: ???\n");
3572                         break;
3573                 }
3574         }
3575
3576         if (RPM == hdsp->io_type) {
3577                 if (hdsp->control_register & HDSP_RPM_Bypass)
3578                         snd_iprintf(buffer, "RPM Bypass: disabled\n");
3579                 else
3580                         snd_iprintf(buffer, "RPM Bypass: enabled\n");
3581                 if (hdsp->control_register & HDSP_RPM_Disconnect)
3582                         snd_iprintf(buffer, "RPM disconnected\n");
3583                 else
3584                         snd_iprintf(buffer, "RPM connected\n");
3585
3586                 switch (hdsp->control_register & HDSP_RPM_Inp12) {
3587                 case HDSP_RPM_Inp12_Phon_6dB:
3588                         snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n");
3589                         break;
3590                 case HDSP_RPM_Inp12_Phon_0dB:
3591                         snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n");
3592                         break;
3593                 case HDSP_RPM_Inp12_Phon_n6dB:
3594                         snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n");
3595                         break;
3596                 case HDSP_RPM_Inp12_Line_0dB:
3597                         snd_iprintf(buffer, "Input 1/2: Line, 0dB\n");
3598                         break;
3599                 case HDSP_RPM_Inp12_Line_n6dB:
3600                         snd_iprintf(buffer, "Input 1/2: Line, -6dB\n");
3601                         break;
3602                 default:
3603                         snd_iprintf(buffer, "Input 1/2: ???\n");
3604                 }
3605
3606                 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3607                 case HDSP_RPM_Inp34_Phon_6dB:
3608                         snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n");
3609                         break;
3610                 case HDSP_RPM_Inp34_Phon_0dB:
3611                         snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n");
3612                         break;
3613                 case HDSP_RPM_Inp34_Phon_n6dB:
3614                         snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n");
3615                         break;
3616                 case HDSP_RPM_Inp34_Line_0dB:
3617                         snd_iprintf(buffer, "Input 3/4: Line, 0dB\n");
3618                         break;
3619                 case HDSP_RPM_Inp34_Line_n6dB:
3620                         snd_iprintf(buffer, "Input 3/4: Line, -6dB\n");
3621                         break;
3622                 default:
3623                         snd_iprintf(buffer, "Input 3/4: ???\n");
3624                 }
3625
3626         } else {
3627                 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3628                         snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3629                 else
3630                         snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3631
3632                 if (hdsp->control_register & HDSP_SPDIFProfessional)
3633                         snd_iprintf(buffer, "IEC958 quality: Professional\n");
3634                 else
3635                         snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3636
3637                 if (hdsp->control_register & HDSP_SPDIFEmphasis)
3638                         snd_iprintf(buffer, "IEC958 emphasis: on\n");
3639                 else
3640                         snd_iprintf(buffer, "IEC958 emphasis: off\n");
3641
3642                 if (hdsp->control_register & HDSP_SPDIFNonAudio)
3643                         snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3644                 else
3645                         snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3646                 x = hdsp_spdif_sample_rate(hdsp);
3647                 if (x != 0)
3648                         snd_iprintf(buffer, "IEC958 sample rate: %d\n", x);
3649                 else
3650                         snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n");
3651         }
3652         snd_iprintf(buffer, "\n");
3653
3654         /* Sync Check */
3655         x = status & HDSP_Sync0;
3656         if (status & HDSP_Lock0)
3657                 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3658         else
3659                 snd_iprintf(buffer, "ADAT1: No Lock\n");
3660
3661         switch (hdsp->io_type) {
3662         case Digiface:
3663         case H9652:
3664                 x = status & HDSP_Sync1;
3665                 if (status & HDSP_Lock1)
3666                         snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3667                 else
3668                         snd_iprintf(buffer, "ADAT2: No Lock\n");
3669                 x = status & HDSP_Sync2;
3670                 if (status & HDSP_Lock2)
3671                         snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3672                 else
3673                         snd_iprintf(buffer, "ADAT3: No Lock\n");
3674                 break;
3675         default:
3676                 /* relax */
3677                 break;
3678         }
3679
3680         x = status & HDSP_SPDIFSync;
3681         if (status & HDSP_SPDIFErrorFlag)
3682                 snd_iprintf (buffer, "SPDIF: No Lock\n");
3683         else
3684                 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3685
3686         x = status2 & HDSP_wc_sync;
3687         if (status2 & HDSP_wc_lock)
3688                 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3689         else
3690                 snd_iprintf (buffer, "Word Clock: No Lock\n");
3691
3692         x = status & HDSP_TimecodeSync;
3693         if (status & HDSP_TimecodeLock)
3694                 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3695         else
3696                 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3697
3698         snd_iprintf(buffer, "\n");
3699
3700         /* Informations about H9632 specific controls */
3701         if (hdsp->io_type == H9632) {
3702                 char *tmp;
3703
3704                 switch (hdsp_ad_gain(hdsp)) {
3705                 case 0:
3706                         tmp = "-10 dBV";
3707                         break;
3708                 case 1:
3709                         tmp = "+4 dBu";
3710                         break;
3711                 default:
3712                         tmp = "Lo Gain";
3713                         break;
3714                 }
3715                 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3716
3717                 switch (hdsp_da_gain(hdsp)) {
3718                 case 0:
3719                         tmp = "Hi Gain";
3720                         break;
3721                 case 1:
3722                         tmp = "+4 dBu";
3723                         break;
3724                 default:
3725                         tmp = "-10 dBV";
3726                         break;
3727                 }
3728                 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3729
3730                 switch (hdsp_phone_gain(hdsp)) {
3731                 case 0:
3732                         tmp = "0 dB";
3733                         break;
3734                 case 1:
3735                         tmp = "-6 dB";
3736                         break;
3737                 default:
3738                         tmp = "-12 dB";
3739                         break;
3740                 }
3741                 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3742
3743                 snd_iprintf(buffer, "XLR Breakout Cable : %s\n",
3744                         hdsp_toggle_setting(hdsp, HDSP_XLRBreakoutCable) ?
3745                         "yes" : "no");
3746
3747                 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3748                         snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3749                 else
3750                         snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3751                 snd_iprintf(buffer, "\n");
3752         }
3753
3754 }
3755
3756 static void snd_hdsp_proc_init(struct hdsp *hdsp)
3757 {
3758         snd_card_ro_proc_new(hdsp->card, "hdsp", hdsp, snd_hdsp_proc_read);
3759 }
3760
3761 static void snd_hdsp_free_buffers(struct hdsp *hdsp)
3762 {
3763         snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3764         snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3765 }
3766
3767 static int snd_hdsp_initialize_memory(struct hdsp *hdsp)
3768 {
3769         unsigned long pb_bus, cb_bus;
3770
3771         if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3772             snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3773                 if (hdsp->capture_dma_buf.area)
3774                         snd_dma_free_pages(&hdsp->capture_dma_buf);
3775                 dev_err(hdsp->card->dev,
3776                         "%s: no buffers available\n", hdsp->card_name);
3777                 return -ENOMEM;
3778         }
3779
3780         /* Align to bus-space 64K boundary */
3781
3782         cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul);
3783         pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul);
3784
3785         /* Tell the card where it is */
3786
3787         hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3788         hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3789
3790         hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3791         hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3792
3793         return 0;
3794 }
3795
3796 static int snd_hdsp_set_defaults(struct hdsp *hdsp)
3797 {
3798         unsigned int i;
3799
3800         /* ASSUMPTION: hdsp->lock is either held, or
3801            there is no need to hold it (e.g. during module
3802            initialization).
3803          */
3804
3805         /* set defaults:
3806
3807            SPDIF Input via Coax
3808            Master clock mode
3809            maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3810                             which implies 2 4096 sample, 32Kbyte periods).
3811            Enable line out.
3812          */
3813
3814         hdsp->control_register = HDSP_ClockModeMaster |
3815                                  HDSP_SPDIFInputCoaxial |
3816                                  hdsp_encode_latency(7) |
3817                                  HDSP_LineOut;
3818
3819
3820         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3821
3822 #ifdef SNDRV_BIG_ENDIAN
3823         hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3824 #else
3825         hdsp->control2_register = 0;
3826 #endif
3827         if (hdsp->io_type == H9652)
3828                 snd_hdsp_9652_enable_mixer (hdsp);
3829         else
3830                 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3831
3832         hdsp_reset_hw_pointer(hdsp);
3833         hdsp_compute_period_size(hdsp);
3834
3835         /* silence everything */
3836
3837         for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
3838                 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3839
3840         for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3841                 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
3842                         return -EIO;
3843         }
3844
3845         /* H9632 specific defaults */
3846         if (hdsp->io_type == H9632) {
3847                 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3848                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3849         }
3850
3851         /* set a default rate so that the channel map is set up.
3852          */
3853
3854         hdsp_set_rate(hdsp, 48000, 1);
3855
3856         return 0;
3857 }
3858
3859 static void hdsp_midi_work(struct work_struct *work)
3860 {
3861         struct hdsp *hdsp = container_of(work, struct hdsp, midi_work);
3862
3863         if (hdsp->midi[0].pending)
3864                 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3865         if (hdsp->midi[1].pending)
3866                 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3867 }
3868
3869 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
3870 {
3871         struct hdsp *hdsp = (struct hdsp *) dev_id;
3872         unsigned int status;
3873         int audio;
3874         int midi0;
3875         int midi1;
3876         unsigned int midi0status;
3877         unsigned int midi1status;
3878         int schedule = 0;
3879
3880         status = hdsp_read(hdsp, HDSP_statusRegister);
3881
3882         audio = status & HDSP_audioIRQPending;
3883         midi0 = status & HDSP_midi0IRQPending;
3884         midi1 = status & HDSP_midi1IRQPending;
3885
3886         if (!audio && !midi0 && !midi1)
3887                 return IRQ_NONE;
3888
3889         hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3890
3891         midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3892         midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3893
3894         if (!(hdsp->state & HDSP_InitializationComplete))
3895                 return IRQ_HANDLED;
3896
3897         if (audio) {
3898                 if (hdsp->capture_substream)
3899                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3900
3901                 if (hdsp->playback_substream)
3902                         snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3903         }
3904
3905         if (midi0 && midi0status) {
3906                 if (hdsp->use_midi_work) {
3907                         /* we disable interrupts for this input until processing is done */
3908                         hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3909                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3910                         hdsp->midi[0].pending = 1;
3911                         schedule = 1;
3912                 } else {
3913                         snd_hdsp_midi_input_read (&hdsp->midi[0]);
3914                 }
3915         }
3916         if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) {
3917                 if (hdsp->use_midi_work) {
3918                         /* we disable interrupts for this input until processing is done */
3919                         hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3920                         hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3921                         hdsp->midi[1].pending = 1;
3922                         schedule = 1;
3923                 } else {
3924                         snd_hdsp_midi_input_read (&hdsp->midi[1]);
3925                 }
3926         }
3927         if (hdsp->use_midi_work && schedule)
3928                 queue_work(system_highpri_wq, &hdsp->midi_work);
3929         return IRQ_HANDLED;
3930 }
3931
3932 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
3933 {
3934         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3935         return hdsp_hw_pointer(hdsp);
3936 }
3937
3938 static char *hdsp_channel_buffer_location(struct hdsp *hdsp,
3939                                              int stream,
3940                                              int channel)
3941
3942 {
3943         int mapped_channel;
3944
3945         if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels))
3946                 return NULL;
3947
3948         if ((mapped_channel = hdsp->channel_map[channel]) < 0)
3949                 return NULL;
3950
3951         if (stream == SNDRV_PCM_STREAM_CAPTURE)
3952                 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3953         else
3954                 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3955 }
3956
3957 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream,
3958                                   int channel, unsigned long pos,
3959                                   void __user *src, unsigned long count)
3960 {
3961         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3962         char *channel_buf;
3963
3964         if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3965                 return -EINVAL;
3966
3967         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3968         if (snd_BUG_ON(!channel_buf))
3969                 return -EIO;
3970         if (copy_from_user(channel_buf + pos, src, count))
3971                 return -EFAULT;
3972         return 0;
3973 }
3974
3975 static int snd_hdsp_playback_copy_kernel(struct snd_pcm_substream *substream,
3976                                          int channel, unsigned long pos,
3977                                          void *src, unsigned long count)
3978 {
3979         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3980         char *channel_buf;
3981
3982         channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
3983         if (snd_BUG_ON(!channel_buf))
3984                 return -EIO;
3985         memcpy(channel_buf + pos, src, count);
3986         return 0;
3987 }
3988
3989 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream,
3990                                  int channel, unsigned long pos,
3991                                  void __user *dst, unsigned long count)
3992 {
3993         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3994         char *channel_buf;
3995
3996         if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3997                 return -EINVAL;
3998
3999         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
4000         if (snd_BUG_ON(!channel_buf))
4001                 return -EIO;
4002         if (copy_to_user(dst, channel_buf + pos, count))
4003                 return -EFAULT;
4004         return 0;
4005 }
4006
4007 static int snd_hdsp_capture_copy_kernel(struct snd_pcm_substream *substream,
4008                                         int channel, unsigned long pos,
4009                                         void *dst, unsigned long count)
4010 {
4011         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4012         char *channel_buf;
4013
4014         channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
4015         if (snd_BUG_ON(!channel_buf))
4016                 return -EIO;
4017         memcpy(dst, channel_buf + pos, count);
4018         return 0;
4019 }
4020
4021 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream,
4022                                int channel, unsigned long pos,
4023                                unsigned long count)
4024 {
4025         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4026         char *channel_buf;
4027
4028         channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
4029         if (snd_BUG_ON(!channel_buf))
4030                 return -EIO;
4031         memset(channel_buf + pos, 0, count);
4032         return 0;
4033 }
4034
4035 static int snd_hdsp_reset(struct snd_pcm_substream *substream)
4036 {
4037         struct snd_pcm_runtime *runtime = substream->runtime;
4038         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4039         struct snd_pcm_substream *other;
4040         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4041                 other = hdsp->capture_substream;
4042         else
4043                 other = hdsp->playback_substream;
4044         if (hdsp->running)
4045                 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
4046         else
4047                 runtime->status->hw_ptr = 0;
4048         if (other) {
4049                 struct snd_pcm_substream *s;
4050                 struct snd_pcm_runtime *oruntime = other->runtime;
4051                 snd_pcm_group_for_each_entry(s, substream) {
4052                         if (s == other) {
4053                                 oruntime->status->hw_ptr = runtime->status->hw_ptr;
4054                                 break;
4055                         }
4056                 }
4057         }
4058         return 0;
4059 }
4060
4061 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
4062                                  struct snd_pcm_hw_params *params)
4063 {
4064         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4065         int err;
4066         pid_t this_pid;
4067         pid_t other_pid;
4068
4069         if (hdsp_check_for_iobox (hdsp))
4070                 return -EIO;
4071
4072         if (hdsp_check_for_firmware(hdsp, 1))
4073                 return -EIO;
4074
4075         spin_lock_irq(&hdsp->lock);
4076
4077         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4078                 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
4079                 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
4080                 this_pid = hdsp->playback_pid;
4081                 other_pid = hdsp->capture_pid;
4082         } else {
4083                 this_pid = hdsp->capture_pid;
4084                 other_pid = hdsp->playback_pid;
4085         }
4086
4087         if ((other_pid > 0) && (this_pid != other_pid)) {
4088
4089                 /* The other stream is open, and not by the same
4090                    task as this one. Make sure that the parameters
4091                    that matter are the same.
4092                  */
4093
4094                 if (params_rate(params) != hdsp->system_sample_rate) {
4095                         spin_unlock_irq(&hdsp->lock);
4096                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4097                         return -EBUSY;
4098                 }
4099
4100                 if (params_period_size(params) != hdsp->period_bytes / 4) {
4101                         spin_unlock_irq(&hdsp->lock);
4102                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4103                         return -EBUSY;
4104                 }
4105
4106                 /* We're fine. */
4107
4108                 spin_unlock_irq(&hdsp->lock);
4109                 return 0;
4110
4111         } else {
4112                 spin_unlock_irq(&hdsp->lock);
4113         }
4114
4115         /* how to make sure that the rate matches an externally-set one ?
4116          */
4117
4118         spin_lock_irq(&hdsp->lock);
4119         if (! hdsp->clock_source_locked) {
4120                 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
4121                         spin_unlock_irq(&hdsp->lock);
4122                         _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4123                         return err;
4124                 }
4125         }
4126         spin_unlock_irq(&hdsp->lock);
4127
4128         if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
4129                 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4130                 return err;
4131         }
4132
4133         return 0;
4134 }
4135
4136 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
4137                                     struct snd_pcm_channel_info *info)
4138 {
4139         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4140         unsigned int channel = info->channel;
4141
4142         if (snd_BUG_ON(channel >= hdsp->max_channels))
4143                 return -EINVAL;
4144         channel = array_index_nospec(channel, hdsp->max_channels);
4145
4146         if (hdsp->channel_map[channel] < 0)
4147                 return -EINVAL;
4148
4149         info->offset = hdsp->channel_map[channel] * HDSP_CHANNEL_BUFFER_BYTES;
4150         info->first = 0;
4151         info->step = 32;
4152         return 0;
4153 }
4154
4155 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
4156                              unsigned int cmd, void *arg)
4157 {
4158         switch (cmd) {
4159         case SNDRV_PCM_IOCTL1_RESET:
4160                 return snd_hdsp_reset(substream);
4161         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
4162                 return snd_hdsp_channel_info(substream, arg);
4163         default:
4164                 break;
4165         }
4166
4167         return snd_pcm_lib_ioctl(substream, cmd, arg);
4168 }
4169
4170 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
4171 {
4172         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4173         struct snd_pcm_substream *other;
4174         int running;
4175
4176         if (hdsp_check_for_iobox (hdsp))
4177                 return -EIO;
4178
4179         if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */
4180                 return -EIO;
4181
4182         spin_lock(&hdsp->lock);
4183         running = hdsp->running;
4184         switch (cmd) {
4185         case SNDRV_PCM_TRIGGER_START:
4186                 running |= 1 << substream->stream;
4187                 break;
4188         case SNDRV_PCM_TRIGGER_STOP:
4189                 running &= ~(1 << substream->stream);
4190                 break;
4191         default:
4192                 snd_BUG();
4193                 spin_unlock(&hdsp->lock);
4194                 return -EINVAL;
4195         }
4196         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4197                 other = hdsp->capture_substream;
4198         else
4199                 other = hdsp->playback_substream;
4200
4201         if (other) {
4202                 struct snd_pcm_substream *s;
4203                 snd_pcm_group_for_each_entry(s, substream) {
4204                         if (s == other) {
4205                                 snd_pcm_trigger_done(s, substream);
4206                                 if (cmd == SNDRV_PCM_TRIGGER_START)
4207                                         running |= 1 << s->stream;
4208                                 else
4209                                         running &= ~(1 << s->stream);
4210                                 goto _ok;
4211                         }
4212                 }
4213                 if (cmd == SNDRV_PCM_TRIGGER_START) {
4214                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4215                             substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4216                                 hdsp_silence_playback(hdsp);
4217                 } else {
4218                         if (running &&
4219                             substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4220                                 hdsp_silence_playback(hdsp);
4221                 }
4222         } else {
4223                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4224                                 hdsp_silence_playback(hdsp);
4225         }
4226  _ok:
4227         snd_pcm_trigger_done(substream, substream);
4228         if (!hdsp->running && running)
4229                 hdsp_start_audio(hdsp);
4230         else if (hdsp->running && !running)
4231                 hdsp_stop_audio(hdsp);
4232         hdsp->running = running;
4233         spin_unlock(&hdsp->lock);
4234
4235         return 0;
4236 }
4237
4238 static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
4239 {
4240         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4241         int result = 0;
4242
4243         if (hdsp_check_for_iobox (hdsp))
4244                 return -EIO;
4245
4246         if (hdsp_check_for_firmware(hdsp, 1))
4247                 return -EIO;
4248
4249         spin_lock_irq(&hdsp->lock);
4250         if (!hdsp->running)
4251                 hdsp_reset_hw_pointer(hdsp);
4252         spin_unlock_irq(&hdsp->lock);
4253         return result;
4254 }
4255
4256 static const struct snd_pcm_hardware snd_hdsp_playback_subinfo =
4257 {
4258         .info =                 (SNDRV_PCM_INFO_MMAP |
4259                                  SNDRV_PCM_INFO_MMAP_VALID |
4260                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4261                                  SNDRV_PCM_INFO_SYNC_START |
4262                                  SNDRV_PCM_INFO_DOUBLE),
4263 #ifdef SNDRV_BIG_ENDIAN
4264         .formats =              SNDRV_PCM_FMTBIT_S32_BE,
4265 #else
4266         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4267 #endif
4268         .rates =                (SNDRV_PCM_RATE_32000 |
4269                                  SNDRV_PCM_RATE_44100 |
4270                                  SNDRV_PCM_RATE_48000 |
4271                                  SNDRV_PCM_RATE_64000 |
4272                                  SNDRV_PCM_RATE_88200 |
4273                                  SNDRV_PCM_RATE_96000),
4274         .rate_min =             32000,
4275         .rate_max =             96000,
4276         .channels_min =         6,
4277         .channels_max =         HDSP_MAX_CHANNELS,
4278         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4279         .period_bytes_min =     (64 * 4) * 10,
4280         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4281         .periods_min =          2,
4282         .periods_max =          2,
4283         .fifo_size =            0
4284 };
4285
4286 static const struct snd_pcm_hardware snd_hdsp_capture_subinfo =
4287 {
4288         .info =                 (SNDRV_PCM_INFO_MMAP |
4289                                  SNDRV_PCM_INFO_MMAP_VALID |
4290                                  SNDRV_PCM_INFO_NONINTERLEAVED |
4291                                  SNDRV_PCM_INFO_SYNC_START),
4292 #ifdef SNDRV_BIG_ENDIAN
4293         .formats =              SNDRV_PCM_FMTBIT_S32_BE,
4294 #else
4295         .formats =              SNDRV_PCM_FMTBIT_S32_LE,
4296 #endif
4297         .rates =                (SNDRV_PCM_RATE_32000 |
4298                                  SNDRV_PCM_RATE_44100 |
4299                                  SNDRV_PCM_RATE_48000 |
4300                                  SNDRV_PCM_RATE_64000 |
4301                                  SNDRV_PCM_RATE_88200 |
4302                                  SNDRV_PCM_RATE_96000),
4303         .rate_min =             32000,
4304         .rate_max =             96000,
4305         .channels_min =         5,
4306         .channels_max =         HDSP_MAX_CHANNELS,
4307         .buffer_bytes_max =     HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4308         .period_bytes_min =     (64 * 4) * 10,
4309         .period_bytes_max =     (8192 * 4) * HDSP_MAX_CHANNELS,
4310         .periods_min =          2,
4311         .periods_max =          2,
4312         .fifo_size =            0
4313 };
4314
4315 static const unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4316
4317 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
4318         .count = ARRAY_SIZE(hdsp_period_sizes),
4319         .list = hdsp_period_sizes,
4320         .mask = 0
4321 };
4322
4323 static const unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4324
4325 static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
4326         .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4327         .list = hdsp_9632_sample_rates,
4328         .mask = 0
4329 };
4330
4331 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4332                                         struct snd_pcm_hw_rule *rule)
4333 {
4334         struct hdsp *hdsp = rule->private;
4335         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4336         if (hdsp->io_type == H9632) {
4337                 unsigned int list[3];
4338                 list[0] = hdsp->qs_in_channels;
4339                 list[1] = hdsp->ds_in_channels;
4340                 list[2] = hdsp->ss_in_channels;
4341                 return snd_interval_list(c, 3, list, 0);
4342         } else {
4343                 unsigned int list[2];
4344                 list[0] = hdsp->ds_in_channels;
4345                 list[1] = hdsp->ss_in_channels;
4346                 return snd_interval_list(c, 2, list, 0);
4347         }
4348 }
4349
4350 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4351                                         struct snd_pcm_hw_rule *rule)
4352 {
4353         unsigned int list[3];
4354         struct hdsp *hdsp = rule->private;
4355         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4356         if (hdsp->io_type == H9632) {
4357                 list[0] = hdsp->qs_out_channels;
4358                 list[1] = hdsp->ds_out_channels;
4359                 list[2] = hdsp->ss_out_channels;
4360                 return snd_interval_list(c, 3, list, 0);
4361         } else {
4362                 list[0] = hdsp->ds_out_channels;
4363                 list[1] = hdsp->ss_out_channels;
4364         }
4365         return snd_interval_list(c, 2, list, 0);
4366 }
4367
4368 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4369                                              struct snd_pcm_hw_rule *rule)
4370 {
4371         struct hdsp *hdsp = rule->private;
4372         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4373         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4374         if (r->min > 96000 && hdsp->io_type == H9632) {
4375                 struct snd_interval t = {
4376                         .min = hdsp->qs_in_channels,
4377                         .max = hdsp->qs_in_channels,
4378                         .integer = 1,
4379                 };
4380                 return snd_interval_refine(c, &t);
4381         } else if (r->min > 48000 && r->max <= 96000) {
4382                 struct snd_interval t = {
4383                         .min = hdsp->ds_in_channels,
4384                         .max = hdsp->ds_in_channels,
4385                         .integer = 1,
4386                 };
4387                 return snd_interval_refine(c, &t);
4388         } else if (r->max < 64000) {
4389                 struct snd_interval t = {
4390                         .min = hdsp->ss_in_channels,
4391                         .max = hdsp->ss_in_channels,
4392                         .integer = 1,
4393                 };
4394                 return snd_interval_refine(c, &t);
4395         }
4396         return 0;
4397 }
4398
4399 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4400                                              struct snd_pcm_hw_rule *rule)
4401 {
4402         struct hdsp *hdsp = rule->private;
4403         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4404         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4405         if (r->min > 96000 && hdsp->io_type == H9632) {
4406                 struct snd_interval t = {
4407                         .min = hdsp->qs_out_channels,
4408                         .max = hdsp->qs_out_channels,
4409                         .integer = 1,
4410                 };
4411                 return snd_interval_refine(c, &t);
4412         } else if (r->min > 48000 && r->max <= 96000) {
4413                 struct snd_interval t = {
4414                         .min = hdsp->ds_out_channels,
4415                         .max = hdsp->ds_out_channels,
4416                         .integer = 1,
4417                 };
4418                 return snd_interval_refine(c, &t);
4419         } else if (r->max < 64000) {
4420                 struct snd_interval t = {
4421                         .min = hdsp->ss_out_channels,
4422                         .max = hdsp->ss_out_channels,
4423                         .integer = 1,
4424                 };
4425                 return snd_interval_refine(c, &t);
4426         }
4427         return 0;
4428 }
4429
4430 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4431                                              struct snd_pcm_hw_rule *rule)
4432 {
4433         struct hdsp *hdsp = rule->private;
4434         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4435         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4436         if (c->min >= hdsp->ss_out_channels) {
4437                 struct snd_interval t = {
4438                         .min = 32000,
4439                         .max = 48000,
4440                         .integer = 1,
4441                 };
4442                 return snd_interval_refine(r, &t);
4443         } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4444                 struct snd_interval t = {
4445                         .min = 128000,
4446                         .max = 192000,
4447                         .integer = 1,
4448                 };
4449                 return snd_interval_refine(r, &t);
4450         } else if (c->max <= hdsp->ds_out_channels) {
4451                 struct snd_interval t = {
4452                         .min = 64000,
4453                         .max = 96000,
4454                         .integer = 1,
4455                 };
4456                 return snd_interval_refine(r, &t);
4457         }
4458         return 0;
4459 }
4460
4461 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4462                                              struct snd_pcm_hw_rule *rule)
4463 {
4464         struct hdsp *hdsp = rule->private;
4465         struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4466         struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4467         if (c->min >= hdsp->ss_in_channels) {
4468                 struct snd_interval t = {
4469                         .min = 32000,
4470                         .max = 48000,
4471                         .integer = 1,
4472                 };
4473                 return snd_interval_refine(r, &t);
4474         } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4475                 struct snd_interval t = {
4476                         .min = 128000,
4477                         .max = 192000,
4478                         .integer = 1,
4479                 };
4480                 return snd_interval_refine(r, &t);
4481         } else if (c->max <= hdsp->ds_in_channels) {
4482                 struct snd_interval t = {
4483                         .min = 64000,
4484                         .max = 96000,
4485                         .integer = 1,
4486                 };
4487                 return snd_interval_refine(r, &t);
4488         }
4489         return 0;
4490 }
4491
4492 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
4493 {
4494         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4495         struct snd_pcm_runtime *runtime = substream->runtime;
4496
4497         if (hdsp_check_for_iobox (hdsp))
4498                 return -EIO;
4499
4500         if (hdsp_check_for_firmware(hdsp, 1))
4501                 return -EIO;
4502
4503         spin_lock_irq(&hdsp->lock);
4504
4505         snd_pcm_set_sync(substream);
4506
4507         runtime->hw = snd_hdsp_playback_subinfo;
4508         runtime->dma_area = hdsp->playback_buffer;
4509         runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4510
4511         hdsp->playback_pid = current->pid;
4512         hdsp->playback_substream = substream;
4513
4514         spin_unlock_irq(&hdsp->lock);
4515
4516         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4517         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4518         if (hdsp->clock_source_locked) {
4519                 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4520         } else if (hdsp->io_type == H9632) {
4521                 runtime->hw.rate_max = 192000;
4522                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4523                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4524         }
4525         if (hdsp->io_type == H9632) {
4526                 runtime->hw.channels_min = hdsp->qs_out_channels;
4527                 runtime->hw.channels_max = hdsp->ss_out_channels;
4528         }
4529
4530         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4531                              snd_hdsp_hw_rule_out_channels, hdsp,
4532                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4533         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4534                              snd_hdsp_hw_rule_out_channels_rate, hdsp,
4535                              SNDRV_PCM_HW_PARAM_RATE, -1);
4536         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4537                              snd_hdsp_hw_rule_rate_out_channels, hdsp,
4538                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4539
4540         if (RPM != hdsp->io_type) {
4541                 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4542                 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4543                 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4544                         SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4545         }
4546         return 0;
4547 }
4548
4549 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
4550 {
4551         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4552
4553         spin_lock_irq(&hdsp->lock);
4554
4555         hdsp->playback_pid = -1;
4556         hdsp->playback_substream = NULL;
4557
4558         spin_unlock_irq(&hdsp->lock);
4559
4560         if (RPM != hdsp->io_type) {
4561                 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4562                 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4563                         SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4564         }
4565         return 0;
4566 }
4567
4568
4569 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
4570 {
4571         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4572         struct snd_pcm_runtime *runtime = substream->runtime;
4573
4574         if (hdsp_check_for_iobox (hdsp))
4575                 return -EIO;
4576
4577         if (hdsp_check_for_firmware(hdsp, 1))
4578                 return -EIO;
4579
4580         spin_lock_irq(&hdsp->lock);
4581
4582         snd_pcm_set_sync(substream);
4583
4584         runtime->hw = snd_hdsp_capture_subinfo;
4585         runtime->dma_area = hdsp->capture_buffer;
4586         runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4587
4588         hdsp->capture_pid = current->pid;
4589         hdsp->capture_substream = substream;
4590
4591         spin_unlock_irq(&hdsp->lock);
4592
4593         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4594         snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4595         if (hdsp->io_type == H9632) {
4596                 runtime->hw.channels_min = hdsp->qs_in_channels;
4597                 runtime->hw.channels_max = hdsp->ss_in_channels;
4598                 runtime->hw.rate_max = 192000;
4599                 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4600                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4601         }
4602         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4603                              snd_hdsp_hw_rule_in_channels, hdsp,
4604                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4605         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4606                              snd_hdsp_hw_rule_in_channels_rate, hdsp,
4607                              SNDRV_PCM_HW_PARAM_RATE, -1);
4608         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4609                              snd_hdsp_hw_rule_rate_in_channels, hdsp,
4610                              SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4611         return 0;
4612 }
4613
4614 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
4615 {
4616         struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4617
4618         spin_lock_irq(&hdsp->lock);
4619
4620         hdsp->capture_pid = -1;
4621         hdsp->capture_substream = NULL;
4622
4623         spin_unlock_irq(&hdsp->lock);
4624         return 0;
4625 }
4626
4627 /* helper functions for copying meter values */
4628 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4629 {
4630         u32 val = readl(src);
4631         return copy_to_user(dest, &val, 4);
4632 }
4633
4634 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4635 {
4636         u32 rms_low, rms_high;
4637         u64 rms;
4638         rms_low = readl(src_low);
4639         rms_high = readl(src_high);
4640         rms = ((u64)rms_high << 32) | rms_low;
4641         return copy_to_user(dest, &rms, 8);
4642 }
4643
4644 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4645 {
4646         u32 rms_low, rms_high;
4647         u64 rms;
4648         rms_low = readl(src_low) & 0xffffff00;
4649         rms_high = readl(src_high) & 0xffffff00;
4650         rms = ((u64)rms_high << 32) | rms_low;
4651         return copy_to_user(dest, &rms, 8);
4652 }
4653
4654 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4655 {
4656         int doublespeed = 0;
4657         int i, j, channels, ofs;
4658
4659         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4660                 doublespeed = 1;
4661         channels = doublespeed ? 14 : 26;
4662         for (i = 0, j = 0; i < 26; ++i) {
4663                 if (doublespeed && (i & 4))
4664                         continue;
4665                 ofs = HDSP_9652_peakBase - j * 4;
4666                 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4667                         return -EFAULT;
4668                 ofs -= channels * 4;
4669                 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4670                         return -EFAULT;
4671                 ofs -= channels * 4;
4672                 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4673                         return -EFAULT;
4674                 ofs = HDSP_9652_rmsBase + j * 8;
4675                 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4676                                 hdsp->iobase + ofs + 4))
4677                         return -EFAULT;
4678                 ofs += channels * 8;
4679                 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4680                                 hdsp->iobase + ofs + 4))
4681                         return -EFAULT;
4682                 ofs += channels * 8;
4683                 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4684                                 hdsp->iobase + ofs + 4))
4685                         return -EFAULT;
4686                 j++;
4687         }
4688         return 0;
4689 }
4690
4691 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4692 {
4693         int i, j;
4694         struct hdsp_9632_meters __iomem *m;
4695         int doublespeed = 0;
4696
4697         if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4698                 doublespeed = 1;
4699         m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4700         for (i = 0, j = 0; i < 16; ++i, ++j) {
4701                 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4702                         return -EFAULT;
4703                 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4704                         return -EFAULT;
4705                 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4706                         return -EFAULT;
4707                 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4708                                 &m->input_rms_high[j]))
4709                         return -EFAULT;
4710                 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4711                                 &m->playback_rms_high[j]))
4712                         return -EFAULT;
4713                 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4714                                 &m->output_rms_high[j]))
4715                         return -EFAULT;
4716                 if (doublespeed && i == 3) i += 4;
4717         }
4718         return 0;
4719 }
4720
4721 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4722 {
4723         int i;
4724
4725         for (i = 0; i < 26; i++) {
4726                 if (copy_u32_le(&peak_rms->playback_peaks[i],
4727                                 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4728                         return -EFAULT;
4729                 if (copy_u32_le(&peak_rms->input_peaks[i],
4730                                 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4731                         return -EFAULT;
4732         }
4733         for (i = 0; i < 28; i++) {
4734                 if (copy_u32_le(&peak_rms->output_peaks[i],
4735                                 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4736                         return -EFAULT;
4737         }
4738         for (i = 0; i < 26; ++i) {
4739                 if (copy_u64_le(&peak_rms->playback_rms[i],
4740                                 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4741                                 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4742                         return -EFAULT;
4743                 if (copy_u64_le(&peak_rms->input_rms[i],
4744                                 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4745                                 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4746                         return -EFAULT;
4747         }
4748         return 0;
4749 }
4750
4751 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
4752 {
4753         struct hdsp *hdsp = hw->private_data;
4754         void __user *argp = (void __user *)arg;
4755         int err;
4756
4757         switch (cmd) {
4758         case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4759                 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
4760
4761                 err = hdsp_check_for_iobox(hdsp);
4762                 if (err < 0)
4763                         return err;
4764
4765                 err = hdsp_check_for_firmware(hdsp, 1);
4766                 if (err < 0)
4767                         return err;
4768
4769                 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4770                         dev_err(hdsp->card->dev,
4771                                 "firmware needs to be uploaded to the card.\n");
4772                         return -EINVAL;
4773                 }
4774
4775                 switch (hdsp->io_type) {
4776                 case H9652:
4777                         return hdsp_9652_get_peak(hdsp, peak_rms);
4778                 case H9632:
4779                         return hdsp_9632_get_peak(hdsp, peak_rms);
4780                 default:
4781                         return hdsp_get_peak(hdsp, peak_rms);
4782                 }
4783         }
4784         case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4785                 struct hdsp_config_info info;
4786                 unsigned long flags;
4787                 int i;
4788
4789                 err = hdsp_check_for_iobox(hdsp);
4790                 if (err < 0)
4791                         return err;
4792
4793                 err = hdsp_check_for_firmware(hdsp, 1);
4794                 if (err < 0)
4795                         return err;
4796
4797                 memset(&info, 0, sizeof(info));
4798                 spin_lock_irqsave(&hdsp->lock, flags);
4799                 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4800                 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4801                 if (hdsp->io_type != H9632)
4802                     info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4803                 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4804                 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632) ? 3 : 1); ++i)
4805                         info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4806                 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4807                 info.spdif_out = (unsigned char)hdsp_toggle_setting(hdsp,
4808                                 HDSP_SPDIFOpticalOut);
4809                 info.spdif_professional = (unsigned char)
4810                         hdsp_toggle_setting(hdsp, HDSP_SPDIFProfessional);
4811                 info.spdif_emphasis = (unsigned char)
4812                         hdsp_toggle_setting(hdsp, HDSP_SPDIFEmphasis);
4813                 info.spdif_nonaudio = (unsigned char)
4814                         hdsp_toggle_setting(hdsp, HDSP_SPDIFNonAudio);
4815                 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4816                 info.system_sample_rate = hdsp->system_sample_rate;
4817                 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4818                 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4819                 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4820                 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4821                 info.line_out = (unsigned char)
4822                         hdsp_toggle_setting(hdsp, HDSP_LineOut);
4823                 if (hdsp->io_type == H9632) {
4824                         info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4825                         info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4826                         info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4827                         info.xlr_breakout_cable =
4828                                 (unsigned char)hdsp_toggle_setting(hdsp,
4829                                         HDSP_XLRBreakoutCable);
4830
4831                 } else if (hdsp->io_type == RPM) {
4832                         info.da_gain = (unsigned char) hdsp_rpm_input12(hdsp);
4833                         info.ad_gain = (unsigned char) hdsp_rpm_input34(hdsp);
4834                 }
4835                 if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
4836                         info.analog_extension_board =
4837                                 (unsigned char)hdsp_toggle_setting(hdsp,
4838                                             HDSP_AnalogExtensionBoard);
4839                 spin_unlock_irqrestore(&hdsp->lock, flags);
4840                 if (copy_to_user(argp, &info, sizeof(info)))
4841                         return -EFAULT;
4842                 break;
4843         }
4844         case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4845                 struct hdsp_9632_aeb h9632_aeb;
4846
4847                 if (hdsp->io_type != H9632) return -EINVAL;
4848                 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4849                 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4850                 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4851                         return -EFAULT;
4852                 break;
4853         }
4854         case SNDRV_HDSP_IOCTL_GET_VERSION: {
4855                 struct hdsp_version hdsp_version;
4856                 int err;
4857
4858                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4859                 if (hdsp->io_type == Undefined) {
4860                         if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4861                                 return err;
4862                 }
4863                 memset(&hdsp_version, 0, sizeof(hdsp_version));
4864                 hdsp_version.io_type = hdsp->io_type;
4865                 hdsp_version.firmware_rev = hdsp->firmware_rev;
4866                 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version))))
4867                         return -EFAULT;
4868                 break;
4869         }
4870         case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4871                 struct hdsp_firmware firmware;
4872                 u32 __user *firmware_data;
4873                 int err;
4874
4875                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4876                 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4877                 if (hdsp->io_type == Undefined) return -EINVAL;
4878
4879                 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4880                         return -EBUSY;
4881
4882                 dev_info(hdsp->card->dev,
4883                          "initializing firmware upload\n");
4884                 if (copy_from_user(&firmware, argp, sizeof(firmware)))
4885                         return -EFAULT;
4886                 firmware_data = (u32 __user *)firmware.firmware_data;
4887
4888                 if (hdsp_check_for_iobox (hdsp))
4889                         return -EIO;
4890
4891                 if (!hdsp->fw_uploaded) {
4892                         hdsp->fw_uploaded = vmalloc(HDSP_FIRMWARE_SIZE);
4893                         if (!hdsp->fw_uploaded)
4894                                 return -ENOMEM;
4895                 }
4896
4897                 if (copy_from_user(hdsp->fw_uploaded, firmware_data,
4898                                    HDSP_FIRMWARE_SIZE)) {
4899                         vfree(hdsp->fw_uploaded);
4900                         hdsp->fw_uploaded = NULL;
4901                         return -EFAULT;
4902                 }
4903
4904                 hdsp->state |= HDSP_FirmwareCached;
4905
4906                 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4907                         return err;
4908
4909                 if (!(hdsp->state & HDSP_InitializationComplete)) {
4910                         if ((err = snd_hdsp_enable_io(hdsp)) < 0)
4911                                 return err;
4912
4913                         snd_hdsp_initialize_channels(hdsp);
4914                         snd_hdsp_initialize_midi_flush(hdsp);
4915
4916                         if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4917                                 dev_err(hdsp->card->dev,
4918                                         "error creating alsa devices\n");
4919                                 return err;
4920                         }
4921                 }
4922                 break;
4923         }
4924         case SNDRV_HDSP_IOCTL_GET_MIXER: {
4925                 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
4926                 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4927                         return -EFAULT;
4928                 break;
4929         }
4930         default:
4931                 return -EINVAL;
4932         }
4933         return 0;
4934 }
4935
4936 static const struct snd_pcm_ops snd_hdsp_playback_ops = {
4937         .open =         snd_hdsp_playback_open,
4938         .close =        snd_hdsp_playback_release,
4939         .ioctl =        snd_hdsp_ioctl,
4940         .hw_params =    snd_hdsp_hw_params,
4941         .prepare =      snd_hdsp_prepare,
4942         .trigger =      snd_hdsp_trigger,
4943         .pointer =      snd_hdsp_hw_pointer,
4944         .copy_user =    snd_hdsp_playback_copy,
4945         .copy_kernel =  snd_hdsp_playback_copy_kernel,
4946         .fill_silence = snd_hdsp_hw_silence,
4947 };
4948
4949 static const struct snd_pcm_ops snd_hdsp_capture_ops = {
4950         .open =         snd_hdsp_capture_open,
4951         .close =        snd_hdsp_capture_release,
4952         .ioctl =        snd_hdsp_ioctl,
4953         .hw_params =    snd_hdsp_hw_params,
4954         .prepare =      snd_hdsp_prepare,
4955         .trigger =      snd_hdsp_trigger,
4956         .pointer =      snd_hdsp_hw_pointer,
4957         .copy_user =    snd_hdsp_capture_copy,
4958         .copy_kernel =  snd_hdsp_capture_copy_kernel,
4959 };
4960
4961 static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp)
4962 {
4963         struct snd_hwdep *hw;
4964         int err;
4965
4966         if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4967                 return err;
4968
4969         hdsp->hwdep = hw;
4970         hw->private_data = hdsp;
4971         strcpy(hw->name, "HDSP hwdep interface");
4972
4973         hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4974         hw->ops.ioctl_compat = snd_hdsp_hwdep_ioctl;
4975
4976         return 0;
4977 }
4978
4979 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
4980 {
4981         struct snd_pcm *pcm;
4982         int err;
4983
4984         if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4985                 return err;
4986
4987         hdsp->pcm = pcm;
4988         pcm->private_data = hdsp;
4989         strcpy(pcm->name, hdsp->card_name);
4990
4991         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4992         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4993
4994         pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4995
4996         return 0;
4997 }
4998
4999 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
5000 {
5001         hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
5002         hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
5003 }
5004
5005 static int snd_hdsp_enable_io (struct hdsp *hdsp)
5006 {
5007         int i;
5008
5009         if (hdsp_fifo_wait (hdsp, 0, 100)) {
5010                 dev_err(hdsp->card->dev,
5011                         "enable_io fifo_wait failed\n");
5012                 return -EIO;
5013         }
5014
5015         for (i = 0; i < hdsp->max_channels; ++i) {
5016                 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
5017                 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
5018         }
5019
5020         return 0;
5021 }
5022
5023 static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
5024 {
5025         int status, aebi_channels, aebo_channels, i;
5026
5027         switch (hdsp->io_type) {
5028         case Digiface:
5029                 hdsp->card_name = "RME Hammerfall DSP + Digiface";
5030                 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
5031                 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
5032                 break;
5033
5034         case H9652:
5035                 hdsp->card_name = "RME Hammerfall HDSP 9652";
5036                 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
5037                 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
5038                 break;
5039
5040         case H9632:
5041                 status = hdsp_read(hdsp, HDSP_statusRegister);
5042                 /* HDSP_AEBx bits are low when AEB are connected */
5043                 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
5044                 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
5045                 hdsp->card_name = "RME Hammerfall HDSP 9632";
5046                 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
5047                 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
5048                 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
5049                 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
5050                 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
5051                 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
5052                 /* Disable loopback of output channels, as the set function
5053                  * only sets on a change we fake all bits (channels) as enabled.
5054                  */
5055                 hdsp->io_loopback = 0xffffffff;
5056                 for (i = 0; i < hdsp->max_channels; ++i)
5057                         hdsp_loopback_set(hdsp, i, false);
5058                 break;
5059
5060         case Multiface:
5061                 hdsp->card_name = "RME Hammerfall DSP + Multiface";
5062                 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
5063                 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
5064                 break;
5065
5066         case RPM:
5067                 hdsp->card_name = "RME Hammerfall DSP + RPM";
5068                 hdsp->ss_in_channels = RPM_CHANNELS-1;
5069                 hdsp->ss_out_channels = RPM_CHANNELS;
5070                 hdsp->ds_in_channels = RPM_CHANNELS-1;
5071                 hdsp->ds_out_channels = RPM_CHANNELS;
5072                 break;
5073
5074         default:
5075                 /* should never get here */
5076                 break;
5077         }
5078 }
5079
5080 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
5081 {
5082         snd_hdsp_flush_midi_input (hdsp, 0);
5083         snd_hdsp_flush_midi_input (hdsp, 1);
5084 }
5085
5086 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
5087 {
5088         int err;
5089
5090         if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
5091                 dev_err(card->dev,
5092                         "Error creating pcm interface\n");
5093                 return err;
5094         }
5095
5096
5097         if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
5098                 dev_err(card->dev,
5099                         "Error creating first midi interface\n");
5100                 return err;
5101         }
5102
5103         if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
5104                 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
5105                         dev_err(card->dev,
5106                                 "Error creating second midi interface\n");
5107                         return err;
5108                 }
5109         }
5110
5111         if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
5112                 dev_err(card->dev,
5113                         "Error creating ctl interface\n");
5114                 return err;
5115         }
5116
5117         snd_hdsp_proc_init(hdsp);
5118
5119         hdsp->system_sample_rate = -1;
5120         hdsp->playback_pid = -1;
5121         hdsp->capture_pid = -1;
5122         hdsp->capture_substream = NULL;
5123         hdsp->playback_substream = NULL;
5124
5125         if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
5126                 dev_err(card->dev,
5127                         "Error setting default values\n");
5128                 return err;
5129         }
5130
5131         if (!(hdsp->state & HDSP_InitializationComplete)) {
5132                 strcpy(card->shortname, "Hammerfall DSP");
5133                 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5134                         hdsp->port, hdsp->irq);
5135
5136                 if ((err = snd_card_register(card)) < 0) {
5137                         dev_err(card->dev,
5138                                 "error registering card\n");
5139                         return err;
5140                 }
5141                 hdsp->state |= HDSP_InitializationComplete;
5142         }
5143
5144         return 0;
5145 }
5146
5147 /* load firmware via hotplug fw loader */
5148 static int hdsp_request_fw_loader(struct hdsp *hdsp)
5149 {
5150         const char *fwfile;
5151         const struct firmware *fw;
5152         int err;
5153
5154         if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5155                 return 0;
5156         if (hdsp->io_type == Undefined) {
5157                 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
5158                         return err;
5159                 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5160                         return 0;
5161         }
5162
5163         /* caution: max length of firmware filename is 30! */
5164         switch (hdsp->io_type) {
5165         case RPM:
5166                 fwfile = "rpm_firmware.bin";
5167                 break;
5168         case Multiface:
5169                 if (hdsp->firmware_rev == 0xa)
5170                         fwfile = "multiface_firmware.bin";
5171                 else
5172                         fwfile = "multiface_firmware_rev11.bin";
5173                 break;
5174         case Digiface:
5175                 if (hdsp->firmware_rev == 0xa)
5176                         fwfile = "digiface_firmware.bin";
5177                 else
5178                         fwfile = "digiface_firmware_rev11.bin";
5179                 break;
5180         default:
5181                 dev_err(hdsp->card->dev,
5182                         "invalid io_type %d\n", hdsp->io_type);
5183                 return -EINVAL;
5184         }
5185
5186         if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) {
5187                 dev_err(hdsp->card->dev,
5188                         "cannot load firmware %s\n", fwfile);
5189                 return -ENOENT;
5190         }
5191         if (fw->size < HDSP_FIRMWARE_SIZE) {
5192                 dev_err(hdsp->card->dev,
5193                         "too short firmware size %d (expected %d)\n",
5194                            (int)fw->size, HDSP_FIRMWARE_SIZE);
5195                 release_firmware(fw);
5196                 return -EINVAL;
5197         }
5198
5199         hdsp->firmware = fw;
5200
5201         hdsp->state |= HDSP_FirmwareCached;
5202
5203         if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
5204                 return err;
5205
5206         if (!(hdsp->state & HDSP_InitializationComplete)) {
5207                 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
5208                         return err;
5209
5210                 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
5211                         dev_err(hdsp->card->dev,
5212                                 "error creating hwdep device\n");
5213                         return err;
5214                 }
5215                 snd_hdsp_initialize_channels(hdsp);
5216                 snd_hdsp_initialize_midi_flush(hdsp);
5217                 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
5218                         dev_err(hdsp->card->dev,
5219                                 "error creating alsa devices\n");
5220                         return err;
5221                 }
5222         }
5223         return 0;
5224 }
5225
5226 static int snd_hdsp_create(struct snd_card *card,
5227                            struct hdsp *hdsp)
5228 {
5229         struct pci_dev *pci = hdsp->pci;
5230         int err;
5231         int is_9652 = 0;
5232         int is_9632 = 0;
5233
5234         hdsp->irq = -1;
5235         hdsp->state = 0;
5236         hdsp->midi[0].rmidi = NULL;
5237         hdsp->midi[1].rmidi = NULL;
5238         hdsp->midi[0].input = NULL;
5239         hdsp->midi[1].input = NULL;
5240         hdsp->midi[0].output = NULL;
5241         hdsp->midi[1].output = NULL;
5242         hdsp->midi[0].pending = 0;
5243         hdsp->midi[1].pending = 0;
5244         spin_lock_init(&hdsp->midi[0].lock);
5245         spin_lock_init(&hdsp->midi[1].lock);
5246         hdsp->iobase = NULL;
5247         hdsp->control_register = 0;
5248         hdsp->control2_register = 0;
5249         hdsp->io_type = Undefined;
5250         hdsp->max_channels = 26;
5251
5252         hdsp->card = card;
5253
5254         spin_lock_init(&hdsp->lock);
5255
5256         INIT_WORK(&hdsp->midi_work, hdsp_midi_work);
5257
5258         pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5259         hdsp->firmware_rev &= 0xff;
5260
5261         /* From Martin Bjoernsen :
5262             "It is important that the card's latency timer register in
5263             the PCI configuration space is set to a value much larger
5264             than 0 by the computer's BIOS or the driver.
5265             The windows driver always sets this 8 bit register [...]
5266             to its maximum 255 to avoid problems with some computers."
5267         */
5268         pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5269
5270         strcpy(card->driver, "H-DSP");
5271         strcpy(card->mixername, "Xilinx FPGA");
5272
5273         if (hdsp->firmware_rev < 0xa)
5274                 return -ENODEV;
5275         else if (hdsp->firmware_rev < 0x64)
5276                 hdsp->card_name = "RME Hammerfall DSP";
5277         else if (hdsp->firmware_rev < 0x96) {
5278                 hdsp->card_name = "RME HDSP 9652";
5279                 is_9652 = 1;
5280         } else {
5281                 hdsp->card_name = "RME HDSP 9632";
5282                 hdsp->max_channels = 16;
5283                 is_9632 = 1;
5284         }
5285
5286         if ((err = pci_enable_device(pci)) < 0)
5287                 return err;
5288
5289         pci_set_master(hdsp->pci);
5290
5291         if ((err = pci_request_regions(pci, "hdsp")) < 0)
5292                 return err;
5293         hdsp->port = pci_resource_start(pci, 0);
5294         if ((hdsp->iobase = ioremap(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
5295                 dev_err(hdsp->card->dev, "unable to remap region 0x%lx-0x%lx\n",
5296                         hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5297                 return -EBUSY;
5298         }
5299
5300         if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED,
5301                         KBUILD_MODNAME, hdsp)) {
5302                 dev_err(hdsp->card->dev, "unable to use IRQ %d\n", pci->irq);
5303                 return -EBUSY;
5304         }
5305
5306         hdsp->irq = pci->irq;
5307         card->sync_irq = hdsp->irq;
5308         hdsp->precise_ptr = 0;
5309         hdsp->use_midi_work = 1;
5310         hdsp->dds_value = 0;
5311
5312         if ((err = snd_hdsp_initialize_memory(hdsp)) < 0)
5313                 return err;
5314
5315         if (!is_9652 && !is_9632) {
5316                 /* we wait a maximum of 10 seconds to let freshly
5317                  * inserted cardbus cards do their hardware init */
5318                 err = hdsp_wait_for_iobox(hdsp, 1000, 10);
5319
5320                 if (err < 0)
5321                         return err;
5322
5323                 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5324                         if ((err = hdsp_request_fw_loader(hdsp)) < 0)
5325                                 /* we don't fail as this can happen
5326                                    if userspace is not ready for
5327                                    firmware upload
5328                                 */
5329                                 dev_err(hdsp->card->dev,
5330                                         "couldn't get firmware from userspace. try using hdsploader\n");
5331                         else
5332                                 /* init is complete, we return */
5333                                 return 0;
5334                         /* we defer initialization */
5335                         dev_info(hdsp->card->dev,
5336                                  "card initialization pending : waiting for firmware\n");
5337                         if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5338                                 return err;
5339                         return 0;
5340                 } else {
5341                         dev_info(hdsp->card->dev,
5342                                  "Firmware already present, initializing card.\n");
5343                         if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
5344                                 hdsp->io_type = RPM;
5345                         else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
5346                                 hdsp->io_type = Multiface;
5347                         else
5348                                 hdsp->io_type = Digiface;
5349                 }
5350         }
5351
5352         if ((err = snd_hdsp_enable_io(hdsp)) != 0)
5353                 return err;
5354
5355         if (is_9652)
5356                 hdsp->io_type = H9652;
5357
5358         if (is_9632)
5359                 hdsp->io_type = H9632;
5360
5361         if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5362                 return err;
5363
5364         snd_hdsp_initialize_channels(hdsp);
5365         snd_hdsp_initialize_midi_flush(hdsp);
5366
5367         hdsp->state |= HDSP_FirmwareLoaded;
5368
5369         if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0)
5370                 return err;
5371
5372         return 0;
5373 }
5374
5375 static int snd_hdsp_free(struct hdsp *hdsp)
5376 {
5377         if (hdsp->port) {
5378                 /* stop the audio, and cancel all interrupts */
5379                 cancel_work_sync(&hdsp->midi_work);
5380                 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5381                 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5382         }
5383
5384         if (hdsp->irq >= 0)
5385                 free_irq(hdsp->irq, (void *)hdsp);
5386
5387         snd_hdsp_free_buffers(hdsp);
5388
5389         release_firmware(hdsp->firmware);
5390         vfree(hdsp->fw_uploaded);
5391         iounmap(hdsp->iobase);
5392
5393         if (hdsp->port)
5394                 pci_release_regions(hdsp->pci);
5395
5396         pci_disable_device(hdsp->pci);
5397         return 0;
5398 }
5399
5400 static void snd_hdsp_card_free(struct snd_card *card)
5401 {
5402         struct hdsp *hdsp = card->private_data;
5403
5404         if (hdsp)
5405                 snd_hdsp_free(hdsp);
5406 }
5407
5408 static int snd_hdsp_probe(struct pci_dev *pci,
5409                           const struct pci_device_id *pci_id)
5410 {
5411         static int dev;
5412         struct hdsp *hdsp;
5413         struct snd_card *card;
5414         int err;
5415
5416         if (dev >= SNDRV_CARDS)
5417                 return -ENODEV;
5418         if (!enable[dev]) {
5419                 dev++;
5420                 return -ENOENT;
5421         }
5422
5423         err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
5424                            sizeof(struct hdsp), &card);
5425         if (err < 0)
5426                 return err;
5427
5428         hdsp = card->private_data;
5429         card->private_free = snd_hdsp_card_free;
5430         hdsp->dev = dev;
5431         hdsp->pci = pci;
5432         err = snd_hdsp_create(card, hdsp);
5433         if (err)
5434                 goto free_card;
5435
5436         strcpy(card->shortname, "Hammerfall DSP");
5437         sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5438                 hdsp->port, hdsp->irq);
5439         err = snd_card_register(card);
5440         if (err) {
5441 free_card:
5442                 snd_card_free(card);
5443                 return err;
5444         }
5445         pci_set_drvdata(pci, card);
5446         dev++;
5447         return 0;
5448 }
5449
5450 static void snd_hdsp_remove(struct pci_dev *pci)
5451 {
5452         snd_card_free(pci_get_drvdata(pci));
5453 }
5454
5455 static struct pci_driver hdsp_driver = {
5456         .name =     KBUILD_MODNAME,
5457         .id_table = snd_hdsp_ids,
5458         .probe =    snd_hdsp_probe,
5459         .remove = snd_hdsp_remove,
5460 };
5461
5462 module_pci_driver(hdsp_driver);