3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
12 * Wu Fengguang <wfg@linux.intel.com>
15 * Wu Fengguang <wfg@linux.intel.com>
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/slab.h>
35 #include <linux/module.h>
36 #include <linux/pm_runtime.h>
37 #include <sound/core.h>
38 #include <sound/jack.h>
39 #include <sound/asoundef.h>
40 #include <sound/tlv.h>
41 #include <sound/hdaudio.h>
42 #include <sound/hda_i915.h>
43 #include <sound/hda_chmap.h>
44 #include "hda_codec.h"
45 #include "hda_local.h"
48 static bool static_hdmi_pcm;
49 module_param(static_hdmi_pcm, bool, 0644);
50 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
52 #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
53 #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
54 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
55 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
56 #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
57 #define is_geminilake(codec) (((codec)->core.vendor_id == 0x8086280d) || \
58 ((codec)->core.vendor_id == 0x80862800))
59 #define is_cannonlake(codec) ((codec)->core.vendor_id == 0x8086280c)
60 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
61 || is_skylake(codec) || is_broxton(codec) \
62 || is_kabylake(codec)) || is_geminilake(codec) \
63 || is_cannonlake(codec)
64 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
65 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
66 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
68 struct hdmi_spec_per_cvt {
71 unsigned int channels_min;
72 unsigned int channels_max;
78 /* max. connections to a widget */
79 #define HDA_MAX_CONNECTIONS 32
81 struct hdmi_spec_per_pin {
84 /* pin idx, different device entries on the same pin use the same idx */
87 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
91 struct hda_codec *codec;
92 struct hdmi_eld sink_eld;
94 struct delayed_work work;
95 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
96 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
98 bool setup; /* the stream has been set up by prepare callback */
99 int channels; /* current number of channels */
101 bool chmap_set; /* channel-map override by ALSA API? */
102 unsigned char chmap[8]; /* ALSA API channel-map */
103 #ifdef CONFIG_SND_PROC_FS
104 struct snd_info_entry *proc_entry;
108 /* operations used by generic code that can be overridden by patches */
110 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
111 unsigned char *buf, int *eld_size);
113 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
114 int ca, int active_channels, int conn_type);
116 /* enable/disable HBR (HD passthrough) */
117 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
119 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
120 hda_nid_t pin_nid, u32 stream_tag, int format);
122 void (*pin_cvt_fixup)(struct hda_codec *codec,
123 struct hdmi_spec_per_pin *per_pin,
129 struct snd_jack *jack;
130 struct snd_kcontrol *eld_ctl;
135 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
136 hda_nid_t cvt_nids[4]; /* only for haswell fix */
139 * num_pins is the number of virtual pins
140 * for example, there are 3 pins, and each pin
141 * has 4 device entries, then the num_pins is 12
145 * num_nids is the number of real pins
146 * In the above example, num_nids is 3
150 * dev_num is the number of device entries
152 * In the above example, dev_num is 4
155 struct snd_array pins; /* struct hdmi_spec_per_pin */
156 struct hdmi_pcm pcm_rec[16];
157 struct mutex pcm_lock;
158 /* pcm_bitmap means which pcms have been assigned to pins*/
159 unsigned long pcm_bitmap;
160 int pcm_used; /* counter of pcm_rec[] */
161 /* bitmap shows whether the pcm is opened in user space
162 * bit 0 means the first playback PCM (PCM3);
163 * bit 1 means the second playback PCM, and so on.
165 unsigned long pcm_in_use;
167 struct hdmi_eld temp_eld;
173 * Non-generic VIA/NVIDIA specific
175 struct hda_multi_out multiout;
176 struct hda_pcm_stream pcm_playback;
178 /* i915/powerwell (Haswell+/Valleyview+) specific */
179 bool use_acomp_notifier; /* use i915 eld_notify callback for hotplug */
180 struct i915_audio_component_audio_ops i915_audio_ops;
182 struct hdac_chmap chmap;
183 hda_nid_t vendor_nid;
186 #ifdef CONFIG_SND_HDA_I915
187 static inline bool codec_has_acomp(struct hda_codec *codec)
189 struct hdmi_spec *spec = codec->spec;
190 return spec->use_acomp_notifier;
193 #define codec_has_acomp(codec) false
196 struct hdmi_audio_infoframe {
203 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
207 u8 LFEPBL01_LSV36_DM_INH7;
210 struct dp_audio_infoframe {
213 u8 ver; /* 0x11 << 2 */
215 u8 CC02_CT47; /* match with HDMI infoframe from this on */
219 u8 LFEPBL01_LSV36_DM_INH7;
222 union audio_infoframe {
223 struct hdmi_audio_infoframe hdmi;
224 struct dp_audio_infoframe dp;
232 #define get_pin(spec, idx) \
233 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
234 #define get_cvt(spec, idx) \
235 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
236 /* obtain hdmi_pcm object assigned to idx */
237 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
238 /* obtain hda_pcm object assigned to idx */
239 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
241 static int pin_id_to_pin_index(struct hda_codec *codec,
242 hda_nid_t pin_nid, int dev_id)
244 struct hdmi_spec *spec = codec->spec;
246 struct hdmi_spec_per_pin *per_pin;
249 * (dev_id == -1) means it is NON-MST pin
250 * return the first virtual pin on this port
255 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
256 per_pin = get_pin(spec, pin_idx);
257 if ((per_pin->pin_nid == pin_nid) &&
258 (per_pin->dev_id == dev_id))
262 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
266 static int hinfo_to_pcm_index(struct hda_codec *codec,
267 struct hda_pcm_stream *hinfo)
269 struct hdmi_spec *spec = codec->spec;
272 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
273 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
276 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
280 static int hinfo_to_pin_index(struct hda_codec *codec,
281 struct hda_pcm_stream *hinfo)
283 struct hdmi_spec *spec = codec->spec;
284 struct hdmi_spec_per_pin *per_pin;
287 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
288 per_pin = get_pin(spec, pin_idx);
290 per_pin->pcm->pcm->stream == hinfo)
294 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
298 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
302 struct hdmi_spec_per_pin *per_pin;
304 for (i = 0; i < spec->num_pins; i++) {
305 per_pin = get_pin(spec, i);
306 if (per_pin->pcm_idx == pcm_idx)
312 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
314 struct hdmi_spec *spec = codec->spec;
317 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
318 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
321 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
325 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
326 struct snd_ctl_elem_info *uinfo)
328 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
329 struct hdmi_spec *spec = codec->spec;
330 struct hdmi_spec_per_pin *per_pin;
331 struct hdmi_eld *eld;
334 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
336 pcm_idx = kcontrol->private_value;
337 mutex_lock(&spec->pcm_lock);
338 per_pin = pcm_idx_to_pin(spec, pcm_idx);
340 /* no pin is bound to the pcm */
342 mutex_unlock(&spec->pcm_lock);
345 eld = &per_pin->sink_eld;
346 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
347 mutex_unlock(&spec->pcm_lock);
352 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
353 struct snd_ctl_elem_value *ucontrol)
355 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
356 struct hdmi_spec *spec = codec->spec;
357 struct hdmi_spec_per_pin *per_pin;
358 struct hdmi_eld *eld;
361 pcm_idx = kcontrol->private_value;
362 mutex_lock(&spec->pcm_lock);
363 per_pin = pcm_idx_to_pin(spec, pcm_idx);
365 /* no pin is bound to the pcm */
366 memset(ucontrol->value.bytes.data, 0,
367 ARRAY_SIZE(ucontrol->value.bytes.data));
368 mutex_unlock(&spec->pcm_lock);
371 eld = &per_pin->sink_eld;
373 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
374 eld->eld_size > ELD_MAX_SIZE) {
375 mutex_unlock(&spec->pcm_lock);
380 memset(ucontrol->value.bytes.data, 0,
381 ARRAY_SIZE(ucontrol->value.bytes.data));
383 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
385 mutex_unlock(&spec->pcm_lock);
390 static const struct snd_kcontrol_new eld_bytes_ctl = {
391 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
392 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
394 .info = hdmi_eld_ctl_info,
395 .get = hdmi_eld_ctl_get,
398 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
401 struct snd_kcontrol *kctl;
402 struct hdmi_spec *spec = codec->spec;
405 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
408 kctl->private_value = pcm_idx;
409 kctl->id.device = device;
411 /* no pin nid is associated with the kctl now
412 * tbd: associate pin nid to eld ctl later
414 err = snd_hda_ctl_add(codec, 0, kctl);
418 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
423 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
424 int *packet_index, int *byte_index)
428 val = snd_hda_codec_read(codec, pin_nid, 0,
429 AC_VERB_GET_HDMI_DIP_INDEX, 0);
431 *packet_index = val >> 5;
432 *byte_index = val & 0x1f;
436 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
437 int packet_index, int byte_index)
441 val = (packet_index << 5) | (byte_index & 0x1f);
443 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
446 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
449 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
452 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
454 struct hdmi_spec *spec = codec->spec;
458 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
459 snd_hda_codec_write(codec, pin_nid, 0,
460 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
462 if (spec->dyn_pin_out)
463 /* Disable pin out until stream is active */
466 /* Enable pin out: some machines with GM965 gets broken output
467 * when the pin is disabled or changed while using with HDMI
471 snd_hda_codec_write(codec, pin_nid, 0,
472 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
479 #ifdef CONFIG_SND_PROC_FS
480 static void print_eld_info(struct snd_info_entry *entry,
481 struct snd_info_buffer *buffer)
483 struct hdmi_spec_per_pin *per_pin = entry->private_data;
485 mutex_lock(&per_pin->lock);
486 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
487 mutex_unlock(&per_pin->lock);
490 static void write_eld_info(struct snd_info_entry *entry,
491 struct snd_info_buffer *buffer)
493 struct hdmi_spec_per_pin *per_pin = entry->private_data;
495 mutex_lock(&per_pin->lock);
496 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
497 mutex_unlock(&per_pin->lock);
500 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
503 struct hda_codec *codec = per_pin->codec;
504 struct snd_info_entry *entry;
507 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
508 err = snd_card_proc_new(codec->card, name, &entry);
512 snd_info_set_text_ops(entry, per_pin, print_eld_info);
513 entry->c.text.write = write_eld_info;
515 per_pin->proc_entry = entry;
520 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
522 if (!per_pin->codec->bus->shutdown) {
523 snd_info_free_entry(per_pin->proc_entry);
524 per_pin->proc_entry = NULL;
528 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
533 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
539 * Audio InfoFrame routines
543 * Enable Audio InfoFrame Transmission
545 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
548 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
549 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
554 * Disable Audio InfoFrame Transmission
556 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
559 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
560 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
564 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
566 #ifdef CONFIG_SND_DEBUG_VERBOSE
570 size = snd_hdmi_get_eld_size(codec, pin_nid);
571 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
573 for (i = 0; i < 8; i++) {
574 size = snd_hda_codec_read(codec, pin_nid, 0,
575 AC_VERB_GET_HDMI_DIP_SIZE, i);
576 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
581 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
587 for (i = 0; i < 8; i++) {
588 size = snd_hda_codec_read(codec, pin_nid, 0,
589 AC_VERB_GET_HDMI_DIP_SIZE, i);
593 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
594 for (j = 1; j < 1000; j++) {
595 hdmi_write_dip_byte(codec, pin_nid, 0x0);
596 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
598 codec_dbg(codec, "dip index %d: %d != %d\n",
600 if (bi == 0) /* byte index wrapped around */
604 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
610 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
612 u8 *bytes = (u8 *)hdmi_ai;
616 hdmi_ai->checksum = 0;
618 for (i = 0; i < sizeof(*hdmi_ai); i++)
621 hdmi_ai->checksum = -sum;
624 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
630 hdmi_debug_dip_size(codec, pin_nid);
631 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
633 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
634 for (i = 0; i < size; i++)
635 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
638 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
644 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
648 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
649 for (i = 0; i < size; i++) {
650 val = snd_hda_codec_read(codec, pin_nid, 0,
651 AC_VERB_GET_HDMI_DIP_DATA, 0);
659 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
661 int ca, int active_channels,
664 union audio_infoframe ai;
666 memset(&ai, 0, sizeof(ai));
667 if (conn_type == 0) { /* HDMI */
668 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
670 hdmi_ai->type = 0x84;
673 hdmi_ai->CC02_CT47 = active_channels - 1;
675 hdmi_checksum_audio_infoframe(hdmi_ai);
676 } else if (conn_type == 1) { /* DisplayPort */
677 struct dp_audio_infoframe *dp_ai = &ai.dp;
681 dp_ai->ver = 0x11 << 2;
682 dp_ai->CC02_CT47 = active_channels - 1;
685 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
691 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
692 * sizeof(*dp_ai) to avoid partial match/update problems when
693 * the user switches between HDMI/DP monitors.
695 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
698 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
700 active_channels, ca);
701 hdmi_stop_infoframe_trans(codec, pin_nid);
702 hdmi_fill_audio_infoframe(codec, pin_nid,
703 ai.bytes, sizeof(ai));
704 hdmi_start_infoframe_trans(codec, pin_nid);
708 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
709 struct hdmi_spec_per_pin *per_pin,
712 struct hdmi_spec *spec = codec->spec;
713 struct hdac_chmap *chmap = &spec->chmap;
714 hda_nid_t pin_nid = per_pin->pin_nid;
715 int channels = per_pin->channels;
717 struct hdmi_eld *eld;
723 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
724 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
725 snd_hda_codec_write(codec, pin_nid, 0,
726 AC_VERB_SET_AMP_GAIN_MUTE,
729 eld = &per_pin->sink_eld;
731 ca = snd_hdac_channel_allocation(&codec->core,
732 eld->info.spk_alloc, channels,
733 per_pin->chmap_set, non_pcm, per_pin->chmap);
735 active_channels = snd_hdac_get_active_channels(ca);
737 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
741 * always configure channel mapping, it may have been changed by the
742 * user in the meantime
744 snd_hdac_setup_channel_mapping(&spec->chmap,
745 pin_nid, non_pcm, ca, channels,
746 per_pin->chmap, per_pin->chmap_set);
748 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
749 eld->info.conn_type);
751 per_pin->non_pcm = non_pcm;
758 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
760 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
763 struct hdmi_spec *spec = codec->spec;
764 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
768 mutex_lock(&spec->pcm_lock);
769 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
770 snd_hda_jack_report_sync(codec);
771 mutex_unlock(&spec->pcm_lock);
774 static void jack_callback(struct hda_codec *codec,
775 struct hda_jack_callback *jack)
777 /* hda_jack don't support DP MST */
778 check_presence_and_report(codec, jack->nid, 0);
781 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
783 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
784 struct hda_jack_tbl *jack;
785 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
788 * assume DP MST uses dyn_pcm_assign and acomp and
790 * if DP MST supports unsol event, below code need
793 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
796 jack->jack_dirty = 1;
799 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
800 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
801 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
803 /* hda_jack don't support DP MST */
804 check_presence_and_report(codec, jack->nid, 0);
807 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
809 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
810 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
811 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
812 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
815 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
830 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
832 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
833 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
835 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
836 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
841 hdmi_intrinsic_event(codec, res);
843 hdmi_non_intrinsic_event(codec, res);
846 static void haswell_verify_D0(struct hda_codec *codec,
847 hda_nid_t cvt_nid, hda_nid_t nid)
851 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
852 * thus pins could only choose converter 0 for use. Make sure the
853 * converters are in correct power state */
854 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
855 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
857 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
858 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
861 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
862 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
863 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
871 /* HBR should be Non-PCM, 8 channels */
872 #define is_hbr_format(format) \
873 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
875 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
878 int pinctl, new_pinctl;
880 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
881 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
882 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
885 return hbr ? -EINVAL : 0;
887 new_pinctl = pinctl & ~AC_PINCTL_EPT;
889 new_pinctl |= AC_PINCTL_EPT_HBR;
891 new_pinctl |= AC_PINCTL_EPT_NATIVE;
894 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
896 pinctl == new_pinctl ? "" : "new-",
899 if (pinctl != new_pinctl)
900 snd_hda_codec_write(codec, pin_nid, 0,
901 AC_VERB_SET_PIN_WIDGET_CONTROL,
909 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
910 hda_nid_t pin_nid, u32 stream_tag, int format)
912 struct hdmi_spec *spec = codec->spec;
916 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
919 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
923 if (is_haswell_plus(codec)) {
926 * on recent platforms IEC Coding Type is required for HBR
927 * support, read current Digital Converter settings and set
928 * ICT bitfield if needed.
930 param = snd_hda_codec_read(codec, cvt_nid, 0,
931 AC_VERB_GET_DIGI_CONVERT_1, 0);
933 param = (param >> 16) & ~(AC_DIG3_ICT);
935 /* on recent platforms ICT mode is required for HBR support */
936 if (is_hbr_format(format))
939 snd_hda_codec_write(codec, cvt_nid, 0,
940 AC_VERB_SET_DIGI_CONVERT_3, param);
943 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
947 /* Try to find an available converter
948 * If pin_idx is less then zero, just try to find an available converter.
949 * Otherwise, try to find an available converter and get the cvt mux index
952 static int hdmi_choose_cvt(struct hda_codec *codec,
953 int pin_idx, int *cvt_id)
955 struct hdmi_spec *spec = codec->spec;
956 struct hdmi_spec_per_pin *per_pin;
957 struct hdmi_spec_per_cvt *per_cvt = NULL;
958 int cvt_idx, mux_idx = 0;
960 /* pin_idx < 0 means no pin will be bound to the converter */
964 per_pin = get_pin(spec, pin_idx);
966 /* Dynamically assign converter to stream */
967 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
968 per_cvt = get_cvt(spec, cvt_idx);
970 /* Must not already be assigned */
971 if (per_cvt->assigned)
975 /* Must be in pin's mux's list of converters */
976 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
977 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
979 /* Not in mux list */
980 if (mux_idx == per_pin->num_mux_nids)
985 /* No free converters */
986 if (cvt_idx == spec->num_cvts)
990 per_pin->mux_idx = mux_idx;
998 /* Assure the pin select the right convetor */
999 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1000 struct hdmi_spec_per_pin *per_pin)
1002 hda_nid_t pin_nid = per_pin->pin_nid;
1005 mux_idx = per_pin->mux_idx;
1006 curr = snd_hda_codec_read(codec, pin_nid, 0,
1007 AC_VERB_GET_CONNECT_SEL, 0);
1008 if (curr != mux_idx)
1009 snd_hda_codec_write_cache(codec, pin_nid, 0,
1010 AC_VERB_SET_CONNECT_SEL,
1014 /* get the mux index for the converter of the pins
1015 * converter's mux index is the same for all pins on Intel platform
1017 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1022 for (i = 0; i < spec->num_cvts; i++)
1023 if (spec->cvt_nids[i] == cvt_nid)
1028 /* Intel HDMI workaround to fix audio routing issue:
1029 * For some Intel display codecs, pins share the same connection list.
1030 * So a conveter can be selected by multiple pins and playback on any of these
1031 * pins will generate sound on the external display, because audio flows from
1032 * the same converter to the display pipeline. Also muting one pin may make
1033 * other pins have no sound output.
1034 * So this function assures that an assigned converter for a pin is not selected
1035 * by any other pins.
1037 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1039 int dev_id, int mux_idx)
1041 struct hdmi_spec *spec = codec->spec;
1044 struct hdmi_spec_per_cvt *per_cvt;
1045 struct hdmi_spec_per_pin *per_pin;
1048 /* configure the pins connections */
1049 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1053 per_pin = get_pin(spec, pin_idx);
1055 * pin not connected to monitor
1056 * no need to operate on it
1061 if ((per_pin->pin_nid == pin_nid) &&
1062 (per_pin->dev_id == dev_id))
1066 * if per_pin->dev_id >= dev_num,
1067 * snd_hda_get_dev_select() will fail,
1068 * and the following operation is unpredictable.
1069 * So skip this situation.
1071 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1072 if (per_pin->dev_id >= dev_num)
1075 nid = per_pin->pin_nid;
1078 * Calling this function should not impact
1079 * on the device entry selection
1080 * So let's save the dev id for each pin,
1081 * and restore it when return
1083 dev_id_saved = snd_hda_get_dev_select(codec, nid);
1084 snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
1085 curr = snd_hda_codec_read(codec, nid, 0,
1086 AC_VERB_GET_CONNECT_SEL, 0);
1087 if (curr != mux_idx) {
1088 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1093 /* choose an unassigned converter. The conveters in the
1094 * connection list are in the same order as in the codec.
1096 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1097 per_cvt = get_cvt(spec, cvt_idx);
1098 if (!per_cvt->assigned) {
1100 "choose cvt %d for pin nid %d\n",
1102 snd_hda_codec_write_cache(codec, nid, 0,
1103 AC_VERB_SET_CONNECT_SEL,
1108 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1112 /* A wrapper of intel_not_share_asigned_cvt() */
1113 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1114 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
1117 struct hdmi_spec *spec = codec->spec;
1119 /* On Intel platform, the mapping of converter nid to
1120 * mux index of the pins are always the same.
1121 * The pin nid may be 0, this means all pins will not
1122 * share the converter.
1124 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1126 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
1129 /* skeleton caller of pin_cvt_fixup ops */
1130 static void pin_cvt_fixup(struct hda_codec *codec,
1131 struct hdmi_spec_per_pin *per_pin,
1134 struct hdmi_spec *spec = codec->spec;
1136 if (spec->ops.pin_cvt_fixup)
1137 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1140 /* called in hdmi_pcm_open when no pin is assigned to the PCM
1141 * in dyn_pcm_assign mode.
1143 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1144 struct hda_codec *codec,
1145 struct snd_pcm_substream *substream)
1147 struct hdmi_spec *spec = codec->spec;
1148 struct snd_pcm_runtime *runtime = substream->runtime;
1149 int cvt_idx, pcm_idx;
1150 struct hdmi_spec_per_cvt *per_cvt = NULL;
1153 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1157 err = hdmi_choose_cvt(codec, -1, &cvt_idx);
1161 per_cvt = get_cvt(spec, cvt_idx);
1162 per_cvt->assigned = 1;
1163 hinfo->nid = per_cvt->cvt_nid;
1165 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1167 set_bit(pcm_idx, &spec->pcm_in_use);
1168 /* todo: setup spdif ctls assign */
1170 /* Initially set the converter's capabilities */
1171 hinfo->channels_min = per_cvt->channels_min;
1172 hinfo->channels_max = per_cvt->channels_max;
1173 hinfo->rates = per_cvt->rates;
1174 hinfo->formats = per_cvt->formats;
1175 hinfo->maxbps = per_cvt->maxbps;
1177 /* Store the updated parameters */
1178 runtime->hw.channels_min = hinfo->channels_min;
1179 runtime->hw.channels_max = hinfo->channels_max;
1180 runtime->hw.formats = hinfo->formats;
1181 runtime->hw.rates = hinfo->rates;
1183 snd_pcm_hw_constraint_step(substream->runtime, 0,
1184 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1191 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1192 struct hda_codec *codec,
1193 struct snd_pcm_substream *substream)
1195 struct hdmi_spec *spec = codec->spec;
1196 struct snd_pcm_runtime *runtime = substream->runtime;
1197 int pin_idx, cvt_idx, pcm_idx;
1198 struct hdmi_spec_per_pin *per_pin;
1199 struct hdmi_eld *eld;
1200 struct hdmi_spec_per_cvt *per_cvt = NULL;
1203 /* Validate hinfo */
1204 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1208 mutex_lock(&spec->pcm_lock);
1209 pin_idx = hinfo_to_pin_index(codec, hinfo);
1210 if (!spec->dyn_pcm_assign) {
1211 if (snd_BUG_ON(pin_idx < 0)) {
1212 mutex_unlock(&spec->pcm_lock);
1216 /* no pin is assigned to the PCM
1217 * PA need pcm open successfully when probe
1220 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1221 mutex_unlock(&spec->pcm_lock);
1226 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
1228 mutex_unlock(&spec->pcm_lock);
1232 per_cvt = get_cvt(spec, cvt_idx);
1233 /* Claim converter */
1234 per_cvt->assigned = 1;
1236 set_bit(pcm_idx, &spec->pcm_in_use);
1237 per_pin = get_pin(spec, pin_idx);
1238 per_pin->cvt_nid = per_cvt->cvt_nid;
1239 hinfo->nid = per_cvt->cvt_nid;
1241 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1242 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1243 AC_VERB_SET_CONNECT_SEL,
1246 /* configure unused pins to choose other converters */
1247 pin_cvt_fixup(codec, per_pin, 0);
1249 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1251 /* Initially set the converter's capabilities */
1252 hinfo->channels_min = per_cvt->channels_min;
1253 hinfo->channels_max = per_cvt->channels_max;
1254 hinfo->rates = per_cvt->rates;
1255 hinfo->formats = per_cvt->formats;
1256 hinfo->maxbps = per_cvt->maxbps;
1258 eld = &per_pin->sink_eld;
1259 /* Restrict capabilities by ELD if this isn't disabled */
1260 if (!static_hdmi_pcm && eld->eld_valid) {
1261 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1262 if (hinfo->channels_min > hinfo->channels_max ||
1263 !hinfo->rates || !hinfo->formats) {
1264 per_cvt->assigned = 0;
1266 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1267 mutex_unlock(&spec->pcm_lock);
1272 mutex_unlock(&spec->pcm_lock);
1273 /* Store the updated parameters */
1274 runtime->hw.channels_min = hinfo->channels_min;
1275 runtime->hw.channels_max = hinfo->channels_max;
1276 runtime->hw.formats = hinfo->formats;
1277 runtime->hw.rates = hinfo->rates;
1279 snd_pcm_hw_constraint_step(substream->runtime, 0,
1280 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1285 * HDA/HDMI auto parsing
1287 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1289 struct hdmi_spec *spec = codec->spec;
1290 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1291 hda_nid_t pin_nid = per_pin->pin_nid;
1293 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1295 "HDMI: pin %d wcaps %#x does not support connection list\n",
1296 pin_nid, get_wcaps(codec, pin_nid));
1300 /* all the device entries on the same pin have the same conn list */
1301 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1303 HDA_MAX_CONNECTIONS);
1308 static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1309 struct hdmi_spec_per_pin *per_pin)
1313 /* try the prefer PCM */
1314 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1315 return per_pin->pin_nid_idx;
1317 /* have a second try; check the "reserved area" over num_pins */
1318 for (i = spec->num_nids; i < spec->pcm_used; i++) {
1319 if (!test_bit(i, &spec->pcm_bitmap))
1323 /* the last try; check the empty slots in pins */
1324 for (i = 0; i < spec->num_nids; i++) {
1325 if (!test_bit(i, &spec->pcm_bitmap))
1331 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1332 struct hdmi_spec_per_pin *per_pin)
1336 /* pcm already be attached to the pin */
1339 idx = hdmi_find_pcm_slot(spec, per_pin);
1342 per_pin->pcm_idx = idx;
1343 per_pin->pcm = get_hdmi_pcm(spec, idx);
1344 set_bit(idx, &spec->pcm_bitmap);
1347 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1348 struct hdmi_spec_per_pin *per_pin)
1352 /* pcm already be detached from the pin */
1355 idx = per_pin->pcm_idx;
1356 per_pin->pcm_idx = -1;
1357 per_pin->pcm = NULL;
1358 if (idx >= 0 && idx < spec->pcm_used)
1359 clear_bit(idx, &spec->pcm_bitmap);
1362 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1363 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1367 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1368 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1373 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1375 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1376 struct hdmi_spec_per_pin *per_pin)
1378 struct hda_codec *codec = per_pin->codec;
1379 struct hda_pcm *pcm;
1380 struct hda_pcm_stream *hinfo;
1381 struct snd_pcm_substream *substream;
1385 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1386 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1391 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1394 /* hdmi audio only uses playback and one substream */
1395 hinfo = pcm->stream;
1396 substream = pcm->pcm->streams[0].substream;
1398 per_pin->cvt_nid = hinfo->nid;
1400 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1401 if (mux_idx < per_pin->num_mux_nids) {
1402 snd_hda_set_dev_select(codec, per_pin->pin_nid,
1404 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1405 AC_VERB_SET_CONNECT_SEL,
1408 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1410 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1411 if (substream->runtime)
1412 per_pin->channels = substream->runtime->channels;
1413 per_pin->setup = true;
1414 per_pin->mux_idx = mux_idx;
1416 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1419 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1420 struct hdmi_spec_per_pin *per_pin)
1422 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1423 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1425 per_pin->chmap_set = false;
1426 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1428 per_pin->setup = false;
1429 per_pin->channels = 0;
1432 /* update per_pin ELD from the given new ELD;
1433 * setup info frame and notification accordingly
1435 static void update_eld(struct hda_codec *codec,
1436 struct hdmi_spec_per_pin *per_pin,
1437 struct hdmi_eld *eld)
1439 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1440 struct hdmi_spec *spec = codec->spec;
1441 bool old_eld_valid = pin_eld->eld_valid;
1445 /* for monitor disconnection, save pcm_idx firstly */
1446 pcm_idx = per_pin->pcm_idx;
1447 if (spec->dyn_pcm_assign) {
1448 if (eld->eld_valid) {
1449 hdmi_attach_hda_pcm(spec, per_pin);
1450 hdmi_pcm_setup_pin(spec, per_pin);
1452 hdmi_pcm_reset_pin(spec, per_pin);
1453 hdmi_detach_hda_pcm(spec, per_pin);
1456 /* if pcm_idx == -1, it means this is in monitor connection event
1457 * we can get the correct pcm_idx now.
1460 pcm_idx = per_pin->pcm_idx;
1463 snd_hdmi_show_eld(codec, &eld->info);
1465 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1466 if (eld->eld_valid && pin_eld->eld_valid)
1467 if (pin_eld->eld_size != eld->eld_size ||
1468 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1469 eld->eld_size) != 0)
1472 pin_eld->monitor_present = eld->monitor_present;
1473 pin_eld->eld_valid = eld->eld_valid;
1474 pin_eld->eld_size = eld->eld_size;
1476 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size);
1477 pin_eld->info = eld->info;
1480 * Re-setup pin and infoframe. This is needed e.g. when
1481 * - sink is first plugged-in
1482 * - transcoder can change during stream playback on Haswell
1483 * and this can make HW reset converter selection on a pin.
1485 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1486 pin_cvt_fixup(codec, per_pin, 0);
1487 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1490 if (eld_changed && pcm_idx >= 0)
1491 snd_ctl_notify(codec->card,
1492 SNDRV_CTL_EVENT_MASK_VALUE |
1493 SNDRV_CTL_EVENT_MASK_INFO,
1494 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1497 /* update ELD and jack state via HD-audio verbs */
1498 static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1501 struct hda_jack_tbl *jack;
1502 struct hda_codec *codec = per_pin->codec;
1503 struct hdmi_spec *spec = codec->spec;
1504 struct hdmi_eld *eld = &spec->temp_eld;
1505 hda_nid_t pin_nid = per_pin->pin_nid;
1507 * Always execute a GetPinSense verb here, even when called from
1508 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1509 * response's PD bit is not the real PD value, but indicates that
1510 * the real PD value changed. An older version of the HD-audio
1511 * specification worked this way. Hence, we just ignore the data in
1512 * the unsolicited response to avoid custom WARs.
1516 bool do_repoll = false;
1518 present = snd_hda_pin_sense(codec, pin_nid);
1520 mutex_lock(&per_pin->lock);
1521 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1522 if (eld->monitor_present)
1523 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1525 eld->eld_valid = false;
1528 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1529 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1531 if (eld->eld_valid) {
1532 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1533 &eld->eld_size) < 0)
1534 eld->eld_valid = false;
1536 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1538 eld->eld_valid = false;
1540 if (!eld->eld_valid && repoll)
1545 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1547 update_eld(codec, per_pin, eld);
1549 ret = !repoll || !eld->monitor_present || eld->eld_valid;
1551 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1553 jack->block_report = !ret;
1555 mutex_unlock(&per_pin->lock);
1559 static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec,
1560 struct hdmi_spec_per_pin *per_pin)
1562 struct hdmi_spec *spec = codec->spec;
1563 struct snd_jack *jack = NULL;
1564 struct hda_jack_tbl *jack_tbl;
1566 /* if !dyn_pcm_assign, get jack from hda_jack_tbl
1567 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not
1568 * NULL even after snd_hda_jack_tbl_clear() is called to
1569 * free snd_jack. This may cause access invalid memory
1570 * when calling snd_jack_report
1572 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign)
1573 jack = spec->pcm_rec[per_pin->pcm_idx].jack;
1574 else if (!spec->dyn_pcm_assign) {
1576 * jack tbl doesn't support DP MST
1577 * DP MST will use dyn_pcm_assign,
1578 * so DP MST will never come here
1580 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1582 jack = jack_tbl->jack;
1587 /* update ELD and jack state via audio component */
1588 static void sync_eld_via_acomp(struct hda_codec *codec,
1589 struct hdmi_spec_per_pin *per_pin)
1591 struct hdmi_spec *spec = codec->spec;
1592 struct hdmi_eld *eld = &spec->temp_eld;
1593 struct snd_jack *jack = NULL;
1596 mutex_lock(&per_pin->lock);
1597 eld->monitor_present = false;
1598 size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1599 per_pin->dev_id, &eld->monitor_present,
1600 eld->eld_buffer, ELD_MAX_SIZE);
1602 size = min(size, ELD_MAX_SIZE);
1603 if (snd_hdmi_parse_eld(codec, &eld->info,
1604 eld->eld_buffer, size) < 0)
1609 eld->eld_valid = true;
1610 eld->eld_size = size;
1612 eld->eld_valid = false;
1616 /* pcm_idx >=0 before update_eld() means it is in monitor
1617 * disconnected event. Jack must be fetched before update_eld()
1619 jack = pin_idx_to_jack(codec, per_pin);
1620 update_eld(codec, per_pin, eld);
1622 jack = pin_idx_to_jack(codec, per_pin);
1625 snd_jack_report(jack,
1626 eld->monitor_present ? SND_JACK_AVOUT : 0);
1628 mutex_unlock(&per_pin->lock);
1631 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1633 struct hda_codec *codec = per_pin->codec;
1636 /* no temporary power up/down needed for component notifier */
1637 if (!codec_has_acomp(codec)) {
1638 ret = snd_hda_power_up_pm(codec);
1639 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) {
1640 snd_hda_power_down_pm(codec);
1645 if (codec_has_acomp(codec)) {
1646 sync_eld_via_acomp(codec, per_pin);
1647 ret = false; /* don't call snd_hda_jack_report_sync() */
1649 ret = hdmi_present_sense_via_verbs(per_pin, repoll);
1652 if (!codec_has_acomp(codec))
1653 snd_hda_power_down_pm(codec);
1658 static void hdmi_repoll_eld(struct work_struct *work)
1660 struct hdmi_spec_per_pin *per_pin =
1661 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1662 struct hda_codec *codec = per_pin->codec;
1663 struct hdmi_spec *spec = codec->spec;
1665 if (per_pin->repoll_count++ > 6)
1666 per_pin->repoll_count = 0;
1668 mutex_lock(&spec->pcm_lock);
1669 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1670 snd_hda_jack_report_sync(per_pin->codec);
1671 mutex_unlock(&spec->pcm_lock);
1674 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1677 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1679 struct hdmi_spec *spec = codec->spec;
1680 unsigned int caps, config;
1682 struct hdmi_spec_per_pin *per_pin;
1686 caps = snd_hda_query_pin_caps(codec, pin_nid);
1687 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1691 * For DP MST audio, Configuration Default is the same for
1692 * all device entries on the same pin
1694 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1695 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1699 * To simplify the implementation, malloc all
1700 * the virtual pins in the initialization statically
1702 if (is_haswell_plus(codec)) {
1704 * On Intel platforms, device entries number is
1705 * changed dynamically. If there is a DP MST
1706 * hub connected, the device entries number is 3.
1707 * Otherwise, it is 1.
1708 * Here we manually set dev_num to 3, so that
1709 * we can initialize all the device entries when
1710 * bootup statically.
1714 } else if (spec->dyn_pcm_assign && codec->dp_mst) {
1715 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1717 * spec->dev_num is the maxinum number of device entries
1718 * among all the pins
1720 spec->dev_num = (spec->dev_num > dev_num) ?
1721 spec->dev_num : dev_num;
1724 * If the platform doesn't support DP MST,
1725 * manually set dev_num to 1. This means
1726 * the pin has only one device entry.
1732 for (i = 0; i < dev_num; i++) {
1733 pin_idx = spec->num_pins;
1734 per_pin = snd_array_new(&spec->pins);
1739 if (spec->dyn_pcm_assign) {
1740 per_pin->pcm = NULL;
1741 per_pin->pcm_idx = -1;
1743 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1744 per_pin->pcm_idx = pin_idx;
1746 per_pin->pin_nid = pin_nid;
1747 per_pin->pin_nid_idx = spec->num_nids;
1748 per_pin->dev_id = i;
1749 per_pin->non_pcm = false;
1750 snd_hda_set_dev_select(codec, pin_nid, i);
1751 if (is_haswell_plus(codec))
1752 intel_haswell_fixup_connect_list(codec, pin_nid);
1753 err = hdmi_read_pin_conn(codec, pin_idx);
1763 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1765 struct hdmi_spec *spec = codec->spec;
1766 struct hdmi_spec_per_cvt *per_cvt;
1770 chans = get_wcaps(codec, cvt_nid);
1771 chans = get_wcaps_channels(chans);
1773 per_cvt = snd_array_new(&spec->cvts);
1777 per_cvt->cvt_nid = cvt_nid;
1778 per_cvt->channels_min = 2;
1780 per_cvt->channels_max = chans;
1781 if (chans > spec->chmap.channels_max)
1782 spec->chmap.channels_max = chans;
1785 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1792 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1793 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1799 static int hdmi_parse_codec(struct hda_codec *codec)
1804 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1805 if (!nid || nodes < 0) {
1806 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1810 for (i = 0; i < nodes; i++, nid++) {
1814 caps = get_wcaps(codec, nid);
1815 type = get_wcaps_type(caps);
1817 if (!(caps & AC_WCAP_DIGITAL))
1821 case AC_WID_AUD_OUT:
1822 hdmi_add_cvt(codec, nid);
1825 hdmi_add_pin(codec, nid);
1835 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1837 struct hda_spdif_out *spdif;
1840 mutex_lock(&codec->spdif_mutex);
1841 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1842 /* Add sanity check to pass klockwork check.
1843 * This should never happen.
1845 if (WARN_ON(spdif == NULL))
1847 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1848 mutex_unlock(&codec->spdif_mutex);
1856 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1857 struct hda_codec *codec,
1858 unsigned int stream_tag,
1859 unsigned int format,
1860 struct snd_pcm_substream *substream)
1862 hda_nid_t cvt_nid = hinfo->nid;
1863 struct hdmi_spec *spec = codec->spec;
1865 struct hdmi_spec_per_pin *per_pin;
1867 struct snd_pcm_runtime *runtime = substream->runtime;
1872 mutex_lock(&spec->pcm_lock);
1873 pin_idx = hinfo_to_pin_index(codec, hinfo);
1874 if (spec->dyn_pcm_assign && pin_idx < 0) {
1875 /* when dyn_pcm_assign and pcm is not bound to a pin
1876 * skip pin setup and return 0 to make audio playback
1879 pin_cvt_fixup(codec, NULL, cvt_nid);
1880 snd_hda_codec_setup_stream(codec, cvt_nid,
1881 stream_tag, 0, format);
1882 mutex_unlock(&spec->pcm_lock);
1886 if (snd_BUG_ON(pin_idx < 0)) {
1887 mutex_unlock(&spec->pcm_lock);
1890 per_pin = get_pin(spec, pin_idx);
1891 pin_nid = per_pin->pin_nid;
1893 /* Verify pin:cvt selections to avoid silent audio after S3.
1894 * After S3, the audio driver restores pin:cvt selections
1895 * but this can happen before gfx is ready and such selection
1896 * is overlooked by HW. Thus multiple pins can share a same
1897 * default convertor and mute control will affect each other,
1898 * which can cause a resumed audio playback become silent
1901 pin_cvt_fixup(codec, per_pin, 0);
1903 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1904 /* Todo: add DP1.2 MST audio support later */
1905 if (codec_has_acomp(codec))
1906 snd_hdac_sync_audio_rate(&codec->core, pin_nid, per_pin->dev_id,
1909 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1910 mutex_lock(&per_pin->lock);
1911 per_pin->channels = substream->runtime->channels;
1912 per_pin->setup = true;
1914 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1915 mutex_unlock(&per_pin->lock);
1916 if (spec->dyn_pin_out) {
1917 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1918 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1919 snd_hda_codec_write(codec, pin_nid, 0,
1920 AC_VERB_SET_PIN_WIDGET_CONTROL,
1924 /* snd_hda_set_dev_select() has been called before */
1925 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid,
1926 stream_tag, format);
1927 mutex_unlock(&spec->pcm_lock);
1931 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1932 struct hda_codec *codec,
1933 struct snd_pcm_substream *substream)
1935 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1939 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1940 struct hda_codec *codec,
1941 struct snd_pcm_substream *substream)
1943 struct hdmi_spec *spec = codec->spec;
1944 int cvt_idx, pin_idx, pcm_idx;
1945 struct hdmi_spec_per_cvt *per_cvt;
1946 struct hdmi_spec_per_pin *per_pin;
1950 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1951 if (snd_BUG_ON(pcm_idx < 0))
1953 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1954 if (snd_BUG_ON(cvt_idx < 0))
1956 per_cvt = get_cvt(spec, cvt_idx);
1958 snd_BUG_ON(!per_cvt->assigned);
1959 per_cvt->assigned = 0;
1962 mutex_lock(&spec->pcm_lock);
1963 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1964 clear_bit(pcm_idx, &spec->pcm_in_use);
1965 pin_idx = hinfo_to_pin_index(codec, hinfo);
1966 if (spec->dyn_pcm_assign && pin_idx < 0) {
1967 mutex_unlock(&spec->pcm_lock);
1971 if (snd_BUG_ON(pin_idx < 0)) {
1972 mutex_unlock(&spec->pcm_lock);
1975 per_pin = get_pin(spec, pin_idx);
1977 if (spec->dyn_pin_out) {
1978 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1979 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1980 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1981 AC_VERB_SET_PIN_WIDGET_CONTROL,
1985 mutex_lock(&per_pin->lock);
1986 per_pin->chmap_set = false;
1987 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1989 per_pin->setup = false;
1990 per_pin->channels = 0;
1991 mutex_unlock(&per_pin->lock);
1992 mutex_unlock(&spec->pcm_lock);
1998 static const struct hda_pcm_ops generic_ops = {
1999 .open = hdmi_pcm_open,
2000 .close = hdmi_pcm_close,
2001 .prepare = generic_hdmi_playback_pcm_prepare,
2002 .cleanup = generic_hdmi_playback_pcm_cleanup,
2005 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
2007 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2008 struct hdmi_spec *spec = codec->spec;
2009 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2014 return per_pin->sink_eld.info.spk_alloc;
2017 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
2018 unsigned char *chmap)
2020 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2021 struct hdmi_spec *spec = codec->spec;
2022 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2024 /* chmap is already set to 0 in caller */
2028 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
2031 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
2032 unsigned char *chmap, int prepared)
2034 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2035 struct hdmi_spec *spec = codec->spec;
2036 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2040 mutex_lock(&per_pin->lock);
2041 per_pin->chmap_set = true;
2042 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2044 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2045 mutex_unlock(&per_pin->lock);
2048 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2050 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2051 struct hdmi_spec *spec = codec->spec;
2052 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2054 return per_pin ? true:false;
2057 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2059 struct hdmi_spec *spec = codec->spec;
2063 * for non-mst mode, pcm number is the same as before
2064 * for DP MST mode, pcm number is (nid number + dev_num - 1)
2065 * dev_num is the device entry number in a pin
2068 for (idx = 0; idx < spec->num_nids + spec->dev_num - 1; idx++) {
2069 struct hda_pcm *info;
2070 struct hda_pcm_stream *pstr;
2072 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
2076 spec->pcm_rec[idx].pcm = info;
2078 info->pcm_type = HDA_PCM_TYPE_HDMI;
2079 info->own_chmap = true;
2081 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2082 pstr->substreams = 1;
2083 pstr->ops = generic_ops;
2084 /* pcm number is less than 16 */
2085 if (spec->pcm_used >= 16)
2087 /* other pstr fields are set in open */
2093 static void free_hdmi_jack_priv(struct snd_jack *jack)
2095 struct hdmi_pcm *pcm = jack->private_data;
2100 static int add_hdmi_jack_kctl(struct hda_codec *codec,
2101 struct hdmi_spec *spec,
2105 struct snd_jack *jack;
2108 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
2113 spec->pcm_rec[pcm_idx].jack = jack;
2114 jack->private_data = &spec->pcm_rec[pcm_idx];
2115 jack->private_free = free_hdmi_jack_priv;
2119 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
2121 char hdmi_str[32] = "HDMI/DP";
2122 struct hdmi_spec *spec = codec->spec;
2123 struct hdmi_spec_per_pin *per_pin;
2124 struct hda_jack_tbl *jack;
2125 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
2130 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2132 if (spec->dyn_pcm_assign)
2133 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str);
2135 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */
2136 /* if !dyn_pcm_assign, it must be non-MST mode.
2137 * This means pcms and pins are statically mapped.
2138 * And pcm_idx is pin_idx.
2140 per_pin = get_pin(spec, pcm_idx);
2141 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
2143 strncat(hdmi_str, " Phantom",
2144 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2145 ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
2149 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
2152 /* assign jack->jack to pcm_rec[].jack to
2153 * align with dyn_pcm_assign mode
2155 spec->pcm_rec[pcm_idx].jack = jack->jack;
2159 static int generic_hdmi_build_controls(struct hda_codec *codec)
2161 struct hdmi_spec *spec = codec->spec;
2163 int pin_idx, pcm_idx;
2165 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2166 if (!get_pcm_rec(spec, pcm_idx)->pcm) {
2167 /* no PCM: mark this for skipping permanently */
2168 set_bit(pcm_idx, &spec->pcm_bitmap);
2172 err = generic_hdmi_build_jack(codec, pcm_idx);
2176 /* create the spdif for each pcm
2177 * pin will be bound when monitor is connected
2179 if (spec->dyn_pcm_assign)
2180 err = snd_hda_create_dig_out_ctls(codec,
2181 0, spec->cvt_nids[0],
2184 struct hdmi_spec_per_pin *per_pin =
2185 get_pin(spec, pcm_idx);
2186 err = snd_hda_create_dig_out_ctls(codec,
2188 per_pin->mux_nids[0],
2193 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2195 dev = get_pcm_rec(spec, pcm_idx)->device;
2196 if (dev != SNDRV_PCM_INVALID_DEVICE) {
2197 /* add control for ELD Bytes */
2198 err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2204 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2205 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2207 hdmi_present_sense(per_pin, 0);
2210 /* add channel maps */
2211 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2212 struct hda_pcm *pcm;
2214 pcm = get_pcm_rec(spec, pcm_idx);
2215 if (!pcm || !pcm->pcm)
2217 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2225 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2227 struct hdmi_spec *spec = codec->spec;
2230 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2231 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2233 per_pin->codec = codec;
2234 mutex_init(&per_pin->lock);
2235 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2236 eld_proc_new(per_pin, pin_idx);
2241 static int generic_hdmi_init(struct hda_codec *codec)
2243 struct hdmi_spec *spec = codec->spec;
2246 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2247 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2248 hda_nid_t pin_nid = per_pin->pin_nid;
2249 int dev_id = per_pin->dev_id;
2251 snd_hda_set_dev_select(codec, pin_nid, dev_id);
2252 hdmi_init_pin(codec, pin_nid);
2253 if (!codec_has_acomp(codec))
2254 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2255 codec->jackpoll_interval > 0 ?
2256 jack_callback : NULL);
2261 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2263 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2264 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2267 static void hdmi_array_free(struct hdmi_spec *spec)
2269 snd_array_free(&spec->pins);
2270 snd_array_free(&spec->cvts);
2273 static void generic_spec_free(struct hda_codec *codec)
2275 struct hdmi_spec *spec = codec->spec;
2278 hdmi_array_free(spec);
2282 codec->dp_mst = false;
2285 static void generic_hdmi_free(struct hda_codec *codec)
2287 struct hdmi_spec *spec = codec->spec;
2288 int pin_idx, pcm_idx;
2290 if (codec_has_acomp(codec))
2291 snd_hdac_i915_register_notifier(NULL);
2293 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2294 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2295 cancel_delayed_work_sync(&per_pin->work);
2296 eld_proc_free(per_pin);
2299 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2300 if (spec->pcm_rec[pcm_idx].jack == NULL)
2302 if (spec->dyn_pcm_assign)
2303 snd_device_free(codec->card,
2304 spec->pcm_rec[pcm_idx].jack);
2306 spec->pcm_rec[pcm_idx].jack = NULL;
2309 generic_spec_free(codec);
2313 static int generic_hdmi_resume(struct hda_codec *codec)
2315 struct hdmi_spec *spec = codec->spec;
2318 codec->patch_ops.init(codec);
2319 regcache_sync(codec->core.regmap);
2321 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2322 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2323 hdmi_present_sense(per_pin, 1);
2329 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2330 .init = generic_hdmi_init,
2331 .free = generic_hdmi_free,
2332 .build_pcms = generic_hdmi_build_pcms,
2333 .build_controls = generic_hdmi_build_controls,
2334 .unsol_event = hdmi_unsol_event,
2336 .resume = generic_hdmi_resume,
2340 static const struct hdmi_ops generic_standard_hdmi_ops = {
2341 .pin_get_eld = snd_hdmi_get_eld,
2342 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2343 .pin_hbr_setup = hdmi_pin_hbr_setup,
2344 .setup_stream = hdmi_setup_stream,
2347 /* allocate codec->spec and assign/initialize generic parser ops */
2348 static int alloc_generic_hdmi(struct hda_codec *codec)
2350 struct hdmi_spec *spec;
2352 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2356 spec->ops = generic_standard_hdmi_ops;
2357 spec->dev_num = 1; /* initialize to 1 */
2358 mutex_init(&spec->pcm_lock);
2359 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2361 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2362 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2363 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2364 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc,
2367 hdmi_array_init(spec, 4);
2369 codec->patch_ops = generic_hdmi_patch_ops;
2374 /* generic HDMI parser */
2375 static int patch_generic_hdmi(struct hda_codec *codec)
2379 err = alloc_generic_hdmi(codec);
2383 err = hdmi_parse_codec(codec);
2385 generic_spec_free(codec);
2389 generic_hdmi_init_per_pins(codec);
2394 * Intel codec parsers and helpers
2397 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2400 struct hdmi_spec *spec = codec->spec;
2404 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2405 if (nconns == spec->num_cvts &&
2406 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2409 /* override pins connection list */
2410 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2411 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2414 #define INTEL_VENDOR_NID 0x08
2415 #define INTEL_GLK_VENDOR_NID 0x0B
2416 #define INTEL_GET_VENDOR_VERB 0xf81
2417 #define INTEL_SET_VENDOR_VERB 0x781
2418 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2419 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2421 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2424 unsigned int vendor_param;
2425 struct hdmi_spec *spec = codec->spec;
2427 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2428 INTEL_GET_VENDOR_VERB, 0);
2429 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2432 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2433 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2434 INTEL_SET_VENDOR_VERB, vendor_param);
2435 if (vendor_param == -1)
2439 snd_hda_codec_update_widgets(codec);
2442 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2444 unsigned int vendor_param;
2445 struct hdmi_spec *spec = codec->spec;
2447 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2448 INTEL_GET_VENDOR_VERB, 0);
2449 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2452 /* enable DP1.2 mode */
2453 vendor_param |= INTEL_EN_DP12;
2454 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2455 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
2456 INTEL_SET_VENDOR_VERB, vendor_param);
2459 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2460 * Otherwise you may get severe h/w communication errors.
2462 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2463 unsigned int power_state)
2465 if (power_state == AC_PWRST_D0) {
2466 intel_haswell_enable_all_pins(codec, false);
2467 intel_haswell_fixup_enable_dp12(codec);
2470 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2471 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2474 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
2476 struct hda_codec *codec = audio_ptr;
2480 /* we assume only from port-B to port-D */
2481 if (port < 1 || port > 3)
2484 switch (codec->core.vendor_id) {
2485 case 0x80860054: /* ILK */
2486 case 0x80862804: /* ILK */
2487 case 0x80862882: /* VLV */
2488 pin_nid = port + 0x03;
2491 pin_nid = port + 0x04;
2495 /* skip notification during system suspend (but not in runtime PM);
2496 * the state will be updated at resume
2498 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2500 /* ditto during suspend/resume process itself */
2501 if (atomic_read(&(codec)->core.in_pm))
2504 snd_hdac_i915_set_bclk(&codec->bus->core);
2505 check_presence_and_report(codec, pin_nid, dev_id);
2508 /* register i915 component pin_eld_notify callback */
2509 static void register_i915_notifier(struct hda_codec *codec)
2511 struct hdmi_spec *spec = codec->spec;
2513 spec->use_acomp_notifier = true;
2514 spec->i915_audio_ops.audio_ptr = codec;
2515 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2516 * will call pin_eld_notify with using audio_ptr pointer
2517 * We need make sure audio_ptr is really setup
2520 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2521 snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2524 /* setup_stream ops override for HSW+ */
2525 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2526 hda_nid_t pin_nid, u32 stream_tag, int format)
2528 haswell_verify_D0(codec, cvt_nid, pin_nid);
2529 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
2532 /* pin_cvt_fixup ops override for HSW+ and VLV+ */
2533 static void i915_pin_cvt_fixup(struct hda_codec *codec,
2534 struct hdmi_spec_per_pin *per_pin,
2538 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2540 intel_verify_pin_cvt_connect(codec, per_pin);
2541 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2542 per_pin->dev_id, per_pin->mux_idx);
2544 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
2548 /* precondition and allocation for Intel codecs */
2549 static int alloc_intel_hdmi(struct hda_codec *codec)
2551 /* requires i915 binding */
2552 if (!codec->bus->core.audio_component) {
2553 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2557 return alloc_generic_hdmi(codec);
2560 /* parse and post-process for Intel codecs */
2561 static int parse_intel_hdmi(struct hda_codec *codec)
2565 err = hdmi_parse_codec(codec);
2567 generic_spec_free(codec);
2571 generic_hdmi_init_per_pins(codec);
2572 register_i915_notifier(codec);
2576 /* Intel Haswell and onwards; audio component with eld notifier */
2577 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid)
2579 struct hdmi_spec *spec;
2582 err = alloc_intel_hdmi(codec);
2586 codec->dp_mst = true;
2587 spec->dyn_pcm_assign = true;
2588 spec->vendor_nid = vendor_nid;
2590 intel_haswell_enable_all_pins(codec, true);
2591 intel_haswell_fixup_enable_dp12(codec);
2593 /* For Haswell/Broadwell, the controller is also in the power well and
2594 * can cover the codec power request, and so need not set this flag.
2596 if (!is_haswell(codec) && !is_broadwell(codec))
2597 codec->core.link_power_control = 1;
2599 codec->patch_ops.set_power_state = haswell_set_power_state;
2600 codec->depop_delay = 0;
2601 codec->auto_runtime_pm = 1;
2603 spec->ops.setup_stream = i915_hsw_setup_stream;
2604 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2606 return parse_intel_hdmi(codec);
2609 static int patch_i915_hsw_hdmi(struct hda_codec *codec)
2611 return intel_hsw_common_init(codec, INTEL_VENDOR_NID);
2614 static int patch_i915_glk_hdmi(struct hda_codec *codec)
2616 return intel_hsw_common_init(codec, INTEL_GLK_VENDOR_NID);
2619 /* Intel Baytrail and Braswell; with eld notifier */
2620 static int patch_i915_byt_hdmi(struct hda_codec *codec)
2622 struct hdmi_spec *spec;
2625 err = alloc_intel_hdmi(codec);
2630 /* For Valleyview/Cherryview, only the display codec is in the display
2631 * power well and can use link_power ops to request/release the power.
2633 codec->core.link_power_control = 1;
2635 codec->depop_delay = 0;
2636 codec->auto_runtime_pm = 1;
2638 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2640 return parse_intel_hdmi(codec);
2643 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
2644 static int patch_i915_cpt_hdmi(struct hda_codec *codec)
2648 err = alloc_intel_hdmi(codec);
2651 return parse_intel_hdmi(codec);
2655 * Shared non-generic implementations
2658 static int simple_playback_build_pcms(struct hda_codec *codec)
2660 struct hdmi_spec *spec = codec->spec;
2661 struct hda_pcm *info;
2663 struct hda_pcm_stream *pstr;
2664 struct hdmi_spec_per_cvt *per_cvt;
2666 per_cvt = get_cvt(spec, 0);
2667 chans = get_wcaps(codec, per_cvt->cvt_nid);
2668 chans = get_wcaps_channels(chans);
2670 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2673 spec->pcm_rec[0].pcm = info;
2674 info->pcm_type = HDA_PCM_TYPE_HDMI;
2675 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2676 *pstr = spec->pcm_playback;
2677 pstr->nid = per_cvt->cvt_nid;
2678 if (pstr->channels_max <= 2 && chans && chans <= 16)
2679 pstr->channels_max = chans;
2684 /* unsolicited event for jack sensing */
2685 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2688 snd_hda_jack_set_dirty_all(codec);
2689 snd_hda_jack_report_sync(codec);
2692 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2693 * as long as spec->pins[] is set correctly
2695 #define simple_hdmi_build_jack generic_hdmi_build_jack
2697 static int simple_playback_build_controls(struct hda_codec *codec)
2699 struct hdmi_spec *spec = codec->spec;
2700 struct hdmi_spec_per_cvt *per_cvt;
2703 per_cvt = get_cvt(spec, 0);
2704 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2709 return simple_hdmi_build_jack(codec, 0);
2712 static int simple_playback_init(struct hda_codec *codec)
2714 struct hdmi_spec *spec = codec->spec;
2715 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2716 hda_nid_t pin = per_pin->pin_nid;
2718 snd_hda_codec_write(codec, pin, 0,
2719 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2720 /* some codecs require to unmute the pin */
2721 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2722 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2724 snd_hda_jack_detect_enable(codec, pin);
2728 static void simple_playback_free(struct hda_codec *codec)
2730 struct hdmi_spec *spec = codec->spec;
2732 hdmi_array_free(spec);
2737 * Nvidia specific implementations
2740 #define Nv_VERB_SET_Channel_Allocation 0xF79
2741 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2742 #define Nv_VERB_SET_Audio_Protection_On 0xF98
2743 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
2745 #define nvhdmi_master_con_nid_7x 0x04
2746 #define nvhdmi_master_pin_nid_7x 0x05
2748 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2749 /*front, rear, clfe, rear_surr */
2753 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2754 /* set audio protect on */
2755 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2756 /* enable digital output on pin widget */
2757 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2761 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2762 /* set audio protect on */
2763 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2764 /* enable digital output on pin widget */
2765 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2766 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2767 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2768 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2769 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2773 #ifdef LIMITED_RATE_FMT_SUPPORT
2774 /* support only the safe format and rate */
2775 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2776 #define SUPPORTED_MAXBPS 16
2777 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2779 /* support all rates and formats */
2780 #define SUPPORTED_RATES \
2781 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2782 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2783 SNDRV_PCM_RATE_192000)
2784 #define SUPPORTED_MAXBPS 24
2785 #define SUPPORTED_FORMATS \
2786 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2789 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2791 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2795 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2797 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2801 static const unsigned int channels_2_6_8[] = {
2805 static const unsigned int channels_2_8[] = {
2809 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2810 .count = ARRAY_SIZE(channels_2_6_8),
2811 .list = channels_2_6_8,
2815 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2816 .count = ARRAY_SIZE(channels_2_8),
2817 .list = channels_2_8,
2821 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2822 struct hda_codec *codec,
2823 struct snd_pcm_substream *substream)
2825 struct hdmi_spec *spec = codec->spec;
2826 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2828 switch (codec->preset->vendor_id) {
2833 hw_constraints_channels = &hw_constraints_2_8_channels;
2836 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2842 if (hw_constraints_channels != NULL) {
2843 snd_pcm_hw_constraint_list(substream->runtime, 0,
2844 SNDRV_PCM_HW_PARAM_CHANNELS,
2845 hw_constraints_channels);
2847 snd_pcm_hw_constraint_step(substream->runtime, 0,
2848 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2851 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2854 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2855 struct hda_codec *codec,
2856 struct snd_pcm_substream *substream)
2858 struct hdmi_spec *spec = codec->spec;
2859 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2862 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2863 struct hda_codec *codec,
2864 unsigned int stream_tag,
2865 unsigned int format,
2866 struct snd_pcm_substream *substream)
2868 struct hdmi_spec *spec = codec->spec;
2869 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2870 stream_tag, format, substream);
2873 static const struct hda_pcm_stream simple_pcm_playback = {
2878 .open = simple_playback_pcm_open,
2879 .close = simple_playback_pcm_close,
2880 .prepare = simple_playback_pcm_prepare
2884 static const struct hda_codec_ops simple_hdmi_patch_ops = {
2885 .build_controls = simple_playback_build_controls,
2886 .build_pcms = simple_playback_build_pcms,
2887 .init = simple_playback_init,
2888 .free = simple_playback_free,
2889 .unsol_event = simple_hdmi_unsol_event,
2892 static int patch_simple_hdmi(struct hda_codec *codec,
2893 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2895 struct hdmi_spec *spec;
2896 struct hdmi_spec_per_cvt *per_cvt;
2897 struct hdmi_spec_per_pin *per_pin;
2899 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2904 hdmi_array_init(spec, 1);
2906 spec->multiout.num_dacs = 0; /* no analog */
2907 spec->multiout.max_channels = 2;
2908 spec->multiout.dig_out_nid = cvt_nid;
2911 per_pin = snd_array_new(&spec->pins);
2912 per_cvt = snd_array_new(&spec->cvts);
2913 if (!per_pin || !per_cvt) {
2914 simple_playback_free(codec);
2917 per_cvt->cvt_nid = cvt_nid;
2918 per_pin->pin_nid = pin_nid;
2919 spec->pcm_playback = simple_pcm_playback;
2921 codec->patch_ops = simple_hdmi_patch_ops;
2926 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2929 unsigned int chanmask;
2930 int chan = channels ? (channels - 1) : 1;
2949 /* Set the audio infoframe channel allocation and checksum fields. The
2950 * channel count is computed implicitly by the hardware. */
2951 snd_hda_codec_write(codec, 0x1, 0,
2952 Nv_VERB_SET_Channel_Allocation, chanmask);
2954 snd_hda_codec_write(codec, 0x1, 0,
2955 Nv_VERB_SET_Info_Frame_Checksum,
2956 (0x71 - chan - chanmask));
2959 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2960 struct hda_codec *codec,
2961 struct snd_pcm_substream *substream)
2963 struct hdmi_spec *spec = codec->spec;
2966 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2967 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2968 for (i = 0; i < 4; i++) {
2969 /* set the stream id */
2970 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2971 AC_VERB_SET_CHANNEL_STREAMID, 0);
2972 /* set the stream format */
2973 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2974 AC_VERB_SET_STREAM_FORMAT, 0);
2977 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2978 * streams are disabled. */
2979 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2981 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2984 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2985 struct hda_codec *codec,
2986 unsigned int stream_tag,
2987 unsigned int format,
2988 struct snd_pcm_substream *substream)
2991 unsigned int dataDCC2, channel_id;
2993 struct hdmi_spec *spec = codec->spec;
2994 struct hda_spdif_out *spdif;
2995 struct hdmi_spec_per_cvt *per_cvt;
2997 mutex_lock(&codec->spdif_mutex);
2998 per_cvt = get_cvt(spec, 0);
2999 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
3001 chs = substream->runtime->channels;
3005 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
3006 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
3007 snd_hda_codec_write(codec,
3008 nvhdmi_master_con_nid_7x,
3010 AC_VERB_SET_DIGI_CONVERT_1,
3011 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3013 /* set the stream id */
3014 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3015 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3017 /* set the stream format */
3018 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3019 AC_VERB_SET_STREAM_FORMAT, format);
3021 /* turn on again (if needed) */
3022 /* enable and set the channel status audio/data flag */
3023 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
3024 snd_hda_codec_write(codec,
3025 nvhdmi_master_con_nid_7x,
3027 AC_VERB_SET_DIGI_CONVERT_1,
3028 spdif->ctls & 0xff);
3029 snd_hda_codec_write(codec,
3030 nvhdmi_master_con_nid_7x,
3032 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3035 for (i = 0; i < 4; i++) {
3041 /* turn off SPDIF once;
3042 *otherwise the IEC958 bits won't be updated
3044 if (codec->spdif_status_reset &&
3045 (spdif->ctls & AC_DIG1_ENABLE))
3046 snd_hda_codec_write(codec,
3047 nvhdmi_con_nids_7x[i],
3049 AC_VERB_SET_DIGI_CONVERT_1,
3050 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3051 /* set the stream id */
3052 snd_hda_codec_write(codec,
3053 nvhdmi_con_nids_7x[i],
3055 AC_VERB_SET_CHANNEL_STREAMID,
3056 (stream_tag << 4) | channel_id);
3057 /* set the stream format */
3058 snd_hda_codec_write(codec,
3059 nvhdmi_con_nids_7x[i],
3061 AC_VERB_SET_STREAM_FORMAT,
3063 /* turn on again (if needed) */
3064 /* enable and set the channel status audio/data flag */
3065 if (codec->spdif_status_reset &&
3066 (spdif->ctls & AC_DIG1_ENABLE)) {
3067 snd_hda_codec_write(codec,
3068 nvhdmi_con_nids_7x[i],
3070 AC_VERB_SET_DIGI_CONVERT_1,
3071 spdif->ctls & 0xff);
3072 snd_hda_codec_write(codec,
3073 nvhdmi_con_nids_7x[i],
3075 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3079 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
3081 mutex_unlock(&codec->spdif_mutex);
3085 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
3089 .nid = nvhdmi_master_con_nid_7x,
3090 .rates = SUPPORTED_RATES,
3091 .maxbps = SUPPORTED_MAXBPS,
3092 .formats = SUPPORTED_FORMATS,
3094 .open = simple_playback_pcm_open,
3095 .close = nvhdmi_8ch_7x_pcm_close,
3096 .prepare = nvhdmi_8ch_7x_pcm_prepare
3100 static int patch_nvhdmi_2ch(struct hda_codec *codec)
3102 struct hdmi_spec *spec;
3103 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3104 nvhdmi_master_pin_nid_7x);
3108 codec->patch_ops.init = nvhdmi_7x_init_2ch;
3109 /* override the PCM rates, etc, as the codec doesn't give full list */
3111 spec->pcm_playback.rates = SUPPORTED_RATES;
3112 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3113 spec->pcm_playback.formats = SUPPORTED_FORMATS;
3117 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3119 struct hdmi_spec *spec = codec->spec;
3120 int err = simple_playback_build_pcms(codec);
3122 struct hda_pcm *info = get_pcm_rec(spec, 0);
3123 info->own_chmap = true;
3128 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3130 struct hdmi_spec *spec = codec->spec;
3131 struct hda_pcm *info;
3132 struct snd_pcm_chmap *chmap;
3135 err = simple_playback_build_controls(codec);
3139 /* add channel maps */
3140 info = get_pcm_rec(spec, 0);
3141 err = snd_pcm_add_chmap_ctls(info->pcm,
3142 SNDRV_PCM_STREAM_PLAYBACK,
3143 snd_pcm_alt_chmaps, 8, 0, &chmap);
3146 switch (codec->preset->vendor_id) {
3151 chmap->channel_mask = (1U << 2) | (1U << 8);
3154 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3159 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3161 struct hdmi_spec *spec;
3162 int err = patch_nvhdmi_2ch(codec);
3166 spec->multiout.max_channels = 8;
3167 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3168 codec->patch_ops.init = nvhdmi_7x_init_8ch;
3169 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3170 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3172 /* Initialize the audio infoframe channel mask and checksum to something
3174 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3180 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3184 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3185 struct hdac_cea_channel_speaker_allocation *cap, int channels)
3187 if (cap->ca_index == 0x00 && channels == 2)
3188 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3190 /* If the speaker allocation matches the channel count, it is OK. */
3191 if (cap->channels != channels)
3194 /* all channels are remappable freely */
3195 return SNDRV_CTL_TLVT_CHMAP_VAR;
3198 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3199 int ca, int chs, unsigned char *map)
3201 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3207 static int patch_nvhdmi(struct hda_codec *codec)
3209 struct hdmi_spec *spec;
3212 err = patch_generic_hdmi(codec);
3217 spec->dyn_pin_out = true;
3219 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3220 nvhdmi_chmap_cea_alloc_validate_get_type;
3221 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3227 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3228 * accessed using vendor-defined verbs. These registers can be used for
3229 * interoperability between the HDA and HDMI drivers.
3232 /* Audio Function Group node */
3233 #define NVIDIA_AFG_NID 0x01
3236 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3237 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3238 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3239 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3240 * additional bit (at position 30) to signal the validity of the format.
3242 * | 31 | 30 | 29 16 | 15 0 |
3243 * +---------+-------+--------+--------+
3244 * | TRIGGER | VALID | UNUSED | FORMAT |
3245 * +-----------------------------------|
3247 * Note that for the trigger bit to take effect it needs to change value
3248 * (i.e. it needs to be toggled).
3250 #define NVIDIA_GET_SCRATCH0 0xfa6
3251 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3252 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3253 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3254 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3255 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3256 #define NVIDIA_SCRATCH_VALID (1 << 6)
3258 #define NVIDIA_GET_SCRATCH1 0xfab
3259 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3260 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3261 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3262 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3265 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3266 * the format is invalidated so that the HDMI codec can be disabled.
3268 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3272 /* bits [31:30] contain the trigger and valid bits */
3273 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3274 NVIDIA_GET_SCRATCH0, 0);
3275 value = (value >> 24) & 0xff;
3277 /* bits [15:0] are used to store the HDA format */
3278 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3279 NVIDIA_SET_SCRATCH0_BYTE0,
3280 (format >> 0) & 0xff);
3281 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3282 NVIDIA_SET_SCRATCH0_BYTE1,
3283 (format >> 8) & 0xff);
3285 /* bits [16:24] are unused */
3286 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3287 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3290 * Bit 30 signals that the data is valid and hence that HDMI audio can
3294 value &= ~NVIDIA_SCRATCH_VALID;
3296 value |= NVIDIA_SCRATCH_VALID;
3299 * Whenever the trigger bit is toggled, an interrupt is raised in the
3300 * HDMI codec. The HDMI driver will use that as trigger to update its
3303 value ^= NVIDIA_SCRATCH_TRIGGER;
3305 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3306 NVIDIA_SET_SCRATCH0_BYTE3, value);
3309 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3310 struct hda_codec *codec,
3311 unsigned int stream_tag,
3312 unsigned int format,
3313 struct snd_pcm_substream *substream)
3317 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3322 /* notify the HDMI codec of the format change */
3323 tegra_hdmi_set_format(codec, format);
3328 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3329 struct hda_codec *codec,
3330 struct snd_pcm_substream *substream)
3332 /* invalidate the format in the HDMI codec */
3333 tegra_hdmi_set_format(codec, 0);
3335 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3338 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3340 struct hdmi_spec *spec = codec->spec;
3343 for (i = 0; i < spec->num_pins; i++) {
3344 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3346 if (pcm->pcm_type == type)
3353 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3355 struct hda_pcm_stream *stream;
3356 struct hda_pcm *pcm;
3359 err = generic_hdmi_build_pcms(codec);
3363 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3368 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3369 * codec about format changes.
3371 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3372 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3373 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3378 static int patch_tegra_hdmi(struct hda_codec *codec)
3382 err = patch_generic_hdmi(codec);
3386 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3392 * ATI/AMD-specific implementations
3395 #define is_amdhdmi_rev3_or_later(codec) \
3396 ((codec)->core.vendor_id == 0x1002aa01 && \
3397 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3398 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3400 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3401 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3402 #define ATI_VERB_SET_DOWNMIX_INFO 0x772
3403 #define ATI_VERB_SET_MULTICHANNEL_01 0x777
3404 #define ATI_VERB_SET_MULTICHANNEL_23 0x778
3405 #define ATI_VERB_SET_MULTICHANNEL_45 0x779
3406 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
3407 #define ATI_VERB_SET_HBR_CONTROL 0x77c
3408 #define ATI_VERB_SET_MULTICHANNEL_1 0x785
3409 #define ATI_VERB_SET_MULTICHANNEL_3 0x786
3410 #define ATI_VERB_SET_MULTICHANNEL_5 0x787
3411 #define ATI_VERB_SET_MULTICHANNEL_7 0x788
3412 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3413 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3414 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3415 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3416 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3417 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3418 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
3419 #define ATI_VERB_GET_HBR_CONTROL 0xf7c
3420 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3421 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3422 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3423 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3424 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3426 /* AMD specific HDA cvt verbs */
3427 #define ATI_VERB_SET_RAMP_RATE 0x770
3428 #define ATI_VERB_GET_RAMP_RATE 0xf70
3430 #define ATI_OUT_ENABLE 0x1
3432 #define ATI_MULTICHANNEL_MODE_PAIRED 0
3433 #define ATI_MULTICHANNEL_MODE_SINGLE 1
3435 #define ATI_HBR_CAPABLE 0x01
3436 #define ATI_HBR_ENABLE 0x10
3438 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3439 unsigned char *buf, int *eld_size)
3441 /* call hda_eld.c ATI/AMD-specific function */
3442 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3443 is_amdhdmi_rev3_or_later(codec));
3446 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3447 int active_channels, int conn_type)
3449 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3452 static int atihdmi_paired_swap_fc_lfe(int pos)
3455 * ATI/AMD have automatic FC/LFE swap built-in
3456 * when in pairwise mapping mode.
3460 /* see channel_allocations[].speakers[] */
3469 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3470 int ca, int chs, unsigned char *map)
3472 struct hdac_cea_channel_speaker_allocation *cap;
3475 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3477 cap = snd_hdac_get_ch_alloc_from_ca(ca);
3478 for (i = 0; i < chs; ++i) {
3479 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
3481 bool companion_ok = false;
3486 for (j = 0 + i % 2; j < 8; j += 2) {
3487 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3488 if (cap->speakers[chan_idx] == mask) {
3489 /* channel is in a supported position */
3492 if (i % 2 == 0 && i + 1 < chs) {
3493 /* even channel, check the odd companion */
3494 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3495 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
3496 int comp_mask_act = cap->speakers[comp_chan_idx];
3498 if (comp_mask_req == comp_mask_act)
3499 companion_ok = true;
3511 i++; /* companion channel already checked */
3517 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3518 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
3520 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3522 int ati_channel_setup = 0;
3527 if (!has_amd_full_remap_support(codec)) {
3528 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3530 /* In case this is an odd slot but without stream channel, do not
3531 * disable the slot since the corresponding even slot could have a
3532 * channel. In case neither have a channel, the slot pair will be
3533 * disabled when this function is called for the even slot. */
3534 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3537 hdmi_slot -= hdmi_slot % 2;
3539 if (stream_channel != 0xf)
3540 stream_channel -= stream_channel % 2;
3543 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3545 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3547 if (stream_channel != 0xf)
3548 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3550 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3553 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3554 hda_nid_t pin_nid, int asp_slot)
3556 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3557 bool was_odd = false;
3558 int ati_asp_slot = asp_slot;
3560 int ati_channel_setup;
3565 if (!has_amd_full_remap_support(codec)) {
3566 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3567 if (ati_asp_slot % 2 != 0) {
3573 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3575 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3577 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3580 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3583 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3584 struct hdac_chmap *chmap,
3585 struct hdac_cea_channel_speaker_allocation *cap,
3591 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3592 * we need to take that into account (a single channel may take 2
3593 * channel slots if we need to carry a silent channel next to it).
3594 * On Rev3+ AMD codecs this function is not used.
3598 /* We only produce even-numbered channel count TLVs */
3599 if ((channels % 2) != 0)
3602 for (c = 0; c < 7; c += 2) {
3603 if (cap->speakers[c] || cap->speakers[c+1])
3607 if (chanpairs * 2 != channels)
3610 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3613 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
3614 struct hdac_cea_channel_speaker_allocation *cap,
3615 unsigned int *chmap, int channels)
3617 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3621 for (c = 7; c >= 0; c--) {
3622 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3623 int spk = cap->speakers[chan];
3625 /* add N/A channel if the companion channel is occupied */
3626 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3627 chmap[count++] = SNDRV_CHMAP_NA;
3632 chmap[count++] = snd_hdac_spk_to_chmap(spk);
3635 WARN_ON(count != channels);
3638 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3641 int hbr_ctl, hbr_ctl_new;
3643 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3644 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3646 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3648 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3651 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3653 hbr_ctl == hbr_ctl_new ? "" : "new-",
3656 if (hbr_ctl != hbr_ctl_new)
3657 snd_hda_codec_write(codec, pin_nid, 0,
3658 ATI_VERB_SET_HBR_CONTROL,
3667 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3668 hda_nid_t pin_nid, u32 stream_tag, int format)
3671 if (is_amdhdmi_rev3_or_later(codec)) {
3672 int ramp_rate = 180; /* default as per AMD spec */
3673 /* disable ramp-up/down for non-pcm as per AMD spec */
3674 if (format & AC_FMT_TYPE_NON_PCM)
3677 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3680 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3684 static int atihdmi_init(struct hda_codec *codec)
3686 struct hdmi_spec *spec = codec->spec;
3689 err = generic_hdmi_init(codec);
3694 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3695 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3697 /* make sure downmix information in infoframe is zero */
3698 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3700 /* enable channel-wise remap mode if supported */
3701 if (has_amd_full_remap_support(codec))
3702 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3703 ATI_VERB_SET_MULTICHANNEL_MODE,
3704 ATI_MULTICHANNEL_MODE_SINGLE);
3710 static int patch_atihdmi(struct hda_codec *codec)
3712 struct hdmi_spec *spec;
3713 struct hdmi_spec_per_cvt *per_cvt;
3716 err = patch_generic_hdmi(codec);
3721 codec->patch_ops.init = atihdmi_init;
3725 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3726 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3727 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3728 spec->ops.setup_stream = atihdmi_setup_stream;
3730 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3731 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3733 if (!has_amd_full_remap_support(codec)) {
3734 /* override to ATI/AMD-specific versions with pairwise mapping */
3735 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3736 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3737 spec->chmap.ops.cea_alloc_to_tlv_chmap =
3738 atihdmi_paired_cea_alloc_to_tlv_chmap;
3739 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
3742 /* ATI/AMD converters do not advertise all of their capabilities */
3743 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3744 per_cvt = get_cvt(spec, cvt_idx);
3745 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3746 per_cvt->rates |= SUPPORTED_RATES;
3747 per_cvt->formats |= SUPPORTED_FORMATS;
3748 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3751 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
3753 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing
3754 * the link-down as is. Tell the core to allow it.
3756 codec->link_down_at_suspend = 1;
3761 /* VIA HDMI Implementation */
3762 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3763 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3765 static int patch_via_hdmi(struct hda_codec *codec)
3767 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3773 static const struct hda_device_id snd_hda_id_hdmi[] = {
3774 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
3775 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
3776 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
3777 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
3778 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
3779 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
3780 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
3781 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch),
3782 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3783 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3784 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x),
3785 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3786 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3787 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
3788 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi),
3789 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi),
3790 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
3791 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
3792 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
3793 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
3794 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
3795 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
3796 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
3797 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
3798 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
3799 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
3800 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
3801 /* 17 is known to be absent */
3802 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
3803 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
3804 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
3805 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
3806 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
3807 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
3808 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
3809 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
3810 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
3811 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
3812 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
3813 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
3814 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
3815 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
3816 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi),
3817 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi),
3818 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
3819 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi),
3820 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
3821 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi),
3822 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi),
3823 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
3824 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
3825 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
3826 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
3827 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi),
3828 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi),
3829 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi),
3830 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi),
3831 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi),
3832 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
3833 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi),
3834 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi),
3835 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi),
3836 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
3837 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
3838 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi),
3839 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi),
3840 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi),
3841 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi),
3842 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi),
3843 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi),
3844 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi),
3845 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),
3846 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi),
3847 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi),
3848 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
3849 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch),
3850 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
3851 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
3852 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
3853 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
3854 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
3855 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
3856 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
3857 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
3858 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
3859 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
3860 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
3861 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
3862 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
3863 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
3864 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
3865 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
3866 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi),
3867 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi),
3868 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi),
3869 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
3870 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
3871 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
3872 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
3873 /* special ID for generic HDMI */
3874 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
3877 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
3879 MODULE_LICENSE("GPL");
3880 MODULE_DESCRIPTION("HDMI HD-audio codec");
3881 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3882 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3883 MODULE_ALIAS("snd-hda-codec-atihdmi");
3885 static struct hda_codec_driver hdmi_driver = {
3886 .id = snd_hda_id_hdmi,
3889 module_hda_codec_driver(hdmi_driver);