3 * hda_intel.c - Implementation of primary alsa driver code base
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
48 #include <linux/pm_runtime.h>
49 #include <linux/clocksource.h>
50 #include <linux/time.h>
51 #include <linux/completion.h>
54 /* for snoop control */
55 #include <asm/pgtable.h>
56 #include <asm/cacheflush.h>
57 #include <asm/cpufeature.h>
59 #include <sound/core.h>
60 #include <sound/initval.h>
61 #include <sound/hdaudio.h>
62 #include <sound/hda_i915.h>
63 #include <linux/vgaarb.h>
64 #include <linux/vga_switcheroo.h>
65 #include <linux/firmware.h>
66 #include "hda_codec.h"
67 #include "hda_controller.h"
68 #include "hda_intel.h"
70 #define CREATE_TRACE_POINTS
71 #include "hda_intel_trace.h"
73 /* position fix mode */
83 /* Defines for ATI HD Audio support in SB450 south bridge */
84 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
85 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
87 /* Defines for Nvidia HDA support */
88 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
89 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
90 #define NVIDIA_HDA_ISTRM_COH 0x4d
91 #define NVIDIA_HDA_OSTRM_COH 0x4c
92 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
94 /* Defines for Intel SCH HDA snoop control */
95 #define INTEL_HDA_CGCTL 0x48
96 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6)
97 #define INTEL_SCH_HDA_DEVC 0x78
98 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
100 /* Define IN stream 0 FIFO size offset in VIA controller */
101 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
102 /* Define VIA HD Audio Device ID*/
103 #define VIA_HDAC_DEVICE_ID 0x3288
105 /* max number of SDs */
106 /* ICH, ATI and VIA have 4 playback and 4 capture */
107 #define ICH6_NUM_CAPTURE 4
108 #define ICH6_NUM_PLAYBACK 4
110 /* ULI has 6 playback and 5 capture */
111 #define ULI_NUM_CAPTURE 5
112 #define ULI_NUM_PLAYBACK 6
114 /* ATI HDMI may have up to 8 playbacks and 0 capture */
115 #define ATIHDMI_NUM_CAPTURE 0
116 #define ATIHDMI_NUM_PLAYBACK 8
118 /* TERA has 4 playback and 3 capture */
119 #define TERA_NUM_CAPTURE 3
120 #define TERA_NUM_PLAYBACK 4
123 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
124 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
125 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
126 static char *model[SNDRV_CARDS];
127 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
128 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
129 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
130 static int probe_only[SNDRV_CARDS];
131 static int jackpoll_ms[SNDRV_CARDS];
132 static int single_cmd = -1;
133 static int enable_msi = -1;
134 #ifdef CONFIG_SND_HDA_PATCH_LOADER
135 static char *patch[SNDRV_CARDS];
137 #ifdef CONFIG_SND_HDA_INPUT_BEEP
138 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
139 CONFIG_SND_HDA_INPUT_BEEP_MODE};
142 module_param_array(index, int, NULL, 0444);
143 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
144 module_param_array(id, charp, NULL, 0444);
145 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
146 module_param_array(enable, bool, NULL, 0444);
147 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
148 module_param_array(model, charp, NULL, 0444);
149 MODULE_PARM_DESC(model, "Use the given board model.");
150 module_param_array(position_fix, int, NULL, 0444);
151 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
152 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+).");
153 module_param_array(bdl_pos_adj, int, NULL, 0644);
154 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
155 module_param_array(probe_mask, int, NULL, 0444);
156 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
157 module_param_array(probe_only, int, NULL, 0444);
158 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
159 module_param_array(jackpoll_ms, int, NULL, 0444);
160 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
161 module_param(single_cmd, bint, 0444);
162 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
163 "(for debugging only).");
164 module_param(enable_msi, bint, 0444);
165 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
166 #ifdef CONFIG_SND_HDA_PATCH_LOADER
167 module_param_array(patch, charp, NULL, 0444);
168 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
170 #ifdef CONFIG_SND_HDA_INPUT_BEEP
171 module_param_array(beep_mode, bool, NULL, 0444);
172 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
173 "(0=off, 1=on) (default=1).");
177 static int param_set_xint(const char *val, const struct kernel_param *kp);
178 static const struct kernel_param_ops param_ops_xint = {
179 .set = param_set_xint,
180 .get = param_get_int,
182 #define param_check_xint param_check_int
184 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
185 module_param(power_save, xint, 0644);
186 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
187 "(in second, 0 = disable).");
189 /* reset the HD-audio controller in power save mode.
190 * this may give more power-saving, but will take longer time to
193 static bool power_save_controller = 1;
194 module_param(power_save_controller, bool, 0644);
195 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
198 #endif /* CONFIG_PM */
200 static int align_buffer_size = -1;
201 module_param(align_buffer_size, bint, 0644);
202 MODULE_PARM_DESC(align_buffer_size,
203 "Force buffer and period sizes to be multiple of 128 bytes.");
206 static int hda_snoop = -1;
207 module_param_named(snoop, hda_snoop, bint, 0444);
208 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
210 #define hda_snoop true
214 MODULE_LICENSE("GPL");
215 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
249 MODULE_DESCRIPTION("Intel HDA driver");
251 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
252 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
253 #define SUPPORT_VGA_SWITCHEROO
269 AZX_DRIVER_ATIHDMI_NS,
279 AZX_NUM_DRIVERS, /* keep this as last entry */
282 #define azx_get_snoop_type(chip) \
283 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10)
284 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10)
286 /* quirks for old Intel chipsets */
287 #define AZX_DCAPS_INTEL_ICH \
288 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE)
290 /* quirks for Intel PCH */
291 #define AZX_DCAPS_INTEL_PCH_BASE \
292 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\
293 AZX_DCAPS_SNOOP_TYPE(SCH))
295 /* PCH up to IVB; no runtime PM */
296 #define AZX_DCAPS_INTEL_PCH_NOPM \
297 (AZX_DCAPS_INTEL_PCH_BASE)
299 /* PCH for HSW/BDW; with runtime PM */
300 #define AZX_DCAPS_INTEL_PCH \
301 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME)
304 #define AZX_DCAPS_INTEL_HASWELL \
305 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\
306 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
307 AZX_DCAPS_SNOOP_TYPE(SCH))
309 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */
310 #define AZX_DCAPS_INTEL_BROADWELL \
311 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\
312 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_POWERWELL |\
313 AZX_DCAPS_SNOOP_TYPE(SCH))
315 #define AZX_DCAPS_INTEL_BAYTRAIL \
316 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_I915_POWERWELL)
318 #define AZX_DCAPS_INTEL_BRASWELL \
319 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_I915_POWERWELL)
321 #define AZX_DCAPS_INTEL_SKYLAKE \
322 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
323 AZX_DCAPS_I915_POWERWELL)
325 #define AZX_DCAPS_INTEL_BROXTON \
326 (AZX_DCAPS_INTEL_PCH | AZX_DCAPS_SEPARATE_STREAM_TAG |\
327 AZX_DCAPS_I915_POWERWELL)
329 /* quirks for ATI SB / AMD Hudson */
330 #define AZX_DCAPS_PRESET_ATI_SB \
331 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB |\
332 AZX_DCAPS_SNOOP_TYPE(ATI))
334 /* quirks for ATI/AMD HDMI */
335 #define AZX_DCAPS_PRESET_ATI_HDMI \
336 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB|\
339 /* quirks for ATI HDMI with snoop off */
340 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \
341 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF)
343 /* quirks for Nvidia */
344 #define AZX_DCAPS_PRESET_NVIDIA \
345 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\
346 AZX_DCAPS_SNOOP_TYPE(NVIDIA))
348 #define AZX_DCAPS_PRESET_CTHDA \
349 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\
350 AZX_DCAPS_NO_64BIT |\
351 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF)
354 * vga_switcheroo support
356 #ifdef SUPPORT_VGA_SWITCHEROO
357 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
359 #define use_vga_switcheroo(chip) 0
362 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \
363 ((pci)->device == 0x0c0c) || \
364 ((pci)->device == 0x0d0c) || \
365 ((pci)->device == 0x160c))
367 #define IS_SKL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa170)
368 #define IS_SKL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d70)
369 #define IS_KBL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa171)
370 #define IS_KBL_LP(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x9d71)
371 #define IS_KBL_H(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa2f0)
372 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)
373 #define IS_GLK(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x3198)
374 #define IS_SKL_PLUS(pci) (IS_SKL(pci) || IS_SKL_LP(pci) || IS_BXT(pci)) || \
375 IS_KBL(pci) || IS_KBL_LP(pci) || IS_KBL_H(pci) || \
378 static char *driver_short_names[] = {
379 [AZX_DRIVER_ICH] = "HDA Intel",
380 [AZX_DRIVER_PCH] = "HDA Intel PCH",
381 [AZX_DRIVER_SCH] = "HDA Intel MID",
382 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
383 [AZX_DRIVER_ATI] = "HDA ATI SB",
384 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
385 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
386 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
387 [AZX_DRIVER_SIS] = "HDA SIS966",
388 [AZX_DRIVER_ULI] = "HDA ULI M5461",
389 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
390 [AZX_DRIVER_TERA] = "HDA Teradici",
391 [AZX_DRIVER_CTX] = "HDA Creative",
392 [AZX_DRIVER_CTHDA] = "HDA Creative",
393 [AZX_DRIVER_CMEDIA] = "HDA C-Media",
394 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
398 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
404 if (!dmab || !dmab->area || !dmab->bytes)
407 #ifdef CONFIG_SND_DMA_SGBUF
408 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
409 struct snd_sg_buf *sgbuf = dmab->private_data;
410 if (chip->driver_type == AZX_DRIVER_CMEDIA)
411 return; /* deal with only CORB/RIRB buffers */
413 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
415 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
420 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
422 set_memory_wc((unsigned long)dmab->area, pages);
424 set_memory_wb((unsigned long)dmab->area, pages);
427 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
430 __mark_pages_wc(chip, buf, on);
432 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
433 struct snd_pcm_substream *substream, bool on)
435 if (azx_dev->wc_marked != on) {
436 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
437 azx_dev->wc_marked = on;
441 /* NOP for other archs */
442 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
446 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
447 struct snd_pcm_substream *substream, bool on)
452 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
455 * initialize the PCI registers
457 /* update bits in a PCI register byte */
458 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
459 unsigned char mask, unsigned char val)
463 pci_read_config_byte(pci, reg, &data);
465 data |= (val & mask);
466 pci_write_config_byte(pci, reg, data);
469 static void azx_init_pci(struct azx *chip)
471 int snoop_type = azx_get_snoop_type(chip);
473 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
474 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
475 * Ensuring these bits are 0 clears playback static on some HD Audio
477 * The PCI register TCSEL is defined in the Intel manuals.
479 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
480 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
481 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0);
484 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
485 * we need to enable snoop.
487 if (snoop_type == AZX_SNOOP_TYPE_ATI) {
488 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
490 update_pci_byte(chip->pci,
491 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
492 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
495 /* For NVIDIA HDA, enable snoop */
496 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) {
497 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
499 update_pci_byte(chip->pci,
500 NVIDIA_HDA_TRANSREG_ADDR,
501 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
502 update_pci_byte(chip->pci,
503 NVIDIA_HDA_ISTRM_COH,
504 0x01, NVIDIA_HDA_ENABLE_COHBIT);
505 update_pci_byte(chip->pci,
506 NVIDIA_HDA_OSTRM_COH,
507 0x01, NVIDIA_HDA_ENABLE_COHBIT);
510 /* Enable SCH/PCH snoop if needed */
511 if (snoop_type == AZX_SNOOP_TYPE_SCH) {
512 unsigned short snoop;
513 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
514 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
515 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
516 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
517 if (!azx_snoop(chip))
518 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
519 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
520 pci_read_config_word(chip->pci,
521 INTEL_SCH_HDA_DEVC, &snoop);
523 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
524 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
525 "Disabled" : "Enabled");
530 * In BXT-P A0, HD-Audio DMA requests is later than expected,
531 * and makes an audio stream sensitive to system latencies when
532 * 24/32 bits are playing.
533 * Adjusting threshold of DMA fifo to force the DMA request
534 * sooner to improve latency tolerance at the expense of power.
536 static void bxt_reduce_dma_latency(struct azx *chip)
540 val = azx_readl(chip, VS_EM4L);
542 azx_writel(chip, VS_EM4L, val);
547 * bit 0: 6 MHz Supported
548 * bit 1: 12 MHz Supported
549 * bit 2: 24 MHz Supported
550 * bit 3: 48 MHz Supported
551 * bit 4: 96 MHz Supported
552 * bit 5: 192 MHz Supported
554 static int intel_get_lctl_scf(struct azx *chip)
556 struct hdac_bus *bus = azx_bus(chip);
557 static int preferred_bits[] = { 2, 3, 1, 4, 5 };
561 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP);
563 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) {
564 t = preferred_bits[i];
569 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz");
573 static int intel_ml_lctl_set_power(struct azx *chip, int state)
575 struct hdac_bus *bus = azx_bus(chip);
580 * the codecs are sharing the first link setting by default
581 * If other links are enabled for stream, they need similar fix
583 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
584 val &= ~AZX_MLCTL_SPA;
585 val |= state << AZX_MLCTL_SPA_SHIFT;
586 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
590 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) &
591 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT))
600 static void intel_init_lctl(struct azx *chip)
602 struct hdac_bus *bus = azx_bus(chip);
606 /* 0. check lctl register value is correct or not */
607 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
608 /* if SCF is already set, let's use it */
609 if ((val & ML_LCTL_SCF_MASK) != 0)
613 * Before operating on SPA, CPA must match SPA.
614 * Any deviation may result in undefined behavior.
616 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) !=
617 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT))
620 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */
621 ret = intel_ml_lctl_set_power(chip, 0);
626 /* 2. update SCF to select a properly audio clock*/
627 val &= ~ML_LCTL_SCF_MASK;
628 val |= intel_get_lctl_scf(chip);
629 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL);
632 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */
633 intel_ml_lctl_set_power(chip, 1);
637 static void hda_intel_init_chip(struct azx *chip, bool full_reset)
639 struct hdac_bus *bus = azx_bus(chip);
640 struct pci_dev *pci = chip->pci;
643 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
644 snd_hdac_set_codec_wakeup(bus, true);
645 if (IS_SKL_PLUS(pci)) {
646 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
647 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
648 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
650 azx_init_chip(chip, full_reset);
651 if (IS_SKL_PLUS(pci)) {
652 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
653 val = val | INTEL_HDA_CGCTL_MISCBDCGE;
654 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
656 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
657 snd_hdac_set_codec_wakeup(bus, false);
659 /* reduce dma latency to avoid noise */
661 bxt_reduce_dma_latency(chip);
663 if (bus->mlcap != NULL)
664 intel_init_lctl(chip);
667 /* calculate runtime delay from LPIB */
668 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev,
671 struct snd_pcm_substream *substream = azx_dev->core.substream;
672 int stream = substream->stream;
673 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev);
676 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
677 delay = pos - lpib_pos;
679 delay = lpib_pos - pos;
681 if (delay >= azx_dev->core.delay_negative_threshold)
684 delay += azx_dev->core.bufsize;
687 if (delay >= azx_dev->core.period_bytes) {
688 dev_info(chip->card->dev,
689 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
690 delay, azx_dev->core.period_bytes);
692 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
693 chip->get_delay[stream] = NULL;
696 return bytes_to_frames(substream->runtime, delay);
699 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
701 /* called from IRQ */
702 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev)
704 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
707 ok = azx_position_ok(chip, azx_dev);
709 azx_dev->irq_pending = 0;
711 } else if (ok == 0) {
712 /* bogus IRQ, process it later */
713 azx_dev->irq_pending = 1;
714 schedule_work(&hda->irq_pending_work);
719 /* Enable/disable i915 display power for the link */
720 static int azx_intel_link_power(struct azx *chip, bool enable)
722 struct hdac_bus *bus = azx_bus(chip);
724 return snd_hdac_display_power(bus, enable);
728 * Check whether the current DMA position is acceptable for updating
729 * periods. Returns non-zero if it's OK.
731 * Many HD-audio controllers appear pretty inaccurate about
732 * the update-IRQ timing. The IRQ is issued before actually the
733 * data is processed. So, we need to process it afterwords in a
736 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
738 struct snd_pcm_substream *substream = azx_dev->core.substream;
739 int stream = substream->stream;
743 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk;
744 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3)
745 return -1; /* bogus (too early) interrupt */
747 if (chip->get_position[stream])
748 pos = chip->get_position[stream](chip, azx_dev);
749 else { /* use the position buffer as default */
750 pos = azx_get_pos_posbuf(chip, azx_dev);
751 if (!pos || pos == (u32)-1) {
752 dev_info(chip->card->dev,
753 "Invalid position buffer, using LPIB read method instead.\n");
754 chip->get_position[stream] = azx_get_pos_lpib;
755 if (chip->get_position[0] == azx_get_pos_lpib &&
756 chip->get_position[1] == azx_get_pos_lpib)
757 azx_bus(chip)->use_posbuf = false;
758 pos = azx_get_pos_lpib(chip, azx_dev);
759 chip->get_delay[stream] = NULL;
761 chip->get_position[stream] = azx_get_pos_posbuf;
762 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)
763 chip->get_delay[stream] = azx_get_delay_from_lpib;
767 if (pos >= azx_dev->core.bufsize)
770 if (WARN_ONCE(!azx_dev->core.period_bytes,
771 "hda-intel: zero azx_dev->period_bytes"))
772 return -1; /* this shouldn't happen! */
773 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 &&
774 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2)
775 /* NG - it's below the first next period boundary */
776 return chip->bdl_pos_adj ? 0 : -1;
777 azx_dev->core.start_wallclk += wallclk;
778 return 1; /* OK, it's fine */
782 * The work for pending PCM period updates.
784 static void azx_irq_pending_work(struct work_struct *work)
786 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work);
787 struct azx *chip = &hda->chip;
788 struct hdac_bus *bus = azx_bus(chip);
789 struct hdac_stream *s;
792 if (!hda->irq_pending_warned) {
793 dev_info(chip->card->dev,
794 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
796 hda->irq_pending_warned = 1;
801 spin_lock_irq(&bus->reg_lock);
802 list_for_each_entry(s, &bus->stream_list, list) {
803 struct azx_dev *azx_dev = stream_to_azx_dev(s);
804 if (!azx_dev->irq_pending ||
808 ok = azx_position_ok(chip, azx_dev);
810 azx_dev->irq_pending = 0;
811 spin_unlock(&bus->reg_lock);
812 snd_pcm_period_elapsed(s->substream);
813 spin_lock(&bus->reg_lock);
815 pending = 0; /* too early */
819 spin_unlock_irq(&bus->reg_lock);
826 /* clear irq_pending flags and assure no on-going workq */
827 static void azx_clear_irq_pending(struct azx *chip)
829 struct hdac_bus *bus = azx_bus(chip);
830 struct hdac_stream *s;
832 spin_lock_irq(&bus->reg_lock);
833 list_for_each_entry(s, &bus->stream_list, list) {
834 struct azx_dev *azx_dev = stream_to_azx_dev(s);
835 azx_dev->irq_pending = 0;
837 spin_unlock_irq(&bus->reg_lock);
840 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
842 struct hdac_bus *bus = azx_bus(chip);
844 if (request_irq(chip->pci->irq, azx_interrupt,
845 chip->msi ? 0 : IRQF_SHARED,
846 chip->card->irq_descr, chip)) {
847 dev_err(chip->card->dev,
848 "unable to grab IRQ %d, disabling device\n",
851 snd_card_disconnect(chip->card);
854 bus->irq = chip->pci->irq;
855 pci_intx(chip->pci, !chip->msi);
859 /* get the current DMA position with correction on VIA chips */
860 static unsigned int azx_via_get_position(struct azx *chip,
861 struct azx_dev *azx_dev)
863 unsigned int link_pos, mini_pos, bound_pos;
864 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
865 unsigned int fifo_size;
867 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
868 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
869 /* Playback, no problem using link position */
875 * use mod to get the DMA position just like old chipset
877 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf);
878 mod_dma_pos %= azx_dev->core.period_bytes;
880 /* azx_dev->fifo_size can't get FIFO size of in stream.
881 * Get from base address + offset.
883 fifo_size = readw(azx_bus(chip)->remap_addr +
884 VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
886 if (azx_dev->insufficient) {
887 /* Link position never gather than FIFO size */
888 if (link_pos <= fifo_size)
891 azx_dev->insufficient = 0;
894 if (link_pos <= fifo_size)
895 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size;
897 mini_pos = link_pos - fifo_size;
899 /* Find nearest previous boudary */
900 mod_mini_pos = mini_pos % azx_dev->core.period_bytes;
901 mod_link_pos = link_pos % azx_dev->core.period_bytes;
902 if (mod_link_pos >= fifo_size)
903 bound_pos = link_pos - mod_link_pos;
904 else if (mod_dma_pos >= mod_mini_pos)
905 bound_pos = mini_pos - mod_mini_pos;
907 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes;
908 if (bound_pos >= azx_dev->core.bufsize)
912 /* Calculate real DMA position we want */
913 return bound_pos + mod_dma_pos;
916 static unsigned int azx_skl_get_dpib_pos(struct azx *chip,
917 struct azx_dev *azx_dev)
919 return _snd_hdac_chip_readl(azx_bus(chip),
920 AZX_REG_VS_SDXDPIB_XBASE +
921 (AZX_REG_VS_SDXDPIB_XINTERVAL *
922 azx_dev->core.index));
925 /* get the current DMA position with correction on SKL+ chips */
926 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev)
928 /* DPIB register gives a more accurate position for playback */
929 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
930 return azx_skl_get_dpib_pos(chip, azx_dev);
932 /* For capture, we need to read posbuf, but it requires a delay
933 * for the possible boundary overlap; the read of DPIB fetches the
937 azx_skl_get_dpib_pos(chip, azx_dev);
938 return azx_get_pos_posbuf(chip, azx_dev);
942 static DEFINE_MUTEX(card_list_lock);
943 static LIST_HEAD(card_list);
945 static void azx_add_card_list(struct azx *chip)
947 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
948 mutex_lock(&card_list_lock);
949 list_add(&hda->list, &card_list);
950 mutex_unlock(&card_list_lock);
953 static void azx_del_card_list(struct azx *chip)
955 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
956 mutex_lock(&card_list_lock);
957 list_del_init(&hda->list);
958 mutex_unlock(&card_list_lock);
961 /* trigger power-save check at writing parameter */
962 static int param_set_xint(const char *val, const struct kernel_param *kp)
964 struct hda_intel *hda;
966 int prev = power_save;
967 int ret = param_set_int(val, kp);
969 if (ret || prev == power_save)
972 mutex_lock(&card_list_lock);
973 list_for_each_entry(hda, &card_list, list) {
975 if (!hda->probe_continued || chip->disabled)
977 snd_hda_set_power_save(&chip->bus, power_save * 1000);
979 mutex_unlock(&card_list_lock);
983 #define azx_add_card_list(chip) /* NOP */
984 #define azx_del_card_list(chip) /* NOP */
985 #endif /* CONFIG_PM */
987 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
991 static int azx_suspend(struct device *dev)
993 struct snd_card *card = dev_get_drvdata(dev);
995 struct hda_intel *hda;
996 struct hdac_bus *bus;
1001 chip = card->private_data;
1002 hda = container_of(chip, struct hda_intel, chip);
1003 if (chip->disabled || hda->init_failed || !chip->running)
1006 bus = azx_bus(chip);
1007 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1008 azx_clear_irq_pending(chip);
1009 azx_stop_chip(chip);
1010 azx_enter_link_reset(chip);
1011 if (bus->irq >= 0) {
1012 free_irq(bus->irq, chip);
1017 pci_disable_msi(chip->pci);
1018 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
1019 && hda->need_i915_power)
1020 snd_hdac_display_power(bus, false);
1022 trace_azx_suspend(chip);
1026 static int azx_resume(struct device *dev)
1028 struct pci_dev *pci = to_pci_dev(dev);
1029 struct snd_card *card = dev_get_drvdata(dev);
1031 struct hda_intel *hda;
1032 struct hdac_bus *bus;
1037 chip = card->private_data;
1038 hda = container_of(chip, struct hda_intel, chip);
1039 bus = azx_bus(chip);
1040 if (chip->disabled || hda->init_failed || !chip->running)
1043 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1044 snd_hdac_display_power(bus, true);
1045 if (hda->need_i915_power)
1046 snd_hdac_i915_set_bclk(bus);
1050 if (pci_enable_msi(pci) < 0)
1052 if (azx_acquire_irq(chip, 1) < 0)
1056 hda_intel_init_chip(chip, true);
1058 /* power down again for link-controlled chips */
1059 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1060 !hda->need_i915_power)
1061 snd_hdac_display_power(bus, false);
1063 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1065 trace_azx_resume(chip);
1068 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
1070 #ifdef CONFIG_PM_SLEEP
1071 /* put codec down to D3 at hibernation for Intel SKL+;
1072 * otherwise BIOS may still access the codec and screw up the driver
1074 static int azx_freeze_noirq(struct device *dev)
1076 struct pci_dev *pci = to_pci_dev(dev);
1078 if (IS_SKL_PLUS(pci))
1079 pci_set_power_state(pci, PCI_D3hot);
1084 static int azx_thaw_noirq(struct device *dev)
1086 struct pci_dev *pci = to_pci_dev(dev);
1088 if (IS_SKL_PLUS(pci))
1089 pci_set_power_state(pci, PCI_D0);
1093 #endif /* CONFIG_PM_SLEEP */
1096 static int azx_runtime_suspend(struct device *dev)
1098 struct snd_card *card = dev_get_drvdata(dev);
1100 struct hda_intel *hda;
1105 chip = card->private_data;
1106 hda = container_of(chip, struct hda_intel, chip);
1107 if (chip->disabled || hda->init_failed)
1110 if (!azx_has_pm_runtime(chip))
1113 /* enable controller wake up event */
1114 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1117 azx_stop_chip(chip);
1118 azx_enter_link_reset(chip);
1119 azx_clear_irq_pending(chip);
1120 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
1121 && hda->need_i915_power)
1122 snd_hdac_display_power(azx_bus(chip), false);
1124 trace_azx_runtime_suspend(chip);
1128 static int azx_runtime_resume(struct device *dev)
1130 struct snd_card *card = dev_get_drvdata(dev);
1132 struct hda_intel *hda;
1133 struct hdac_bus *bus;
1134 struct hda_codec *codec;
1140 chip = card->private_data;
1141 hda = container_of(chip, struct hda_intel, chip);
1142 bus = azx_bus(chip);
1143 if (chip->disabled || hda->init_failed)
1146 if (!azx_has_pm_runtime(chip))
1149 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1150 snd_hdac_display_power(bus, true);
1151 if (hda->need_i915_power)
1152 snd_hdac_i915_set_bclk(bus);
1155 /* Read STATESTS before controller reset */
1156 status = azx_readw(chip, STATESTS);
1159 hda_intel_init_chip(chip, true);
1162 list_for_each_codec(codec, &chip->bus)
1163 if (status & (1 << codec->addr))
1164 schedule_delayed_work(&codec->jackpoll_work,
1165 codec->jackpoll_interval);
1168 /* disable controller Wake Up event*/
1169 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1170 ~STATESTS_INT_MASK);
1172 /* power down again for link-controlled chips */
1173 if ((chip->driver_caps & AZX_DCAPS_I915_POWERWELL) &&
1174 !hda->need_i915_power)
1175 snd_hdac_display_power(bus, false);
1177 trace_azx_runtime_resume(chip);
1181 static int azx_runtime_idle(struct device *dev)
1183 struct snd_card *card = dev_get_drvdata(dev);
1185 struct hda_intel *hda;
1190 chip = card->private_data;
1191 hda = container_of(chip, struct hda_intel, chip);
1192 if (chip->disabled || hda->init_failed)
1195 if (!power_save_controller || !azx_has_pm_runtime(chip) ||
1196 azx_bus(chip)->codec_powered || !chip->running)
1202 static const struct dev_pm_ops azx_pm = {
1203 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1204 #ifdef CONFIG_PM_SLEEP
1205 .freeze_noirq = azx_freeze_noirq,
1206 .thaw_noirq = azx_thaw_noirq,
1208 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1211 #define AZX_PM_OPS &azx_pm
1213 #define AZX_PM_OPS NULL
1214 #endif /* CONFIG_PM */
1217 static int azx_probe_continue(struct azx *chip);
1219 #ifdef SUPPORT_VGA_SWITCHEROO
1220 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1222 static void azx_vs_set_state(struct pci_dev *pci,
1223 enum vga_switcheroo_state state)
1225 struct snd_card *card = pci_get_drvdata(pci);
1226 struct azx *chip = card->private_data;
1227 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1230 wait_for_completion(&hda->probe_wait);
1231 if (hda->init_failed)
1234 disabled = (state == VGA_SWITCHEROO_OFF);
1235 if (chip->disabled == disabled)
1238 if (!hda->probe_continued) {
1239 chip->disabled = disabled;
1241 dev_info(chip->card->dev,
1242 "Start delayed initialization\n");
1243 if (azx_probe_continue(chip) < 0) {
1244 dev_err(chip->card->dev, "initialization error\n");
1245 hda->init_failed = true;
1249 dev_info(chip->card->dev, "%s via vga_switcheroo\n",
1250 disabled ? "Disabling" : "Enabling");
1252 pm_runtime_put_sync_suspend(card->dev);
1253 azx_suspend(card->dev);
1254 /* when we get suspended by vga_switcheroo we end up in D3cold,
1255 * however we have no ACPI handle, so pci/acpi can't put us there,
1256 * put ourselves there */
1257 pci->current_state = PCI_D3cold;
1258 chip->disabled = true;
1259 if (snd_hda_lock_devices(&chip->bus))
1260 dev_warn(chip->card->dev,
1261 "Cannot lock devices!\n");
1263 snd_hda_unlock_devices(&chip->bus);
1264 pm_runtime_get_noresume(card->dev);
1265 chip->disabled = false;
1266 azx_resume(card->dev);
1271 static bool azx_vs_can_switch(struct pci_dev *pci)
1273 struct snd_card *card = pci_get_drvdata(pci);
1274 struct azx *chip = card->private_data;
1275 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1277 wait_for_completion(&hda->probe_wait);
1278 if (hda->init_failed)
1280 if (chip->disabled || !hda->probe_continued)
1282 if (snd_hda_lock_devices(&chip->bus))
1284 snd_hda_unlock_devices(&chip->bus);
1288 static void init_vga_switcheroo(struct azx *chip)
1290 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1291 struct pci_dev *p = get_bound_vga(chip->pci);
1293 dev_info(chip->card->dev,
1294 "Handle vga_switcheroo audio client\n");
1295 hda->use_vga_switcheroo = 1;
1300 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1301 .set_gpu_state = azx_vs_set_state,
1302 .can_switch = azx_vs_can_switch,
1305 static int register_vga_switcheroo(struct azx *chip)
1307 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1310 if (!hda->use_vga_switcheroo)
1312 /* FIXME: currently only handling DIS controller
1313 * is there any machine with two switchable HDMI audio controllers?
1315 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1316 VGA_SWITCHEROO_DIS);
1319 hda->vga_switcheroo_registered = 1;
1321 /* register as an optimus hdmi audio power domain */
1322 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1323 &hda->hdmi_pm_domain);
1327 #define init_vga_switcheroo(chip) /* NOP */
1328 #define register_vga_switcheroo(chip) 0
1329 #define check_hdmi_disabled(pci) false
1330 #endif /* SUPPORT_VGA_SWITCHER */
1335 static int azx_free(struct azx *chip)
1337 struct pci_dev *pci = chip->pci;
1338 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
1339 struct hdac_bus *bus = azx_bus(chip);
1341 if (azx_has_pm_runtime(chip) && chip->running)
1342 pm_runtime_get_noresume(&pci->dev);
1344 azx_del_card_list(chip);
1346 hda->init_failed = 1; /* to be sure */
1347 complete_all(&hda->probe_wait);
1349 if (use_vga_switcheroo(hda)) {
1350 if (chip->disabled && hda->probe_continued)
1351 snd_hda_unlock_devices(&chip->bus);
1352 if (hda->vga_switcheroo_registered) {
1353 vga_switcheroo_unregister_client(chip->pci);
1354 vga_switcheroo_fini_domain_pm_ops(chip->card->dev);
1358 if (bus->chip_init) {
1359 azx_clear_irq_pending(chip);
1360 azx_stop_all_streams(chip);
1361 azx_stop_chip(chip);
1365 free_irq(bus->irq, (void*)chip);
1367 pci_disable_msi(chip->pci);
1368 iounmap(bus->remap_addr);
1370 azx_free_stream_pages(chip);
1371 azx_free_streams(chip);
1372 snd_hdac_bus_exit(bus);
1374 if (chip->region_requested)
1375 pci_release_regions(chip->pci);
1377 pci_disable_device(chip->pci);
1378 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1379 release_firmware(chip->fw);
1382 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1383 if (hda->need_i915_power)
1384 snd_hdac_display_power(bus, false);
1385 snd_hdac_i915_exit(bus);
1392 static int azx_dev_disconnect(struct snd_device *device)
1394 struct azx *chip = device->device_data;
1396 chip->bus.shutdown = 1;
1400 static int azx_dev_free(struct snd_device *device)
1402 return azx_free(device->device_data);
1405 #ifdef SUPPORT_VGA_SWITCHEROO
1407 * Check of disabled HDMI controller by vga_switcheroo
1409 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1413 /* check only discrete GPU */
1414 switch (pci->vendor) {
1415 case PCI_VENDOR_ID_ATI:
1416 case PCI_VENDOR_ID_AMD:
1417 case PCI_VENDOR_ID_NVIDIA:
1418 if (pci->devfn == 1) {
1419 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1420 pci->bus->number, 0);
1422 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1432 static bool check_hdmi_disabled(struct pci_dev *pci)
1434 bool vga_inactive = false;
1435 struct pci_dev *p = get_bound_vga(pci);
1438 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1439 vga_inactive = true;
1442 return vga_inactive;
1444 #endif /* SUPPORT_VGA_SWITCHEROO */
1447 * white/black-listing for position_fix
1449 static struct snd_pci_quirk position_fix_list[] = {
1450 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1451 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1452 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1453 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1454 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1455 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1456 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1457 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1458 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1459 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1460 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1461 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1462 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1463 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1467 static int check_position_fix(struct azx *chip, int fix)
1469 const struct snd_pci_quirk *q;
1474 case POS_FIX_POSBUF:
1475 case POS_FIX_VIACOMBO:
1481 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1483 dev_info(chip->card->dev,
1484 "position_fix set to %d for device %04x:%04x\n",
1485 q->value, q->subvendor, q->subdevice);
1489 /* Check VIA/ATI HD Audio Controller exist */
1490 if (chip->driver_type == AZX_DRIVER_VIA) {
1491 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1492 return POS_FIX_VIACOMBO;
1494 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1495 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1496 return POS_FIX_LPIB;
1498 if (IS_SKL_PLUS(chip->pci)) {
1499 dev_dbg(chip->card->dev, "Using SKL position fix\n");
1502 return POS_FIX_AUTO;
1505 static void assign_position_fix(struct azx *chip, int fix)
1507 static azx_get_pos_callback_t callbacks[] = {
1508 [POS_FIX_AUTO] = NULL,
1509 [POS_FIX_LPIB] = azx_get_pos_lpib,
1510 [POS_FIX_POSBUF] = azx_get_pos_posbuf,
1511 [POS_FIX_VIACOMBO] = azx_via_get_position,
1512 [POS_FIX_COMBO] = azx_get_pos_lpib,
1513 [POS_FIX_SKL] = azx_get_pos_skl,
1516 chip->get_position[0] = chip->get_position[1] = callbacks[fix];
1518 /* combo mode uses LPIB only for playback */
1519 if (fix == POS_FIX_COMBO)
1520 chip->get_position[1] = NULL;
1522 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) &&
1523 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
1524 chip->get_delay[0] = chip->get_delay[1] =
1525 azx_get_delay_from_lpib;
1531 * black-lists for probe_mask
1533 static struct snd_pci_quirk probe_mask_list[] = {
1534 /* Thinkpad often breaks the controller communication when accessing
1535 * to the non-working (or non-existing) modem codec slot.
1537 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1538 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1539 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1541 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1542 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1543 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1544 /* forced codec slots */
1545 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
1546 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
1547 /* WinFast VP200 H (Teradici) user reported broken communication */
1548 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
1552 #define AZX_FORCE_CODEC_MASK 0x100
1554 static void check_probe_mask(struct azx *chip, int dev)
1556 const struct snd_pci_quirk *q;
1558 chip->codec_probe_mask = probe_mask[dev];
1559 if (chip->codec_probe_mask == -1) {
1560 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1562 dev_info(chip->card->dev,
1563 "probe_mask set to 0x%x for device %04x:%04x\n",
1564 q->value, q->subvendor, q->subdevice);
1565 chip->codec_probe_mask = q->value;
1569 /* check forced option */
1570 if (chip->codec_probe_mask != -1 &&
1571 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
1572 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff;
1573 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
1574 (int)azx_bus(chip)->codec_mask);
1579 * white/black-list for enable_msi
1581 static struct snd_pci_quirk msi_black_list[] = {
1582 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
1583 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
1584 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
1585 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
1586 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
1587 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
1588 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
1589 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
1590 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
1591 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
1595 static void check_msi(struct azx *chip)
1597 const struct snd_pci_quirk *q;
1599 if (enable_msi >= 0) {
1600 chip->msi = !!enable_msi;
1603 chip->msi = 1; /* enable MSI as default */
1604 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
1606 dev_info(chip->card->dev,
1607 "msi for device %04x:%04x set to %d\n",
1608 q->subvendor, q->subdevice, q->value);
1609 chip->msi = q->value;
1613 /* NVidia chipsets seem to cause troubles with MSI */
1614 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
1615 dev_info(chip->card->dev, "Disabling MSI\n");
1620 /* check the snoop mode availability */
1621 static void azx_check_snoop_available(struct azx *chip)
1623 int snoop = hda_snoop;
1626 dev_info(chip->card->dev, "Force to %s mode by module option\n",
1627 snoop ? "snoop" : "non-snoop");
1628 chip->snoop = snoop;
1633 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE &&
1634 chip->driver_type == AZX_DRIVER_VIA) {
1635 /* force to non-snoop mode for a new VIA controller
1639 pci_read_config_byte(chip->pci, 0x42, &val);
1640 if (!(val & 0x80) && chip->pci->revision == 0x30)
1644 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF)
1647 chip->snoop = snoop;
1649 dev_info(chip->card->dev, "Force to non-snoop mode\n");
1652 static void azx_probe_work(struct work_struct *work)
1654 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work);
1655 azx_probe_continue(&hda->chip);
1658 static int default_bdl_pos_adj(struct azx *chip)
1660 /* some exceptions: Atoms seem problematic with value 1 */
1661 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) {
1662 switch (chip->pci->device) {
1663 case 0x0f04: /* Baytrail */
1664 case 0x2284: /* Braswell */
1669 switch (chip->driver_type) {
1670 case AZX_DRIVER_ICH:
1671 case AZX_DRIVER_PCH:
1681 static const struct hdac_io_ops pci_hda_io_ops;
1682 static const struct hda_controller_ops pci_hda_ops;
1684 static int azx_create(struct snd_card *card, struct pci_dev *pci,
1685 int dev, unsigned int driver_caps,
1688 static struct snd_device_ops ops = {
1689 .dev_disconnect = azx_dev_disconnect,
1690 .dev_free = azx_dev_free,
1692 struct hda_intel *hda;
1698 err = pci_enable_device(pci);
1702 hda = kzalloc(sizeof(*hda), GFP_KERNEL);
1704 pci_disable_device(pci);
1709 mutex_init(&chip->open_mutex);
1712 chip->ops = &pci_hda_ops;
1713 chip->driver_caps = driver_caps;
1714 chip->driver_type = driver_caps & 0xff;
1716 chip->dev_index = dev;
1717 chip->jackpoll_ms = jackpoll_ms;
1718 INIT_LIST_HEAD(&chip->pcm_list);
1719 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work);
1720 INIT_LIST_HEAD(&hda->list);
1721 init_vga_switcheroo(chip);
1722 init_completion(&hda->probe_wait);
1724 assign_position_fix(chip, check_position_fix(chip, position_fix[dev]));
1726 check_probe_mask(chip, dev);
1728 if (single_cmd < 0) /* allow fallback to single_cmd at errors */
1729 chip->fallback_to_single_cmd = 1;
1730 else /* explicitly set to single_cmd or not */
1731 chip->single_cmd = single_cmd;
1733 azx_check_snoop_available(chip);
1735 if (bdl_pos_adj[dev] < 0)
1736 chip->bdl_pos_adj = default_bdl_pos_adj(chip);
1738 chip->bdl_pos_adj = bdl_pos_adj[dev];
1740 err = azx_bus_init(chip, model[dev], &pci_hda_io_ops);
1743 pci_disable_device(pci);
1747 if (chip->driver_type == AZX_DRIVER_NVIDIA) {
1748 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1749 chip->bus.needs_damn_long_delay = 1;
1752 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1754 dev_err(card->dev, "Error creating device [card]!\n");
1759 /* continue probing in work context as may trigger request module */
1760 INIT_WORK(&hda->probe_work, azx_probe_work);
1767 static int azx_first_init(struct azx *chip)
1769 int dev = chip->dev_index;
1770 struct pci_dev *pci = chip->pci;
1771 struct snd_card *card = chip->card;
1772 struct hdac_bus *bus = azx_bus(chip);
1774 unsigned short gcap;
1775 unsigned int dma_bits = 64;
1777 #if BITS_PER_LONG != 64
1778 /* Fix up base address on ULI M5461 */
1779 if (chip->driver_type == AZX_DRIVER_ULI) {
1781 pci_read_config_word(pci, 0x40, &tmp3);
1782 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1783 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1787 err = pci_request_regions(pci, "ICH HD audio");
1790 chip->region_requested = 1;
1792 bus->addr = pci_resource_start(pci, 0);
1793 bus->remap_addr = pci_ioremap_bar(pci, 0);
1794 if (bus->remap_addr == NULL) {
1795 dev_err(card->dev, "ioremap error\n");
1799 if (IS_SKL_PLUS(pci))
1800 snd_hdac_bus_parse_capabilities(bus);
1803 * Some Intel CPUs has always running timer (ART) feature and
1804 * controller may have Global time sync reporting capability, so
1805 * check both of these before declaring synchronized time reporting
1806 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME
1808 chip->gts_present = false;
1811 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART))
1812 chip->gts_present = true;
1816 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) {
1817 dev_dbg(card->dev, "Disabling 64bit MSI\n");
1818 pci->no_64bit_msi = true;
1820 if (pci_enable_msi(pci) < 0)
1824 if (azx_acquire_irq(chip, 0) < 0)
1827 pci_set_master(pci);
1828 synchronize_irq(bus->irq);
1830 gcap = azx_readw(chip, GCAP);
1831 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
1833 /* AMD devices support 40 or 48bit DMA, take the safe one */
1834 if (chip->pci->vendor == PCI_VENDOR_ID_AMD)
1837 /* disable SB600 64bit support for safety */
1838 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
1839 struct pci_dev *p_smbus;
1841 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
1842 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1845 if (p_smbus->revision < 0x30)
1846 gcap &= ~AZX_GCAP_64OK;
1847 pci_dev_put(p_smbus);
1851 /* NVidia hardware normally only supports up to 40 bits of DMA */
1852 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA)
1855 /* disable 64bit DMA address on some devices */
1856 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
1857 dev_dbg(card->dev, "Disabling 64bit DMA\n");
1858 gcap &= ~AZX_GCAP_64OK;
1861 /* disable buffer size rounding to 128-byte multiples if supported */
1862 if (align_buffer_size >= 0)
1863 chip->align_buffer_size = !!align_buffer_size;
1865 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE)
1866 chip->align_buffer_size = 0;
1868 chip->align_buffer_size = 1;
1871 /* allow 64bit DMA address if supported by H/W */
1872 if (!(gcap & AZX_GCAP_64OK))
1874 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1875 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
1877 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
1878 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
1881 /* read number of streams from GCAP register instead of using
1884 chip->capture_streams = (gcap >> 8) & 0x0f;
1885 chip->playback_streams = (gcap >> 12) & 0x0f;
1886 if (!chip->playback_streams && !chip->capture_streams) {
1887 /* gcap didn't give any info, switching to old method */
1889 switch (chip->driver_type) {
1890 case AZX_DRIVER_ULI:
1891 chip->playback_streams = ULI_NUM_PLAYBACK;
1892 chip->capture_streams = ULI_NUM_CAPTURE;
1894 case AZX_DRIVER_ATIHDMI:
1895 case AZX_DRIVER_ATIHDMI_NS:
1896 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1897 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1899 case AZX_DRIVER_GENERIC:
1901 chip->playback_streams = ICH6_NUM_PLAYBACK;
1902 chip->capture_streams = ICH6_NUM_CAPTURE;
1906 chip->capture_index_offset = 0;
1907 chip->playback_index_offset = chip->capture_streams;
1908 chip->num_streams = chip->playback_streams + chip->capture_streams;
1910 /* sanity check for the SDxCTL.STRM field overflow */
1911 if (chip->num_streams > 15 &&
1912 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) {
1913 dev_warn(chip->card->dev, "number of I/O streams is %d, "
1914 "forcing separate stream tags", chip->num_streams);
1915 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG;
1918 /* initialize streams */
1919 err = azx_init_streams(chip);
1923 err = azx_alloc_stream_pages(chip);
1927 /* initialize chip */
1930 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1931 snd_hdac_i915_set_bclk(bus);
1933 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0);
1935 /* codec detection */
1936 if (!azx_bus(chip)->codec_mask) {
1937 dev_err(card->dev, "no codecs found!\n");
1941 strcpy(card->driver, "HDA-Intel");
1942 strlcpy(card->shortname, driver_short_names[chip->driver_type],
1943 sizeof(card->shortname));
1944 snprintf(card->longname, sizeof(card->longname),
1945 "%s at 0x%lx irq %i",
1946 card->shortname, bus->addr, bus->irq);
1951 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1952 /* callback from request_firmware_nowait() */
1953 static void azx_firmware_cb(const struct firmware *fw, void *context)
1955 struct snd_card *card = context;
1956 struct azx *chip = card->private_data;
1957 struct pci_dev *pci = chip->pci;
1960 dev_err(card->dev, "Cannot load firmware, aborting\n");
1965 if (!chip->disabled) {
1966 /* continue probing */
1967 if (azx_probe_continue(chip))
1973 snd_card_free(card);
1974 pci_set_drvdata(pci, NULL);
1979 * HDA controller ops.
1982 /* PCI register access. */
1983 static void pci_azx_writel(u32 value, u32 __iomem *addr)
1985 writel(value, addr);
1988 static u32 pci_azx_readl(u32 __iomem *addr)
1993 static void pci_azx_writew(u16 value, u16 __iomem *addr)
1995 writew(value, addr);
1998 static u16 pci_azx_readw(u16 __iomem *addr)
2003 static void pci_azx_writeb(u8 value, u8 __iomem *addr)
2005 writeb(value, addr);
2008 static u8 pci_azx_readb(u8 __iomem *addr)
2013 static int disable_msi_reset_irq(struct azx *chip)
2015 struct hdac_bus *bus = azx_bus(chip);
2018 free_irq(bus->irq, chip);
2020 pci_disable_msi(chip->pci);
2022 err = azx_acquire_irq(chip, 1);
2029 /* DMA page allocation helpers. */
2030 static int dma_alloc_pages(struct hdac_bus *bus,
2033 struct snd_dma_buffer *buf)
2035 struct azx *chip = bus_to_azx(bus);
2038 err = snd_dma_alloc_pages(type,
2043 mark_pages_wc(chip, buf, true);
2047 static void dma_free_pages(struct hdac_bus *bus, struct snd_dma_buffer *buf)
2049 struct azx *chip = bus_to_azx(bus);
2051 mark_pages_wc(chip, buf, false);
2052 snd_dma_free_pages(buf);
2055 static int substream_alloc_pages(struct azx *chip,
2056 struct snd_pcm_substream *substream,
2059 struct azx_dev *azx_dev = get_azx_dev(substream);
2062 mark_runtime_wc(chip, azx_dev, substream, false);
2063 ret = snd_pcm_lib_malloc_pages(substream, size);
2066 mark_runtime_wc(chip, azx_dev, substream, true);
2070 static int substream_free_pages(struct azx *chip,
2071 struct snd_pcm_substream *substream)
2073 struct azx_dev *azx_dev = get_azx_dev(substream);
2074 mark_runtime_wc(chip, azx_dev, substream, false);
2075 return snd_pcm_lib_free_pages(substream);
2078 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2079 struct vm_area_struct *area)
2082 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2083 struct azx *chip = apcm->chip;
2084 if (!azx_snoop(chip) && chip->driver_type != AZX_DRIVER_CMEDIA)
2085 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2089 static const struct hdac_io_ops pci_hda_io_ops = {
2090 .reg_writel = pci_azx_writel,
2091 .reg_readl = pci_azx_readl,
2092 .reg_writew = pci_azx_writew,
2093 .reg_readw = pci_azx_readw,
2094 .reg_writeb = pci_azx_writeb,
2095 .reg_readb = pci_azx_readb,
2096 .dma_alloc_pages = dma_alloc_pages,
2097 .dma_free_pages = dma_free_pages,
2100 static const struct hda_controller_ops pci_hda_ops = {
2101 .disable_msi_reset_irq = disable_msi_reset_irq,
2102 .substream_alloc_pages = substream_alloc_pages,
2103 .substream_free_pages = substream_free_pages,
2104 .pcm_mmap_prepare = pcm_mmap_prepare,
2105 .position_check = azx_position_check,
2106 .link_power = azx_intel_link_power,
2109 static int azx_probe(struct pci_dev *pci,
2110 const struct pci_device_id *pci_id)
2113 struct snd_card *card;
2114 struct hda_intel *hda;
2116 bool schedule_probe;
2119 if (dev >= SNDRV_CARDS)
2126 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2129 dev_err(&pci->dev, "Error creating card!\n");
2133 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2136 card->private_data = chip;
2137 hda = container_of(chip, struct hda_intel, chip);
2139 pci_set_drvdata(pci, card);
2141 err = register_vga_switcheroo(chip);
2143 dev_err(card->dev, "Error registering vga_switcheroo client\n");
2147 if (check_hdmi_disabled(pci)) {
2148 dev_info(card->dev, "VGA controller is disabled\n");
2149 dev_info(card->dev, "Delaying initialization\n");
2150 chip->disabled = true;
2153 schedule_probe = !chip->disabled;
2155 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2156 if (patch[dev] && *patch[dev]) {
2157 dev_info(card->dev, "Applying patch firmware '%s'\n",
2159 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2160 &pci->dev, GFP_KERNEL, card,
2164 schedule_probe = false; /* continued in azx_firmware_cb() */
2166 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2168 #ifndef CONFIG_SND_HDA_I915
2169 if (CONTROLLER_IN_GPU(pci))
2170 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n");
2174 schedule_work(&hda->probe_work);
2178 complete_all(&hda->probe_wait);
2182 snd_card_free(card);
2186 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2187 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2188 [AZX_DRIVER_NVIDIA] = 8,
2189 [AZX_DRIVER_TERA] = 1,
2192 static int azx_probe_continue(struct azx *chip)
2194 struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
2195 struct hdac_bus *bus = azx_bus(chip);
2196 struct pci_dev *pci = chip->pci;
2197 int dev = chip->dev_index;
2200 hda->probe_continued = 1;
2202 /* Request display power well for the HDA controller or codec. For
2203 * Haswell/Broadwell, both the display HDA controller and codec need
2204 * this power. For other platforms, like Baytrail/Braswell, only the
2205 * display codec needs the power and it can be released after probe.
2207 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2208 /* HSW/BDW controllers need this power */
2209 if (CONTROLLER_IN_GPU(pci))
2210 hda->need_i915_power = 1;
2212 err = snd_hdac_i915_init(bus);
2214 /* if the controller is bound only with HDMI/DP
2215 * (for HSW and BDW), we need to abort the probe;
2216 * for other chips, still continue probing as other
2217 * codecs can be on the same link.
2219 if (CONTROLLER_IN_GPU(pci)) {
2220 dev_err(chip->card->dev,
2221 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n");
2227 err = snd_hdac_display_power(bus, true);
2229 dev_err(chip->card->dev,
2230 "Cannot turn on display power on i915\n");
2231 goto i915_power_fail;
2236 err = azx_first_init(chip);
2240 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2241 chip->beep_mode = beep_mode[dev];
2244 /* create codec instances */
2245 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]);
2249 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2251 err = snd_hda_load_patch(&chip->bus, chip->fw->size,
2256 release_firmware(chip->fw); /* no longer needed */
2261 if ((probe_only[dev] & 1) == 0) {
2262 err = azx_codec_configure(chip);
2267 err = snd_card_register(chip->card);
2272 azx_add_card_list(chip);
2273 snd_hda_set_power_save(&chip->bus, power_save * 1000);
2274 if (azx_has_pm_runtime(chip) || hda->use_vga_switcheroo)
2275 pm_runtime_put_autosuspend(&pci->dev);
2278 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL
2279 && !hda->need_i915_power)
2280 snd_hdac_display_power(bus, false);
2284 hda->init_failed = 1;
2285 complete_all(&hda->probe_wait);
2289 static void azx_remove(struct pci_dev *pci)
2291 struct snd_card *card = pci_get_drvdata(pci);
2293 struct hda_intel *hda;
2296 /* cancel the pending probing work */
2297 chip = card->private_data;
2298 hda = container_of(chip, struct hda_intel, chip);
2299 /* FIXME: below is an ugly workaround.
2300 * Both device_release_driver() and driver_probe_device()
2301 * take *both* the device's and its parent's lock before
2302 * calling the remove() and probe() callbacks. The codec
2303 * probe takes the locks of both the codec itself and its
2304 * parent, i.e. the PCI controller dev. Meanwhile, when
2305 * the PCI controller is unbound, it takes its lock, too
2306 * ==> ouch, a deadlock!
2307 * As a workaround, we unlock temporarily here the controller
2308 * device during cancel_work_sync() call.
2310 device_unlock(&pci->dev);
2311 cancel_work_sync(&hda->probe_work);
2312 device_lock(&pci->dev);
2314 snd_card_free(card);
2318 static void azx_shutdown(struct pci_dev *pci)
2320 struct snd_card *card = pci_get_drvdata(pci);
2325 chip = card->private_data;
2326 if (chip && chip->running)
2327 azx_stop_chip(chip);
2331 static const struct pci_device_id azx_ids[] = {
2333 { PCI_DEVICE(0x8086, 0x1c20),
2334 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2336 { PCI_DEVICE(0x8086, 0x1d20),
2337 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2339 { PCI_DEVICE(0x8086, 0x1e20),
2340 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2342 { PCI_DEVICE(0x8086, 0x8c20),
2343 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2345 { PCI_DEVICE(0x8086, 0x8ca0),
2346 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2348 { PCI_DEVICE(0x8086, 0x8d20),
2349 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2350 { PCI_DEVICE(0x8086, 0x8d21),
2351 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2353 { PCI_DEVICE(0x8086, 0xa1f0),
2354 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2355 { PCI_DEVICE(0x8086, 0xa270),
2356 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2358 { PCI_DEVICE(0x8086, 0x9c20),
2359 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2361 { PCI_DEVICE(0x8086, 0x9c21),
2362 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2363 /* Wildcat Point-LP */
2364 { PCI_DEVICE(0x8086, 0x9ca0),
2365 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2367 { PCI_DEVICE(0x8086, 0xa170),
2368 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2369 /* Sunrise Point-LP */
2370 { PCI_DEVICE(0x8086, 0x9d70),
2371 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2373 { PCI_DEVICE(0x8086, 0xa171),
2374 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2376 { PCI_DEVICE(0x8086, 0x9d71),
2377 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2379 { PCI_DEVICE(0x8086, 0xa2f0),
2380 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE },
2381 /* Broxton-P(Apollolake) */
2382 { PCI_DEVICE(0x8086, 0x5a98),
2383 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2385 { PCI_DEVICE(0x8086, 0x1a98),
2386 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2388 { PCI_DEVICE(0x8086, 0x3198),
2389 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BROXTON },
2391 { PCI_DEVICE(0x8086, 0x0a0c),
2392 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2393 { PCI_DEVICE(0x8086, 0x0c0c),
2394 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2395 { PCI_DEVICE(0x8086, 0x0d0c),
2396 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2398 { PCI_DEVICE(0x8086, 0x160c),
2399 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL },
2401 { PCI_DEVICE(0x8086, 0x3b56),
2402 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2404 { PCI_DEVICE(0x8086, 0x811b),
2405 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2407 { PCI_DEVICE(0x8086, 0x080a),
2408 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE },
2410 { PCI_DEVICE(0x8086, 0x0f04),
2411 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL },
2413 { PCI_DEVICE(0x8086, 0x2284),
2414 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL },
2416 { PCI_DEVICE(0x8086, 0x2668),
2417 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2419 { PCI_DEVICE(0x8086, 0x27d8),
2420 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2422 { PCI_DEVICE(0x8086, 0x269a),
2423 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2425 { PCI_DEVICE(0x8086, 0x284b),
2426 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2428 { PCI_DEVICE(0x8086, 0x293e),
2429 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2431 { PCI_DEVICE(0x8086, 0x293f),
2432 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2434 { PCI_DEVICE(0x8086, 0x3a3e),
2435 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2437 { PCI_DEVICE(0x8086, 0x3a6e),
2438 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH },
2440 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2441 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2442 .class_mask = 0xffffff,
2443 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE },
2444 /* ATI SB 450/600/700/800/900 */
2445 { PCI_DEVICE(0x1002, 0x437b),
2446 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2447 { PCI_DEVICE(0x1002, 0x4383),
2448 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2450 { PCI_DEVICE(0x1022, 0x780d),
2451 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2453 { PCI_DEVICE(0x1002, 0x0002),
2454 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2455 { PCI_DEVICE(0x1002, 0x1308),
2456 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2457 { PCI_DEVICE(0x1002, 0x157a),
2458 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2459 { PCI_DEVICE(0x1002, 0x15b3),
2460 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2461 { PCI_DEVICE(0x1002, 0x793b),
2462 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2463 { PCI_DEVICE(0x1002, 0x7919),
2464 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2465 { PCI_DEVICE(0x1002, 0x960f),
2466 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2467 { PCI_DEVICE(0x1002, 0x970f),
2468 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2469 { PCI_DEVICE(0x1002, 0x9840),
2470 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2471 { PCI_DEVICE(0x1002, 0xaa00),
2472 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2473 { PCI_DEVICE(0x1002, 0xaa08),
2474 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2475 { PCI_DEVICE(0x1002, 0xaa10),
2476 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2477 { PCI_DEVICE(0x1002, 0xaa18),
2478 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2479 { PCI_DEVICE(0x1002, 0xaa20),
2480 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2481 { PCI_DEVICE(0x1002, 0xaa28),
2482 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2483 { PCI_DEVICE(0x1002, 0xaa30),
2484 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2485 { PCI_DEVICE(0x1002, 0xaa38),
2486 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2487 { PCI_DEVICE(0x1002, 0xaa40),
2488 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2489 { PCI_DEVICE(0x1002, 0xaa48),
2490 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2491 { PCI_DEVICE(0x1002, 0xaa50),
2492 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2493 { PCI_DEVICE(0x1002, 0xaa58),
2494 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2495 { PCI_DEVICE(0x1002, 0xaa60),
2496 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2497 { PCI_DEVICE(0x1002, 0xaa68),
2498 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2499 { PCI_DEVICE(0x1002, 0xaa80),
2500 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2501 { PCI_DEVICE(0x1002, 0xaa88),
2502 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2503 { PCI_DEVICE(0x1002, 0xaa90),
2504 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2505 { PCI_DEVICE(0x1002, 0xaa98),
2506 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2507 { PCI_DEVICE(0x1002, 0x9902),
2508 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2509 { PCI_DEVICE(0x1002, 0xaaa0),
2510 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2511 { PCI_DEVICE(0x1002, 0xaaa8),
2512 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2513 { PCI_DEVICE(0x1002, 0xaab0),
2514 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2515 { PCI_DEVICE(0x1002, 0xaac0),
2516 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2517 { PCI_DEVICE(0x1002, 0xaac8),
2518 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2519 { PCI_DEVICE(0x1002, 0xaad8),
2520 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2521 { PCI_DEVICE(0x1002, 0xaae8),
2522 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2523 { PCI_DEVICE(0x1002, 0xaae0),
2524 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2525 { PCI_DEVICE(0x1002, 0xaaf0),
2526 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS },
2527 /* VIA VT8251/VT8237A */
2528 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2529 /* VIA GFX VT7122/VX900 */
2530 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2531 /* VIA GFX VT6122/VX11 */
2532 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2534 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2536 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2538 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2539 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2540 .class_mask = 0xffffff,
2541 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2543 { PCI_DEVICE(0x6549, 0x1200),
2544 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2545 { PCI_DEVICE(0x6549, 0x2200),
2546 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2547 /* Creative X-Fi (CA0110-IBG) */
2549 { PCI_DEVICE(0x1102, 0x0010),
2550 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2551 { PCI_DEVICE(0x1102, 0x0012),
2552 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2553 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2554 /* the following entry conflicts with snd-ctxfi driver,
2555 * as ctxfi driver mutates from HD-audio to native mode with
2556 * a special command sequence.
2558 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2559 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2560 .class_mask = 0xffffff,
2561 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2562 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2564 /* this entry seems still valid -- i.e. without emu20kx chip */
2565 { PCI_DEVICE(0x1102, 0x0009),
2566 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2567 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB },
2570 { PCI_DEVICE(0x13f6, 0x5011),
2571 .driver_data = AZX_DRIVER_CMEDIA |
2572 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF },
2574 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2575 /* VMware HDAudio */
2576 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2577 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2578 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2579 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2580 .class_mask = 0xffffff,
2581 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2582 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2583 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2584 .class_mask = 0xffffff,
2585 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2588 MODULE_DEVICE_TABLE(pci, azx_ids);
2590 /* pci_driver definition */
2591 static struct pci_driver azx_driver = {
2592 .name = KBUILD_MODNAME,
2593 .id_table = azx_ids,
2595 .remove = azx_remove,
2596 .shutdown = azx_shutdown,
2602 module_pci_driver(azx_driver);