2 * SAS structures and definitions header file
4 * Copyright (C) 2005 Adaptec, Inc. All rights reserved.
5 * Copyright (C) 2005 Luben Tuikov <luben_tuikov@adaptec.com>
7 * This file is licensed under GPLv2.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
29 #include <linux/types.h>
30 #include <asm/byteorder.h>
32 #define SAS_ADDR_SIZE 8
33 #define HASHED_SAS_ADDR_SIZE 3
34 #define SAS_ADDR(_sa) ((unsigned long long) be64_to_cpu(*(__be64 *)(_sa)))
36 #define SMP_REQUEST 0x40
37 #define SMP_RESPONSE 0x41
40 #define SSP_XFER_RDY 0x05
41 #define SSP_COMMAND 0x06
42 #define SSP_RESPONSE 0x07
45 #define SMP_REPORT_GENERAL 0x00
46 #define SMP_REPORT_MANUF_INFO 0x01
47 #define SMP_READ_GPIO_REG 0x02
48 #define SMP_DISCOVER 0x10
49 #define SMP_REPORT_PHY_ERR_LOG 0x11
50 #define SMP_REPORT_PHY_SATA 0x12
51 #define SMP_REPORT_ROUTE_INFO 0x13
52 #define SMP_WRITE_GPIO_REG 0x82
53 #define SMP_CONF_ROUTE_INFO 0x90
54 #define SMP_PHY_CONTROL 0x91
55 #define SMP_PHY_TEST_FUNCTION 0x92
57 #define SMP_RESP_FUNC_ACC 0x00
58 #define SMP_RESP_FUNC_UNK 0x01
59 #define SMP_RESP_FUNC_FAILED 0x02
60 #define SMP_RESP_INV_FRM_LEN 0x03
61 #define SMP_RESP_NO_PHY 0x10
62 #define SMP_RESP_NO_INDEX 0x11
63 #define SMP_RESP_PHY_NO_SATA 0x12
64 #define SMP_RESP_PHY_UNK_OP 0x13
65 #define SMP_RESP_PHY_UNK_TESTF 0x14
66 #define SMP_RESP_PHY_TEST_INPROG 0x15
67 #define SMP_RESP_PHY_VACANT 0x16
70 #define TMF_ABORT_TASK 0x01
71 #define TMF_ABORT_TASK_SET 0x02
72 #define TMF_CLEAR_TASK_SET 0x04
73 #define TMF_LU_RESET 0x08
74 #define TMF_CLEAR_ACA 0x40
75 #define TMF_QUERY_TASK 0x80
77 /* SAS TMF responses */
78 #define TMF_RESP_FUNC_COMPLETE 0x00
79 #define TMF_RESP_INVALID_FRAME 0x02
80 #define TMF_RESP_FUNC_ESUPP 0x04
81 #define TMF_RESP_FUNC_FAILED 0x05
82 #define TMF_RESP_FUNC_SUCC 0x08
83 #define TMF_RESP_NO_LUN 0x09
84 #define TMF_RESP_OVERLAPPED_TAG 0x0A
92 /* See sas_discover.c if you plan on changing these */
93 enum sas_device_type {
94 /* these are SAS protocol defined (attached device type field) */
97 SAS_EDGE_EXPANDER_DEVICE = 2,
98 SAS_FANOUT_EXPANDER_DEVICE = 3,
99 /* these are internal to libsas */
103 SAS_SATA_PM_PORT = 8,
104 SAS_SATA_PENDING = 9,
108 SAS_PROTOCOL_NONE = 0,
109 SAS_PROTOCOL_SATA = 0x01,
110 SAS_PROTOCOL_SMP = 0x02,
111 SAS_PROTOCOL_STP = 0x04,
112 SAS_PROTOCOL_SSP = 0x08,
113 SAS_PROTOCOL_ALL = 0x0E,
114 SAS_PROTOCOL_STP_ALL = SAS_PROTOCOL_STP|SAS_PROTOCOL_SATA,
117 /* From the spec; local phys only */
120 PHY_FUNC_LINK_RESET, /* Enables the phy */
123 PHY_FUNC_CLEAR_ERROR_LOG = 5,
124 PHY_FUNC_CLEAR_AFFIL,
125 PHY_FUNC_TX_SATA_PS_SIGNAL,
126 PHY_FUNC_RELEASE_SPINUP_HOLD = 0x10, /* LOCAL PORT ONLY! */
127 PHY_FUNC_SET_LINK_RATE,
131 /* SAS LLDD would need to report only _very_few_ of those, like BROADCAST.
132 * Most of those are here for completeness.
135 SAS_PRIM_AIP_NORMAL = 1,
142 SAS_PRIM_AIP_RWP = 8,
145 SAS_PRIM_BC_RCH0 = 10,
146 SAS_PRIM_BC_RCH1 = 11,
153 SAS_PRIM_NOTIFY_ENSP= 17,
154 SAS_PRIM_NOTIFY_R0 = 18,
155 SAS_PRIM_NOTIFY_R1 = 19,
156 SAS_PRIM_NOTIFY_R2 = 20,
158 SAS_PRIM_CLOSE_CLAF = 21,
159 SAS_PRIM_CLOSE_NORM = 22,
160 SAS_PRIM_CLOSE_R0 = 23,
161 SAS_PRIM_CLOSE_R1 = 24,
163 SAS_PRIM_OPEN_RTRY = 25,
164 SAS_PRIM_OPEN_RJCT = 26,
165 SAS_PRIM_OPEN_ACPT = 27,
171 SATA_PRIM_PMNAK = 34,
172 SATA_PRIM_PMACK = 35,
173 SATA_PRIM_PMREQ_S = 36,
174 SATA_PRIM_PMREQ_P = 37,
175 SATA_SATA_R_ERR = 38,
178 enum sas_open_rej_reason {
180 SAS_OREJ_UNKNOWN = 0,
181 SAS_OREJ_BAD_DEST = 1,
182 SAS_OREJ_CONN_RATE = 2,
184 SAS_OREJ_RESV_AB0 = 4,
185 SAS_OREJ_RESV_AB1 = 5,
186 SAS_OREJ_RESV_AB2 = 6,
187 SAS_OREJ_RESV_AB3 = 7,
188 SAS_OREJ_WRONG_DEST= 8,
189 SAS_OREJ_STP_NORES = 9,
192 SAS_OREJ_NO_DEST = 10,
193 SAS_OREJ_PATH_BLOCKED = 11,
194 SAS_OREJ_RSVD_CONT0 = 12,
195 SAS_OREJ_RSVD_CONT1 = 13,
196 SAS_OREJ_RSVD_INIT0 = 14,
197 SAS_OREJ_RSVD_INIT1 = 15,
198 SAS_OREJ_RSVD_STOP0 = 16,
199 SAS_OREJ_RSVD_STOP1 = 17,
200 SAS_OREJ_RSVD_RETRY = 18,
203 enum sas_gpio_reg_type {
204 SAS_GPIO_REG_CFG = 0,
206 SAS_GPIO_REG_RX_GP = 2,
208 SAS_GPIO_REG_TX_GP = 4,
211 struct dev_to_host_fis {
212 u8 fis_type; /* 0x34 */
218 union { u8 lbam; u8 byte_count_low; };
219 union { u8 lbah; u8 byte_count_high; };
227 union { u8 sector_count; u8 interrupt_reason; };
233 } __attribute__ ((packed));
235 struct host_to_dev_fis {
236 u8 fis_type; /* 0x27 */
242 union { u8 lbam; u8 byte_count_low; };
243 union { u8 lbah; u8 byte_count_high; };
251 union { u8 sector_count; u8 interrupt_reason; };
257 } __attribute__ ((packed));
259 /* Prefer to have code clarity over header file clarity.
261 #ifdef __LITTLE_ENDIAN_BITFIELD
262 struct sas_identify_frame {
299 u8 sas_addr[SAS_ADDR_SIZE];
307 } __attribute__ ((packed));
309 struct ssp_frame_hdr {
311 u8 hashed_dest_addr[HASHED_SAS_ADDR_SIZE];
313 u8 hashed_src_addr[HASHED_SAS_ADDR_SIZE];
316 u8 changing_data_ptr:1;
318 u8 retry_data_frames:1;
328 } __attribute__ ((packed));
330 struct ssp_response_iu {
340 __be32 sense_data_len;
341 __be32 response_data_len;
345 } __attribute__ ((packed));
347 struct ssp_command_iu {
367 } __attribute__ ((packed));
370 __be32 requested_offset;
371 __be32 write_data_len;
373 } __attribute__ ((packed));
382 } __attribute__ ((packed));
384 /* ---------- SMP ---------- */
386 struct report_general_resp {
388 __be16 route_indexes;
392 u8 conf_route_table:1;
395 u8 orej_retry_supp:1;
403 u8 enclosure_logical_id[8];
406 } __attribute__ ((packed));
408 struct discover_resp {
415 u8 attached_dev_type:3;
421 u8 attached_sata_host:1;
425 u8 attached_sata_dev:1;
428 u8 attached_sata_ps:1;
431 u8 attached_sas_addr[8];
455 } __attribute__ ((packed));
457 struct report_phy_sata_resp {
471 struct dev_to_host_fis fis;
475 u8 affil_stp_ini_addr[8];
478 } __attribute__ ((packed));
486 struct report_general_resp rg;
487 struct discover_resp disc;
488 struct report_phy_sata_resp rps;
490 } __attribute__ ((packed));
492 #elif defined(__BIG_ENDIAN_BITFIELD)
493 struct sas_identify_frame {
530 u8 sas_addr[SAS_ADDR_SIZE];
538 } __attribute__ ((packed));
540 struct ssp_frame_hdr {
542 u8 hashed_dest_addr[HASHED_SAS_ADDR_SIZE];
544 u8 hashed_src_addr[HASHED_SAS_ADDR_SIZE];
548 u8 retry_data_frames:1;
550 u8 changing_data_ptr:1;
559 } __attribute__ ((packed));
561 struct ssp_response_iu {
571 __be32 sense_data_len;
572 __be32 response_data_len;
576 } __attribute__ ((packed));
578 struct ssp_command_iu {
598 } __attribute__ ((packed));
601 __be32 requested_offset;
602 __be32 write_data_len;
604 } __attribute__ ((packed));
613 } __attribute__ ((packed));
615 /* ---------- SMP ---------- */
617 struct report_general_resp {
619 __be16 route_indexes;
627 u8 orej_retry_supp:1;
630 u8 conf_route_table:1;
634 u8 enclosure_logical_id[8];
637 } __attribute__ ((packed));
639 struct discover_resp {
646 u8 attached_dev_type:3;
654 u8 attached_sata_host:1;
656 u8 attached_sata_ps:1;
659 u8 attached_sata_dev:1;
662 u8 attached_sas_addr[8];
686 } __attribute__ ((packed));
688 struct report_phy_sata_resp {
702 struct dev_to_host_fis fis;
706 u8 affil_stp_ini_addr[8];
709 } __attribute__ ((packed));
717 struct report_general_resp rg;
718 struct discover_resp disc;
719 struct report_phy_sata_resp rps;
721 } __attribute__ ((packed));
724 #error "Bitfield order not defined!"