2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include "mlx5_ifc_fpga.h"
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
75 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
79 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
80 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
81 MLX5_CMD_OP_INIT_HCA = 0x102,
82 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
83 MLX5_CMD_OP_ENABLE_HCA = 0x104,
84 MLX5_CMD_OP_DISABLE_HCA = 0x105,
85 MLX5_CMD_OP_QUERY_PAGES = 0x107,
86 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
87 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
88 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
89 MLX5_CMD_OP_SET_ISSI = 0x10b,
90 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
91 MLX5_CMD_OP_CREATE_MKEY = 0x200,
92 MLX5_CMD_OP_QUERY_MKEY = 0x201,
93 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
94 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
95 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
96 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
97 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
98 MLX5_CMD_OP_CREATE_EQ = 0x301,
99 MLX5_CMD_OP_DESTROY_EQ = 0x302,
100 MLX5_CMD_OP_QUERY_EQ = 0x303,
101 MLX5_CMD_OP_GEN_EQE = 0x304,
102 MLX5_CMD_OP_CREATE_CQ = 0x400,
103 MLX5_CMD_OP_DESTROY_CQ = 0x401,
104 MLX5_CMD_OP_QUERY_CQ = 0x402,
105 MLX5_CMD_OP_MODIFY_CQ = 0x403,
106 MLX5_CMD_OP_CREATE_QP = 0x500,
107 MLX5_CMD_OP_DESTROY_QP = 0x501,
108 MLX5_CMD_OP_RST2INIT_QP = 0x502,
109 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
110 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
111 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
112 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
113 MLX5_CMD_OP_2ERR_QP = 0x507,
114 MLX5_CMD_OP_2RST_QP = 0x50a,
115 MLX5_CMD_OP_QUERY_QP = 0x50b,
116 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
117 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
118 MLX5_CMD_OP_CREATE_PSV = 0x600,
119 MLX5_CMD_OP_DESTROY_PSV = 0x601,
120 MLX5_CMD_OP_CREATE_SRQ = 0x700,
121 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
122 MLX5_CMD_OP_QUERY_SRQ = 0x702,
123 MLX5_CMD_OP_ARM_RQ = 0x703,
124 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
125 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
126 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
127 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
128 MLX5_CMD_OP_CREATE_DCT = 0x710,
129 MLX5_CMD_OP_DESTROY_DCT = 0x711,
130 MLX5_CMD_OP_DRAIN_DCT = 0x712,
131 MLX5_CMD_OP_QUERY_DCT = 0x713,
132 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
133 MLX5_CMD_OP_CREATE_XRQ = 0x717,
134 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
135 MLX5_CMD_OP_QUERY_XRQ = 0x719,
136 MLX5_CMD_OP_ARM_XRQ = 0x71a,
137 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
138 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
139 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
140 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
141 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
142 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
143 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
144 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
145 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
146 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
147 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
148 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
149 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
150 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
151 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
152 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
153 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
154 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
155 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
156 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
157 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
158 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
159 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
160 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
161 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
162 MLX5_CMD_OP_ALLOC_PD = 0x800,
163 MLX5_CMD_OP_DEALLOC_PD = 0x801,
164 MLX5_CMD_OP_ALLOC_UAR = 0x802,
165 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
166 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
167 MLX5_CMD_OP_ACCESS_REG = 0x805,
168 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
169 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
170 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
171 MLX5_CMD_OP_MAD_IFC = 0x50d,
172 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
173 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
174 MLX5_CMD_OP_NOP = 0x80d,
175 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
176 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
177 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
178 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
179 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
180 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
181 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
182 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
183 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
184 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
185 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
186 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
187 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
188 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
189 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
190 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
191 MLX5_CMD_OP_CREATE_LAG = 0x840,
192 MLX5_CMD_OP_MODIFY_LAG = 0x841,
193 MLX5_CMD_OP_QUERY_LAG = 0x842,
194 MLX5_CMD_OP_DESTROY_LAG = 0x843,
195 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
196 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
197 MLX5_CMD_OP_CREATE_TIR = 0x900,
198 MLX5_CMD_OP_MODIFY_TIR = 0x901,
199 MLX5_CMD_OP_DESTROY_TIR = 0x902,
200 MLX5_CMD_OP_QUERY_TIR = 0x903,
201 MLX5_CMD_OP_CREATE_SQ = 0x904,
202 MLX5_CMD_OP_MODIFY_SQ = 0x905,
203 MLX5_CMD_OP_DESTROY_SQ = 0x906,
204 MLX5_CMD_OP_QUERY_SQ = 0x907,
205 MLX5_CMD_OP_CREATE_RQ = 0x908,
206 MLX5_CMD_OP_MODIFY_RQ = 0x909,
207 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
208 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
209 MLX5_CMD_OP_QUERY_RQ = 0x90b,
210 MLX5_CMD_OP_CREATE_RMP = 0x90c,
211 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
212 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
213 MLX5_CMD_OP_QUERY_RMP = 0x90f,
214 MLX5_CMD_OP_CREATE_TIS = 0x912,
215 MLX5_CMD_OP_MODIFY_TIS = 0x913,
216 MLX5_CMD_OP_DESTROY_TIS = 0x914,
217 MLX5_CMD_OP_QUERY_TIS = 0x915,
218 MLX5_CMD_OP_CREATE_RQT = 0x916,
219 MLX5_CMD_OP_MODIFY_RQT = 0x917,
220 MLX5_CMD_OP_DESTROY_RQT = 0x918,
221 MLX5_CMD_OP_QUERY_RQT = 0x919,
222 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
223 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
224 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
225 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
226 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
227 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
228 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
229 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
230 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
231 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
232 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
233 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
234 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
235 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
236 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
237 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
238 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
239 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
240 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
241 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
242 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
243 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
244 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
248 struct mlx5_ifc_flow_table_fields_supported_bits {
251 u8 outer_ether_type[0x1];
252 u8 outer_ip_version[0x1];
253 u8 outer_first_prio[0x1];
254 u8 outer_first_cfi[0x1];
255 u8 outer_first_vid[0x1];
256 u8 outer_ipv4_ttl[0x1];
257 u8 outer_second_prio[0x1];
258 u8 outer_second_cfi[0x1];
259 u8 outer_second_vid[0x1];
260 u8 reserved_at_b[0x1];
264 u8 outer_ip_protocol[0x1];
265 u8 outer_ip_ecn[0x1];
266 u8 outer_ip_dscp[0x1];
267 u8 outer_udp_sport[0x1];
268 u8 outer_udp_dport[0x1];
269 u8 outer_tcp_sport[0x1];
270 u8 outer_tcp_dport[0x1];
271 u8 outer_tcp_flags[0x1];
272 u8 outer_gre_protocol[0x1];
273 u8 outer_gre_key[0x1];
274 u8 outer_vxlan_vni[0x1];
275 u8 reserved_at_1a[0x5];
276 u8 source_eswitch_port[0x1];
280 u8 inner_ether_type[0x1];
281 u8 inner_ip_version[0x1];
282 u8 inner_first_prio[0x1];
283 u8 inner_first_cfi[0x1];
284 u8 inner_first_vid[0x1];
285 u8 reserved_at_27[0x1];
286 u8 inner_second_prio[0x1];
287 u8 inner_second_cfi[0x1];
288 u8 inner_second_vid[0x1];
289 u8 reserved_at_2b[0x1];
293 u8 inner_ip_protocol[0x1];
294 u8 inner_ip_ecn[0x1];
295 u8 inner_ip_dscp[0x1];
296 u8 inner_udp_sport[0x1];
297 u8 inner_udp_dport[0x1];
298 u8 inner_tcp_sport[0x1];
299 u8 inner_tcp_dport[0x1];
300 u8 inner_tcp_flags[0x1];
301 u8 reserved_at_37[0x9];
303 u8 reserved_at_40[0x5];
304 u8 outer_first_mpls_over_udp[0x4];
305 u8 outer_first_mpls_over_gre[0x4];
306 u8 inner_first_mpls[0x4];
307 u8 outer_first_mpls[0x4];
308 u8 reserved_at_55[0x2];
309 u8 outer_esp_spi[0x1];
310 u8 reserved_at_58[0x2];
313 u8 reserved_at_5b[0x25];
316 struct mlx5_ifc_flow_table_prop_layout_bits {
318 u8 reserved_at_1[0x1];
319 u8 flow_counter[0x1];
320 u8 flow_modify_en[0x1];
322 u8 identified_miss_table_mode[0x1];
323 u8 flow_table_modify[0x1];
326 u8 reserved_at_9[0x1];
329 u8 reserved_at_c[0x14];
331 u8 reserved_at_20[0x2];
332 u8 log_max_ft_size[0x6];
333 u8 log_max_modify_header_context[0x8];
334 u8 max_modify_header_actions[0x8];
335 u8 max_ft_level[0x8];
337 u8 reserved_at_40[0x20];
339 u8 reserved_at_60[0x18];
340 u8 log_max_ft_num[0x8];
342 u8 reserved_at_80[0x18];
343 u8 log_max_destination[0x8];
345 u8 log_max_flow_counter[0x8];
346 u8 reserved_at_a8[0x10];
347 u8 log_max_flow[0x8];
349 u8 reserved_at_c0[0x40];
351 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
353 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
356 struct mlx5_ifc_odp_per_transport_service_cap_bits {
363 u8 reserved_at_6[0x1a];
366 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
391 u8 reserved_at_c0[0x18];
392 u8 ttl_hoplimit[0x8];
397 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
399 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
402 struct mlx5_ifc_fte_match_set_misc_bits {
403 u8 reserved_at_0[0x8];
406 u8 source_eswitch_owner_vhca_id[0x10];
407 u8 source_port[0x10];
409 u8 outer_second_prio[0x3];
410 u8 outer_second_cfi[0x1];
411 u8 outer_second_vid[0xc];
412 u8 inner_second_prio[0x3];
413 u8 inner_second_cfi[0x1];
414 u8 inner_second_vid[0xc];
416 u8 outer_second_cvlan_tag[0x1];
417 u8 inner_second_cvlan_tag[0x1];
418 u8 outer_second_svlan_tag[0x1];
419 u8 inner_second_svlan_tag[0x1];
420 u8 reserved_at_64[0xc];
421 u8 gre_protocol[0x10];
427 u8 reserved_at_b8[0x8];
429 u8 reserved_at_c0[0x20];
431 u8 reserved_at_e0[0xc];
432 u8 outer_ipv6_flow_label[0x14];
434 u8 reserved_at_100[0xc];
435 u8 inner_ipv6_flow_label[0x14];
437 u8 reserved_at_120[0x28];
439 u8 reserved_at_160[0x20];
440 u8 outer_esp_spi[0x20];
441 u8 reserved_at_1a0[0x60];
444 struct mlx5_ifc_fte_match_mpls_bits {
451 struct mlx5_ifc_fte_match_set_misc2_bits {
452 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
454 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
456 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
458 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
460 u8 reserved_at_80[0x100];
462 u8 metadata_reg_a[0x20];
464 u8 reserved_at_1a0[0x60];
467 struct mlx5_ifc_cmd_pas_bits {
471 u8 reserved_at_34[0xc];
474 struct mlx5_ifc_uint64_bits {
481 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
482 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
483 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
484 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
485 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
486 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
487 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
488 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
489 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
490 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
493 struct mlx5_ifc_ads_bits {
496 u8 reserved_at_2[0xe];
499 u8 reserved_at_20[0x8];
505 u8 reserved_at_45[0x3];
506 u8 src_addr_index[0x8];
507 u8 reserved_at_50[0x4];
511 u8 reserved_at_60[0x4];
515 u8 rgid_rip[16][0x8];
517 u8 reserved_at_100[0x4];
520 u8 reserved_at_106[0x1];
529 u8 vhca_port_num[0x8];
535 struct mlx5_ifc_flow_table_nic_cap_bits {
536 u8 nic_rx_multi_path_tirs[0x1];
537 u8 nic_rx_multi_path_tirs_fts[0x1];
538 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
539 u8 reserved_at_3[0x1fd];
541 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
543 u8 reserved_at_400[0x200];
545 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
547 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
549 u8 reserved_at_a00[0x200];
551 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
553 u8 reserved_at_e00[0x7200];
556 struct mlx5_ifc_flow_table_eswitch_cap_bits {
557 u8 reserved_at_0[0x1c];
558 u8 fdb_multi_path_to_table[0x1];
559 u8 reserved_at_1d[0x1e3];
561 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
563 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
565 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
567 u8 reserved_at_800[0x7800];
570 struct mlx5_ifc_e_switch_cap_bits {
571 u8 vport_svlan_strip[0x1];
572 u8 vport_cvlan_strip[0x1];
573 u8 vport_svlan_insert[0x1];
574 u8 vport_cvlan_insert_if_not_exist[0x1];
575 u8 vport_cvlan_insert_overwrite[0x1];
576 u8 reserved_at_5[0x18];
577 u8 merged_eswitch[0x1];
578 u8 nic_vport_node_guid_modify[0x1];
579 u8 nic_vport_port_guid_modify[0x1];
581 u8 vxlan_encap_decap[0x1];
582 u8 nvgre_encap_decap[0x1];
583 u8 reserved_at_22[0x9];
584 u8 log_max_encap_headers[0x5];
586 u8 max_encap_header_size[0xa];
588 u8 reserved_40[0x7c0];
592 struct mlx5_ifc_qos_cap_bits {
593 u8 packet_pacing[0x1];
594 u8 esw_scheduling[0x1];
595 u8 esw_bw_share[0x1];
596 u8 esw_rate_limit[0x1];
597 u8 reserved_at_4[0x1];
598 u8 packet_pacing_burst_bound[0x1];
599 u8 packet_pacing_typical_size[0x1];
600 u8 reserved_at_7[0x19];
602 u8 reserved_at_20[0x20];
604 u8 packet_pacing_max_rate[0x20];
606 u8 packet_pacing_min_rate[0x20];
608 u8 reserved_at_80[0x10];
609 u8 packet_pacing_rate_table_size[0x10];
611 u8 esw_element_type[0x10];
612 u8 esw_tsar_type[0x10];
614 u8 reserved_at_c0[0x10];
615 u8 max_qos_para_vport[0x10];
617 u8 max_tsar_bw_share[0x20];
619 u8 reserved_at_100[0x700];
622 struct mlx5_ifc_debug_cap_bits {
623 u8 reserved_at_0[0x20];
625 u8 reserved_at_20[0x2];
626 u8 stall_detect[0x1];
627 u8 reserved_at_23[0x1d];
629 u8 reserved_at_40[0x7c0];
632 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
636 u8 lro_psh_flag[0x1];
637 u8 lro_time_stamp[0x1];
638 u8 reserved_at_5[0x2];
639 u8 wqe_vlan_insert[0x1];
640 u8 self_lb_en_modifiable[0x1];
641 u8 reserved_at_9[0x2];
643 u8 multi_pkt_send_wqe[0x2];
644 u8 wqe_inline_mode[0x2];
645 u8 rss_ind_tbl_cap[0x4];
648 u8 enhanced_multi_pkt_send_wqe[0x1];
649 u8 tunnel_lso_const_out_ip_id[0x1];
650 u8 reserved_at_1c[0x2];
651 u8 tunnel_stateless_gre[0x1];
652 u8 tunnel_stateless_vxlan[0x1];
657 u8 reserved_at_23[0x1b];
658 u8 max_geneve_opt_len[0x1];
659 u8 tunnel_stateless_geneve_rx[0x1];
661 u8 reserved_at_40[0x10];
662 u8 lro_min_mss_size[0x10];
664 u8 reserved_at_60[0x120];
666 u8 lro_timer_supported_periods[4][0x20];
668 u8 reserved_at_200[0x600];
671 struct mlx5_ifc_roce_cap_bits {
673 u8 reserved_at_1[0x1f];
675 u8 reserved_at_20[0x60];
677 u8 reserved_at_80[0xc];
679 u8 reserved_at_90[0x8];
680 u8 roce_version[0x8];
682 u8 reserved_at_a0[0x10];
683 u8 r_roce_dest_udp_port[0x10];
685 u8 r_roce_max_src_udp_port[0x10];
686 u8 r_roce_min_src_udp_port[0x10];
688 u8 reserved_at_e0[0x10];
689 u8 roce_address_table_size[0x10];
691 u8 reserved_at_100[0x700];
694 struct mlx5_ifc_device_mem_cap_bits {
696 u8 reserved_at_1[0x1f];
698 u8 reserved_at_20[0xb];
699 u8 log_min_memic_alloc_size[0x5];
700 u8 reserved_at_30[0x8];
701 u8 log_max_memic_addr_alignment[0x8];
703 u8 memic_bar_start_addr[0x40];
705 u8 memic_bar_size[0x20];
707 u8 max_memic_size[0x20];
709 u8 reserved_at_c0[0x740];
713 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
714 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
715 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
716 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
717 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
718 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
719 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
720 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
721 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
725 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
726 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
727 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
728 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
729 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
730 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
731 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
732 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
733 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
736 struct mlx5_ifc_atomic_caps_bits {
737 u8 reserved_at_0[0x40];
739 u8 atomic_req_8B_endianness_mode[0x2];
740 u8 reserved_at_42[0x4];
741 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
743 u8 reserved_at_47[0x19];
745 u8 reserved_at_60[0x20];
747 u8 reserved_at_80[0x10];
748 u8 atomic_operations[0x10];
750 u8 reserved_at_a0[0x10];
751 u8 atomic_size_qp[0x10];
753 u8 reserved_at_c0[0x10];
754 u8 atomic_size_dc[0x10];
756 u8 reserved_at_e0[0x720];
759 struct mlx5_ifc_odp_cap_bits {
760 u8 reserved_at_0[0x40];
763 u8 reserved_at_41[0x1f];
765 u8 reserved_at_60[0x20];
767 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
769 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
771 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
773 u8 reserved_at_e0[0x720];
776 struct mlx5_ifc_calc_op {
777 u8 reserved_at_0[0x10];
778 u8 reserved_at_10[0x9];
779 u8 op_swap_endianness[0x1];
788 struct mlx5_ifc_vector_calc_cap_bits {
790 u8 reserved_at_1[0x1f];
791 u8 reserved_at_20[0x8];
792 u8 max_vec_count[0x8];
793 u8 reserved_at_30[0xd];
794 u8 max_chunk_size[0x3];
795 struct mlx5_ifc_calc_op calc0;
796 struct mlx5_ifc_calc_op calc1;
797 struct mlx5_ifc_calc_op calc2;
798 struct mlx5_ifc_calc_op calc3;
800 u8 reserved_at_e0[0x720];
804 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
805 MLX5_WQ_TYPE_CYCLIC = 0x1,
806 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
807 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
811 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
812 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
816 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
817 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
818 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
819 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
820 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
824 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
825 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
826 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
827 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
828 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
829 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
833 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
834 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
838 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
839 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
840 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
844 MLX5_CAP_PORT_TYPE_IB = 0x0,
845 MLX5_CAP_PORT_TYPE_ETH = 0x1,
849 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
850 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
851 MLX5_CAP_UMR_FENCE_NONE = 0x2,
854 struct mlx5_ifc_cmd_hca_cap_bits {
855 u8 reserved_at_0[0x30];
858 u8 reserved_at_40[0x40];
860 u8 log_max_srq_sz[0x8];
861 u8 log_max_qp_sz[0x8];
862 u8 reserved_at_90[0xb];
865 u8 reserved_at_a0[0xb];
867 u8 reserved_at_b0[0x10];
869 u8 reserved_at_c0[0x8];
870 u8 log_max_cq_sz[0x8];
871 u8 reserved_at_d0[0xb];
874 u8 log_max_eq_sz[0x8];
875 u8 reserved_at_e8[0x2];
876 u8 log_max_mkey[0x6];
877 u8 reserved_at_f0[0xc];
880 u8 max_indirection[0x8];
881 u8 fixed_buffer_size[0x1];
882 u8 log_max_mrw_sz[0x7];
883 u8 force_teardown[0x1];
884 u8 reserved_at_111[0x1];
885 u8 log_max_bsf_list_size[0x6];
886 u8 umr_extended_translation_offset[0x1];
888 u8 log_max_klm_list_size[0x6];
890 u8 reserved_at_120[0xa];
891 u8 log_max_ra_req_dc[0x6];
892 u8 reserved_at_130[0xa];
893 u8 log_max_ra_res_dc[0x6];
895 u8 reserved_at_140[0xa];
896 u8 log_max_ra_req_qp[0x6];
897 u8 reserved_at_150[0xa];
898 u8 log_max_ra_res_qp[0x6];
901 u8 cc_query_allowed[0x1];
902 u8 cc_modify_allowed[0x1];
904 u8 cache_line_128byte[0x1];
905 u8 reserved_at_165[0xa];
907 u8 gid_table_size[0x10];
909 u8 out_of_seq_cnt[0x1];
910 u8 vport_counters[0x1];
911 u8 retransmission_q_counters[0x1];
913 u8 modify_rq_counter_set_id[0x1];
914 u8 rq_delay_drop[0x1];
916 u8 pkey_table_size[0x10];
918 u8 vport_group_manager[0x1];
919 u8 vhca_group_manager[0x1];
922 u8 vnic_env_queue_counters[0x1];
924 u8 nic_flow_table[0x1];
925 u8 eswitch_manager[0x1];
926 u8 device_memory[0x1];
929 u8 local_ca_ack_delay[0x5];
930 u8 port_module_event[0x1];
931 u8 enhanced_error_q_counters[0x1];
933 u8 reserved_at_1b3[0x1];
934 u8 disable_link_up[0x1];
939 u8 reserved_at_1c0[0x1];
943 u8 reserved_at_1c8[0x4];
945 u8 temp_warn_event[0x1];
947 u8 general_notification_event[0x1];
948 u8 reserved_at_1d3[0x2];
952 u8 reserved_at_1d8[0x1];
961 u8 stat_rate_support[0x10];
962 u8 reserved_at_1f0[0xc];
965 u8 compact_address_vector[0x1];
967 u8 reserved_at_202[0x1];
968 u8 ipoib_enhanced_offloads[0x1];
969 u8 ipoib_basic_offloads[0x1];
970 u8 reserved_at_205[0x1];
971 u8 repeated_block_disabled[0x1];
972 u8 umr_modify_entity_size_disabled[0x1];
973 u8 umr_modify_atomic_disabled[0x1];
974 u8 umr_indirect_mkey_disabled[0x1];
976 u8 reserved_at_20c[0x3];
977 u8 drain_sigerr[0x1];
978 u8 cmdif_checksum[0x2];
980 u8 reserved_at_213[0x1];
981 u8 wq_signature[0x1];
982 u8 sctr_data_cqe[0x1];
983 u8 reserved_at_216[0x1];
989 u8 eth_net_offloads[0x1];
992 u8 reserved_at_21f[0x1];
996 u8 cq_moderation[0x1];
997 u8 reserved_at_223[0x3];
1000 u8 block_lb_mc[0x1];
1001 u8 reserved_at_229[0x1];
1002 u8 scqe_break_moderation[0x1];
1003 u8 cq_period_start_from_cqe[0x1];
1005 u8 reserved_at_22d[0x1];
1007 u8 vector_calc[0x1];
1008 u8 umr_ptr_rlky[0x1];
1010 u8 reserved_at_232[0x4];
1013 u8 set_deth_sqpn[0x1];
1014 u8 reserved_at_239[0x3];
1021 u8 reserved_at_241[0x9];
1023 u8 reserved_at_250[0x8];
1027 u8 driver_version[0x1];
1028 u8 pad_tx_eth_packet[0x1];
1029 u8 reserved_at_263[0x8];
1030 u8 log_bf_reg_size[0x5];
1032 u8 reserved_at_270[0xb];
1034 u8 num_lag_ports[0x4];
1036 u8 reserved_at_280[0x10];
1037 u8 max_wqe_sz_sq[0x10];
1039 u8 reserved_at_2a0[0x10];
1040 u8 max_wqe_sz_rq[0x10];
1042 u8 max_flow_counter_31_16[0x10];
1043 u8 max_wqe_sz_sq_dc[0x10];
1045 u8 reserved_at_2e0[0x7];
1046 u8 max_qp_mcg[0x19];
1048 u8 reserved_at_300[0x18];
1049 u8 log_max_mcg[0x8];
1051 u8 reserved_at_320[0x3];
1052 u8 log_max_transport_domain[0x5];
1053 u8 reserved_at_328[0x3];
1055 u8 reserved_at_330[0xb];
1056 u8 log_max_xrcd[0x5];
1058 u8 nic_receive_steering_discard[0x1];
1059 u8 receive_discard_vport_down[0x1];
1060 u8 transmit_discard_vport_down[0x1];
1061 u8 reserved_at_343[0x5];
1062 u8 log_max_flow_counter_bulk[0x8];
1063 u8 max_flow_counter_15_0[0x10];
1066 u8 reserved_at_360[0x3];
1068 u8 reserved_at_368[0x3];
1070 u8 reserved_at_370[0x3];
1071 u8 log_max_tir[0x5];
1072 u8 reserved_at_378[0x3];
1073 u8 log_max_tis[0x5];
1075 u8 basic_cyclic_rcv_wqe[0x1];
1076 u8 reserved_at_381[0x2];
1077 u8 log_max_rmp[0x5];
1078 u8 reserved_at_388[0x3];
1079 u8 log_max_rqt[0x5];
1080 u8 reserved_at_390[0x3];
1081 u8 log_max_rqt_size[0x5];
1082 u8 reserved_at_398[0x3];
1083 u8 log_max_tis_per_sq[0x5];
1085 u8 ext_stride_num_range[0x1];
1086 u8 reserved_at_3a1[0x2];
1087 u8 log_max_stride_sz_rq[0x5];
1088 u8 reserved_at_3a8[0x3];
1089 u8 log_min_stride_sz_rq[0x5];
1090 u8 reserved_at_3b0[0x3];
1091 u8 log_max_stride_sz_sq[0x5];
1092 u8 reserved_at_3b8[0x3];
1093 u8 log_min_stride_sz_sq[0x5];
1096 u8 reserved_at_3c1[0x2];
1097 u8 log_max_hairpin_queues[0x5];
1098 u8 reserved_at_3c8[0x3];
1099 u8 log_max_hairpin_wq_data_sz[0x5];
1100 u8 reserved_at_3d0[0x3];
1101 u8 log_max_hairpin_num_packets[0x5];
1102 u8 reserved_at_3d8[0x3];
1103 u8 log_max_wq_sz[0x5];
1105 u8 nic_vport_change_event[0x1];
1106 u8 disable_local_lb_uc[0x1];
1107 u8 disable_local_lb_mc[0x1];
1108 u8 log_min_hairpin_wq_data_sz[0x5];
1109 u8 reserved_at_3e8[0x3];
1110 u8 log_max_vlan_list[0x5];
1111 u8 reserved_at_3f0[0x3];
1112 u8 log_max_current_mc_list[0x5];
1113 u8 reserved_at_3f8[0x3];
1114 u8 log_max_current_uc_list[0x5];
1116 u8 reserved_at_400[0x80];
1118 u8 reserved_at_480[0x3];
1119 u8 log_max_l2_table[0x5];
1120 u8 reserved_at_488[0x8];
1121 u8 log_uar_page_sz[0x10];
1123 u8 reserved_at_4a0[0x20];
1124 u8 device_frequency_mhz[0x20];
1125 u8 device_frequency_khz[0x20];
1127 u8 reserved_at_500[0x20];
1128 u8 num_of_uars_per_page[0x20];
1130 u8 flex_parser_protocols[0x20];
1131 u8 reserved_at_560[0x20];
1133 u8 reserved_at_580[0x3c];
1134 u8 mini_cqe_resp_stride_index[0x1];
1135 u8 cqe_128_always[0x1];
1136 u8 cqe_compression_128[0x1];
1137 u8 cqe_compression[0x1];
1139 u8 cqe_compression_timeout[0x10];
1140 u8 cqe_compression_max_num[0x10];
1142 u8 reserved_at_5e0[0x10];
1143 u8 tag_matching[0x1];
1144 u8 rndv_offload_rc[0x1];
1145 u8 rndv_offload_dc[0x1];
1146 u8 log_tag_matching_list_sz[0x5];
1147 u8 reserved_at_5f8[0x3];
1148 u8 log_max_xrq[0x5];
1150 u8 affiliate_nic_vport_criteria[0x8];
1151 u8 native_port_num[0x8];
1152 u8 num_vhca_ports[0x8];
1153 u8 reserved_at_618[0x6];
1154 u8 sw_owner_id[0x1];
1155 u8 reserved_at_61f[0x1e1];
1158 enum mlx5_flow_destination_type {
1159 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1160 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1161 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1163 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
1164 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1167 struct mlx5_ifc_dest_format_struct_bits {
1168 u8 destination_type[0x8];
1169 u8 destination_id[0x18];
1170 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1171 u8 reserved_at_21[0xf];
1172 u8 destination_eswitch_owner_vhca_id[0x10];
1175 struct mlx5_ifc_flow_counter_list_bits {
1176 u8 flow_counter_id[0x20];
1178 u8 reserved_at_20[0x20];
1181 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1182 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1183 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1184 u8 reserved_at_0[0x40];
1187 struct mlx5_ifc_fte_match_param_bits {
1188 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1190 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1192 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1194 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1196 u8 reserved_at_800[0x800];
1200 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1201 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1202 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1203 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1204 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1207 struct mlx5_ifc_rx_hash_field_select_bits {
1208 u8 l3_prot_type[0x1];
1209 u8 l4_prot_type[0x1];
1210 u8 selected_fields[0x1e];
1214 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1215 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1219 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1220 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1223 struct mlx5_ifc_wq_bits {
1225 u8 wq_signature[0x1];
1226 u8 end_padding_mode[0x2];
1228 u8 reserved_at_8[0x18];
1230 u8 hds_skip_first_sge[0x1];
1231 u8 log2_hds_buf_size[0x3];
1232 u8 reserved_at_24[0x7];
1233 u8 page_offset[0x5];
1236 u8 reserved_at_40[0x8];
1239 u8 reserved_at_60[0x8];
1244 u8 hw_counter[0x20];
1246 u8 sw_counter[0x20];
1248 u8 reserved_at_100[0xc];
1249 u8 log_wq_stride[0x4];
1250 u8 reserved_at_110[0x3];
1251 u8 log_wq_pg_sz[0x5];
1252 u8 reserved_at_118[0x3];
1255 u8 reserved_at_120[0x3];
1256 u8 log_hairpin_num_packets[0x5];
1257 u8 reserved_at_128[0x3];
1258 u8 log_hairpin_data_sz[0x5];
1260 u8 reserved_at_130[0x4];
1261 u8 log_wqe_num_of_strides[0x4];
1262 u8 two_byte_shift_en[0x1];
1263 u8 reserved_at_139[0x4];
1264 u8 log_wqe_stride_size[0x3];
1266 u8 reserved_at_140[0x4c0];
1268 struct mlx5_ifc_cmd_pas_bits pas[0];
1271 struct mlx5_ifc_rq_num_bits {
1272 u8 reserved_at_0[0x8];
1276 struct mlx5_ifc_mac_address_layout_bits {
1277 u8 reserved_at_0[0x10];
1278 u8 mac_addr_47_32[0x10];
1280 u8 mac_addr_31_0[0x20];
1283 struct mlx5_ifc_vlan_layout_bits {
1284 u8 reserved_at_0[0x14];
1287 u8 reserved_at_20[0x20];
1290 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1291 u8 reserved_at_0[0xa0];
1293 u8 min_time_between_cnps[0x20];
1295 u8 reserved_at_c0[0x12];
1297 u8 reserved_at_d8[0x4];
1298 u8 cnp_prio_mode[0x1];
1299 u8 cnp_802p_prio[0x3];
1301 u8 reserved_at_e0[0x720];
1304 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1305 u8 reserved_at_0[0x60];
1307 u8 reserved_at_60[0x4];
1308 u8 clamp_tgt_rate[0x1];
1309 u8 reserved_at_65[0x3];
1310 u8 clamp_tgt_rate_after_time_inc[0x1];
1311 u8 reserved_at_69[0x17];
1313 u8 reserved_at_80[0x20];
1315 u8 rpg_time_reset[0x20];
1317 u8 rpg_byte_reset[0x20];
1319 u8 rpg_threshold[0x20];
1321 u8 rpg_max_rate[0x20];
1323 u8 rpg_ai_rate[0x20];
1325 u8 rpg_hai_rate[0x20];
1329 u8 rpg_min_dec_fac[0x20];
1331 u8 rpg_min_rate[0x20];
1333 u8 reserved_at_1c0[0xe0];
1335 u8 rate_to_set_on_first_cnp[0x20];
1339 u8 dce_tcp_rtt[0x20];
1341 u8 rate_reduce_monitor_period[0x20];
1343 u8 reserved_at_320[0x20];
1345 u8 initial_alpha_value[0x20];
1347 u8 reserved_at_360[0x4a0];
1350 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1351 u8 reserved_at_0[0x80];
1353 u8 rppp_max_rps[0x20];
1355 u8 rpg_time_reset[0x20];
1357 u8 rpg_byte_reset[0x20];
1359 u8 rpg_threshold[0x20];
1361 u8 rpg_max_rate[0x20];
1363 u8 rpg_ai_rate[0x20];
1365 u8 rpg_hai_rate[0x20];
1369 u8 rpg_min_dec_fac[0x20];
1371 u8 rpg_min_rate[0x20];
1373 u8 reserved_at_1c0[0x640];
1377 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1378 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1379 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1382 struct mlx5_ifc_resize_field_select_bits {
1383 u8 resize_field_select[0x20];
1387 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1388 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1389 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1390 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1393 struct mlx5_ifc_modify_field_select_bits {
1394 u8 modify_field_select[0x20];
1397 struct mlx5_ifc_field_select_r_roce_np_bits {
1398 u8 field_select_r_roce_np[0x20];
1401 struct mlx5_ifc_field_select_r_roce_rp_bits {
1402 u8 field_select_r_roce_rp[0x20];
1406 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1407 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1408 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1409 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1410 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1411 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1412 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1413 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1414 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1415 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1418 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1419 u8 field_select_8021qaurp[0x20];
1422 struct mlx5_ifc_phys_layer_cntrs_bits {
1423 u8 time_since_last_clear_high[0x20];
1425 u8 time_since_last_clear_low[0x20];
1427 u8 symbol_errors_high[0x20];
1429 u8 symbol_errors_low[0x20];
1431 u8 sync_headers_errors_high[0x20];
1433 u8 sync_headers_errors_low[0x20];
1435 u8 edpl_bip_errors_lane0_high[0x20];
1437 u8 edpl_bip_errors_lane0_low[0x20];
1439 u8 edpl_bip_errors_lane1_high[0x20];
1441 u8 edpl_bip_errors_lane1_low[0x20];
1443 u8 edpl_bip_errors_lane2_high[0x20];
1445 u8 edpl_bip_errors_lane2_low[0x20];
1447 u8 edpl_bip_errors_lane3_high[0x20];
1449 u8 edpl_bip_errors_lane3_low[0x20];
1451 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1453 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1455 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1457 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1459 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1461 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1463 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1465 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1467 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1469 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1471 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1473 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1475 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1477 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1479 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1481 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1483 u8 rs_fec_corrected_blocks_high[0x20];
1485 u8 rs_fec_corrected_blocks_low[0x20];
1487 u8 rs_fec_uncorrectable_blocks_high[0x20];
1489 u8 rs_fec_uncorrectable_blocks_low[0x20];
1491 u8 rs_fec_no_errors_blocks_high[0x20];
1493 u8 rs_fec_no_errors_blocks_low[0x20];
1495 u8 rs_fec_single_error_blocks_high[0x20];
1497 u8 rs_fec_single_error_blocks_low[0x20];
1499 u8 rs_fec_corrected_symbols_total_high[0x20];
1501 u8 rs_fec_corrected_symbols_total_low[0x20];
1503 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1505 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1507 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1509 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1511 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1513 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1515 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1517 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1519 u8 link_down_events[0x20];
1521 u8 successful_recovery_events[0x20];
1523 u8 reserved_at_640[0x180];
1526 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1527 u8 time_since_last_clear_high[0x20];
1529 u8 time_since_last_clear_low[0x20];
1531 u8 phy_received_bits_high[0x20];
1533 u8 phy_received_bits_low[0x20];
1535 u8 phy_symbol_errors_high[0x20];
1537 u8 phy_symbol_errors_low[0x20];
1539 u8 phy_corrected_bits_high[0x20];
1541 u8 phy_corrected_bits_low[0x20];
1543 u8 phy_corrected_bits_lane0_high[0x20];
1545 u8 phy_corrected_bits_lane0_low[0x20];
1547 u8 phy_corrected_bits_lane1_high[0x20];
1549 u8 phy_corrected_bits_lane1_low[0x20];
1551 u8 phy_corrected_bits_lane2_high[0x20];
1553 u8 phy_corrected_bits_lane2_low[0x20];
1555 u8 phy_corrected_bits_lane3_high[0x20];
1557 u8 phy_corrected_bits_lane3_low[0x20];
1559 u8 reserved_at_200[0x5c0];
1562 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1563 u8 symbol_error_counter[0x10];
1565 u8 link_error_recovery_counter[0x8];
1567 u8 link_downed_counter[0x8];
1569 u8 port_rcv_errors[0x10];
1571 u8 port_rcv_remote_physical_errors[0x10];
1573 u8 port_rcv_switch_relay_errors[0x10];
1575 u8 port_xmit_discards[0x10];
1577 u8 port_xmit_constraint_errors[0x8];
1579 u8 port_rcv_constraint_errors[0x8];
1581 u8 reserved_at_70[0x8];
1583 u8 link_overrun_errors[0x8];
1585 u8 reserved_at_80[0x10];
1587 u8 vl_15_dropped[0x10];
1589 u8 reserved_at_a0[0x80];
1591 u8 port_xmit_wait[0x20];
1594 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1595 u8 transmit_queue_high[0x20];
1597 u8 transmit_queue_low[0x20];
1599 u8 reserved_at_40[0x780];
1602 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1603 u8 rx_octets_high[0x20];
1605 u8 rx_octets_low[0x20];
1607 u8 reserved_at_40[0xc0];
1609 u8 rx_frames_high[0x20];
1611 u8 rx_frames_low[0x20];
1613 u8 tx_octets_high[0x20];
1615 u8 tx_octets_low[0x20];
1617 u8 reserved_at_180[0xc0];
1619 u8 tx_frames_high[0x20];
1621 u8 tx_frames_low[0x20];
1623 u8 rx_pause_high[0x20];
1625 u8 rx_pause_low[0x20];
1627 u8 rx_pause_duration_high[0x20];
1629 u8 rx_pause_duration_low[0x20];
1631 u8 tx_pause_high[0x20];
1633 u8 tx_pause_low[0x20];
1635 u8 tx_pause_duration_high[0x20];
1637 u8 tx_pause_duration_low[0x20];
1639 u8 rx_pause_transition_high[0x20];
1641 u8 rx_pause_transition_low[0x20];
1643 u8 reserved_at_3c0[0x40];
1645 u8 device_stall_minor_watermark_cnt_high[0x20];
1647 u8 device_stall_minor_watermark_cnt_low[0x20];
1649 u8 device_stall_critical_watermark_cnt_high[0x20];
1651 u8 device_stall_critical_watermark_cnt_low[0x20];
1653 u8 reserved_at_480[0x340];
1656 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1657 u8 port_transmit_wait_high[0x20];
1659 u8 port_transmit_wait_low[0x20];
1661 u8 reserved_at_40[0x100];
1663 u8 rx_buffer_almost_full_high[0x20];
1665 u8 rx_buffer_almost_full_low[0x20];
1667 u8 rx_buffer_full_high[0x20];
1669 u8 rx_buffer_full_low[0x20];
1671 u8 reserved_at_1c0[0x600];
1674 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1675 u8 dot3stats_alignment_errors_high[0x20];
1677 u8 dot3stats_alignment_errors_low[0x20];
1679 u8 dot3stats_fcs_errors_high[0x20];
1681 u8 dot3stats_fcs_errors_low[0x20];
1683 u8 dot3stats_single_collision_frames_high[0x20];
1685 u8 dot3stats_single_collision_frames_low[0x20];
1687 u8 dot3stats_multiple_collision_frames_high[0x20];
1689 u8 dot3stats_multiple_collision_frames_low[0x20];
1691 u8 dot3stats_sqe_test_errors_high[0x20];
1693 u8 dot3stats_sqe_test_errors_low[0x20];
1695 u8 dot3stats_deferred_transmissions_high[0x20];
1697 u8 dot3stats_deferred_transmissions_low[0x20];
1699 u8 dot3stats_late_collisions_high[0x20];
1701 u8 dot3stats_late_collisions_low[0x20];
1703 u8 dot3stats_excessive_collisions_high[0x20];
1705 u8 dot3stats_excessive_collisions_low[0x20];
1707 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1709 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1711 u8 dot3stats_carrier_sense_errors_high[0x20];
1713 u8 dot3stats_carrier_sense_errors_low[0x20];
1715 u8 dot3stats_frame_too_longs_high[0x20];
1717 u8 dot3stats_frame_too_longs_low[0x20];
1719 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1721 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1723 u8 dot3stats_symbol_errors_high[0x20];
1725 u8 dot3stats_symbol_errors_low[0x20];
1727 u8 dot3control_in_unknown_opcodes_high[0x20];
1729 u8 dot3control_in_unknown_opcodes_low[0x20];
1731 u8 dot3in_pause_frames_high[0x20];
1733 u8 dot3in_pause_frames_low[0x20];
1735 u8 dot3out_pause_frames_high[0x20];
1737 u8 dot3out_pause_frames_low[0x20];
1739 u8 reserved_at_400[0x3c0];
1742 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1743 u8 ether_stats_drop_events_high[0x20];
1745 u8 ether_stats_drop_events_low[0x20];
1747 u8 ether_stats_octets_high[0x20];
1749 u8 ether_stats_octets_low[0x20];
1751 u8 ether_stats_pkts_high[0x20];
1753 u8 ether_stats_pkts_low[0x20];
1755 u8 ether_stats_broadcast_pkts_high[0x20];
1757 u8 ether_stats_broadcast_pkts_low[0x20];
1759 u8 ether_stats_multicast_pkts_high[0x20];
1761 u8 ether_stats_multicast_pkts_low[0x20];
1763 u8 ether_stats_crc_align_errors_high[0x20];
1765 u8 ether_stats_crc_align_errors_low[0x20];
1767 u8 ether_stats_undersize_pkts_high[0x20];
1769 u8 ether_stats_undersize_pkts_low[0x20];
1771 u8 ether_stats_oversize_pkts_high[0x20];
1773 u8 ether_stats_oversize_pkts_low[0x20];
1775 u8 ether_stats_fragments_high[0x20];
1777 u8 ether_stats_fragments_low[0x20];
1779 u8 ether_stats_jabbers_high[0x20];
1781 u8 ether_stats_jabbers_low[0x20];
1783 u8 ether_stats_collisions_high[0x20];
1785 u8 ether_stats_collisions_low[0x20];
1787 u8 ether_stats_pkts64octets_high[0x20];
1789 u8 ether_stats_pkts64octets_low[0x20];
1791 u8 ether_stats_pkts65to127octets_high[0x20];
1793 u8 ether_stats_pkts65to127octets_low[0x20];
1795 u8 ether_stats_pkts128to255octets_high[0x20];
1797 u8 ether_stats_pkts128to255octets_low[0x20];
1799 u8 ether_stats_pkts256to511octets_high[0x20];
1801 u8 ether_stats_pkts256to511octets_low[0x20];
1803 u8 ether_stats_pkts512to1023octets_high[0x20];
1805 u8 ether_stats_pkts512to1023octets_low[0x20];
1807 u8 ether_stats_pkts1024to1518octets_high[0x20];
1809 u8 ether_stats_pkts1024to1518octets_low[0x20];
1811 u8 ether_stats_pkts1519to2047octets_high[0x20];
1813 u8 ether_stats_pkts1519to2047octets_low[0x20];
1815 u8 ether_stats_pkts2048to4095octets_high[0x20];
1817 u8 ether_stats_pkts2048to4095octets_low[0x20];
1819 u8 ether_stats_pkts4096to8191octets_high[0x20];
1821 u8 ether_stats_pkts4096to8191octets_low[0x20];
1823 u8 ether_stats_pkts8192to10239octets_high[0x20];
1825 u8 ether_stats_pkts8192to10239octets_low[0x20];
1827 u8 reserved_at_540[0x280];
1830 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1831 u8 if_in_octets_high[0x20];
1833 u8 if_in_octets_low[0x20];
1835 u8 if_in_ucast_pkts_high[0x20];
1837 u8 if_in_ucast_pkts_low[0x20];
1839 u8 if_in_discards_high[0x20];
1841 u8 if_in_discards_low[0x20];
1843 u8 if_in_errors_high[0x20];
1845 u8 if_in_errors_low[0x20];
1847 u8 if_in_unknown_protos_high[0x20];
1849 u8 if_in_unknown_protos_low[0x20];
1851 u8 if_out_octets_high[0x20];
1853 u8 if_out_octets_low[0x20];
1855 u8 if_out_ucast_pkts_high[0x20];
1857 u8 if_out_ucast_pkts_low[0x20];
1859 u8 if_out_discards_high[0x20];
1861 u8 if_out_discards_low[0x20];
1863 u8 if_out_errors_high[0x20];
1865 u8 if_out_errors_low[0x20];
1867 u8 if_in_multicast_pkts_high[0x20];
1869 u8 if_in_multicast_pkts_low[0x20];
1871 u8 if_in_broadcast_pkts_high[0x20];
1873 u8 if_in_broadcast_pkts_low[0x20];
1875 u8 if_out_multicast_pkts_high[0x20];
1877 u8 if_out_multicast_pkts_low[0x20];
1879 u8 if_out_broadcast_pkts_high[0x20];
1881 u8 if_out_broadcast_pkts_low[0x20];
1883 u8 reserved_at_340[0x480];
1886 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1887 u8 a_frames_transmitted_ok_high[0x20];
1889 u8 a_frames_transmitted_ok_low[0x20];
1891 u8 a_frames_received_ok_high[0x20];
1893 u8 a_frames_received_ok_low[0x20];
1895 u8 a_frame_check_sequence_errors_high[0x20];
1897 u8 a_frame_check_sequence_errors_low[0x20];
1899 u8 a_alignment_errors_high[0x20];
1901 u8 a_alignment_errors_low[0x20];
1903 u8 a_octets_transmitted_ok_high[0x20];
1905 u8 a_octets_transmitted_ok_low[0x20];
1907 u8 a_octets_received_ok_high[0x20];
1909 u8 a_octets_received_ok_low[0x20];
1911 u8 a_multicast_frames_xmitted_ok_high[0x20];
1913 u8 a_multicast_frames_xmitted_ok_low[0x20];
1915 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1917 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1919 u8 a_multicast_frames_received_ok_high[0x20];
1921 u8 a_multicast_frames_received_ok_low[0x20];
1923 u8 a_broadcast_frames_received_ok_high[0x20];
1925 u8 a_broadcast_frames_received_ok_low[0x20];
1927 u8 a_in_range_length_errors_high[0x20];
1929 u8 a_in_range_length_errors_low[0x20];
1931 u8 a_out_of_range_length_field_high[0x20];
1933 u8 a_out_of_range_length_field_low[0x20];
1935 u8 a_frame_too_long_errors_high[0x20];
1937 u8 a_frame_too_long_errors_low[0x20];
1939 u8 a_symbol_error_during_carrier_high[0x20];
1941 u8 a_symbol_error_during_carrier_low[0x20];
1943 u8 a_mac_control_frames_transmitted_high[0x20];
1945 u8 a_mac_control_frames_transmitted_low[0x20];
1947 u8 a_mac_control_frames_received_high[0x20];
1949 u8 a_mac_control_frames_received_low[0x20];
1951 u8 a_unsupported_opcodes_received_high[0x20];
1953 u8 a_unsupported_opcodes_received_low[0x20];
1955 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1957 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1959 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1961 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1963 u8 reserved_at_4c0[0x300];
1966 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1967 u8 life_time_counter_high[0x20];
1969 u8 life_time_counter_low[0x20];
1975 u8 l0_to_recovery_eieos[0x20];
1977 u8 l0_to_recovery_ts[0x20];
1979 u8 l0_to_recovery_framing[0x20];
1981 u8 l0_to_recovery_retrain[0x20];
1983 u8 crc_error_dllp[0x20];
1985 u8 crc_error_tlp[0x20];
1987 u8 tx_overflow_buffer_pkt_high[0x20];
1989 u8 tx_overflow_buffer_pkt_low[0x20];
1991 u8 outbound_stalled_reads[0x20];
1993 u8 outbound_stalled_writes[0x20];
1995 u8 outbound_stalled_reads_events[0x20];
1997 u8 outbound_stalled_writes_events[0x20];
1999 u8 reserved_at_200[0x5c0];
2002 struct mlx5_ifc_cmd_inter_comp_event_bits {
2003 u8 command_completion_vector[0x20];
2005 u8 reserved_at_20[0xc0];
2008 struct mlx5_ifc_stall_vl_event_bits {
2009 u8 reserved_at_0[0x18];
2011 u8 reserved_at_19[0x3];
2014 u8 reserved_at_20[0xa0];
2017 struct mlx5_ifc_db_bf_congestion_event_bits {
2018 u8 event_subtype[0x8];
2019 u8 reserved_at_8[0x8];
2020 u8 congestion_level[0x8];
2021 u8 reserved_at_18[0x8];
2023 u8 reserved_at_20[0xa0];
2026 struct mlx5_ifc_gpio_event_bits {
2027 u8 reserved_at_0[0x60];
2029 u8 gpio_event_hi[0x20];
2031 u8 gpio_event_lo[0x20];
2033 u8 reserved_at_a0[0x40];
2036 struct mlx5_ifc_port_state_change_event_bits {
2037 u8 reserved_at_0[0x40];
2040 u8 reserved_at_44[0x1c];
2042 u8 reserved_at_60[0x80];
2045 struct mlx5_ifc_dropped_packet_logged_bits {
2046 u8 reserved_at_0[0xe0];
2050 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2051 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2054 struct mlx5_ifc_cq_error_bits {
2055 u8 reserved_at_0[0x8];
2058 u8 reserved_at_20[0x20];
2060 u8 reserved_at_40[0x18];
2063 u8 reserved_at_60[0x80];
2066 struct mlx5_ifc_rdma_page_fault_event_bits {
2067 u8 bytes_committed[0x20];
2071 u8 reserved_at_40[0x10];
2072 u8 packet_len[0x10];
2074 u8 rdma_op_len[0x20];
2078 u8 reserved_at_c0[0x5];
2085 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2086 u8 bytes_committed[0x20];
2088 u8 reserved_at_20[0x10];
2091 u8 reserved_at_40[0x10];
2094 u8 reserved_at_60[0x60];
2096 u8 reserved_at_c0[0x5];
2103 struct mlx5_ifc_qp_events_bits {
2104 u8 reserved_at_0[0xa0];
2107 u8 reserved_at_a8[0x18];
2109 u8 reserved_at_c0[0x8];
2110 u8 qpn_rqn_sqn[0x18];
2113 struct mlx5_ifc_dct_events_bits {
2114 u8 reserved_at_0[0xc0];
2116 u8 reserved_at_c0[0x8];
2117 u8 dct_number[0x18];
2120 struct mlx5_ifc_comp_event_bits {
2121 u8 reserved_at_0[0xc0];
2123 u8 reserved_at_c0[0x8];
2128 MLX5_QPC_STATE_RST = 0x0,
2129 MLX5_QPC_STATE_INIT = 0x1,
2130 MLX5_QPC_STATE_RTR = 0x2,
2131 MLX5_QPC_STATE_RTS = 0x3,
2132 MLX5_QPC_STATE_SQER = 0x4,
2133 MLX5_QPC_STATE_ERR = 0x6,
2134 MLX5_QPC_STATE_SQD = 0x7,
2135 MLX5_QPC_STATE_SUSPENDED = 0x9,
2139 MLX5_QPC_ST_RC = 0x0,
2140 MLX5_QPC_ST_UC = 0x1,
2141 MLX5_QPC_ST_UD = 0x2,
2142 MLX5_QPC_ST_XRC = 0x3,
2143 MLX5_QPC_ST_DCI = 0x5,
2144 MLX5_QPC_ST_QP0 = 0x7,
2145 MLX5_QPC_ST_QP1 = 0x8,
2146 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2147 MLX5_QPC_ST_REG_UMR = 0xc,
2151 MLX5_QPC_PM_STATE_ARMED = 0x0,
2152 MLX5_QPC_PM_STATE_REARM = 0x1,
2153 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2154 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2158 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2162 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2163 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2167 MLX5_QPC_MTU_256_BYTES = 0x1,
2168 MLX5_QPC_MTU_512_BYTES = 0x2,
2169 MLX5_QPC_MTU_1K_BYTES = 0x3,
2170 MLX5_QPC_MTU_2K_BYTES = 0x4,
2171 MLX5_QPC_MTU_4K_BYTES = 0x5,
2172 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2176 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2177 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2178 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2179 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2180 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2181 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2182 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2183 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2187 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2188 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2189 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2193 MLX5_QPC_CS_RES_DISABLE = 0x0,
2194 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2195 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2198 struct mlx5_ifc_qpc_bits {
2200 u8 lag_tx_port_affinity[0x4];
2202 u8 reserved_at_10[0x3];
2204 u8 reserved_at_15[0x3];
2205 u8 offload_type[0x4];
2206 u8 end_padding_mode[0x2];
2207 u8 reserved_at_1e[0x2];
2209 u8 wq_signature[0x1];
2210 u8 block_lb_mc[0x1];
2211 u8 atomic_like_write_en[0x1];
2212 u8 latency_sensitive[0x1];
2213 u8 reserved_at_24[0x1];
2214 u8 drain_sigerr[0x1];
2215 u8 reserved_at_26[0x2];
2219 u8 log_msg_max[0x5];
2220 u8 reserved_at_48[0x1];
2221 u8 log_rq_size[0x4];
2222 u8 log_rq_stride[0x3];
2224 u8 log_sq_size[0x4];
2225 u8 reserved_at_55[0x6];
2227 u8 ulp_stateless_offload_mode[0x4];
2229 u8 counter_set_id[0x8];
2232 u8 reserved_at_80[0x8];
2233 u8 user_index[0x18];
2235 u8 reserved_at_a0[0x3];
2236 u8 log_page_size[0x5];
2237 u8 remote_qpn[0x18];
2239 struct mlx5_ifc_ads_bits primary_address_path;
2241 struct mlx5_ifc_ads_bits secondary_address_path;
2243 u8 log_ack_req_freq[0x4];
2244 u8 reserved_at_384[0x4];
2245 u8 log_sra_max[0x3];
2246 u8 reserved_at_38b[0x2];
2247 u8 retry_count[0x3];
2249 u8 reserved_at_393[0x1];
2251 u8 cur_rnr_retry[0x3];
2252 u8 cur_retry_count[0x3];
2253 u8 reserved_at_39b[0x5];
2255 u8 reserved_at_3a0[0x20];
2257 u8 reserved_at_3c0[0x8];
2258 u8 next_send_psn[0x18];
2260 u8 reserved_at_3e0[0x8];
2263 u8 reserved_at_400[0x8];
2266 u8 reserved_at_420[0x20];
2268 u8 reserved_at_440[0x8];
2269 u8 last_acked_psn[0x18];
2271 u8 reserved_at_460[0x8];
2274 u8 reserved_at_480[0x8];
2275 u8 log_rra_max[0x3];
2276 u8 reserved_at_48b[0x1];
2277 u8 atomic_mode[0x4];
2281 u8 reserved_at_493[0x1];
2282 u8 page_offset[0x6];
2283 u8 reserved_at_49a[0x3];
2284 u8 cd_slave_receive[0x1];
2285 u8 cd_slave_send[0x1];
2288 u8 reserved_at_4a0[0x3];
2289 u8 min_rnr_nak[0x5];
2290 u8 next_rcv_psn[0x18];
2292 u8 reserved_at_4c0[0x8];
2295 u8 reserved_at_4e0[0x8];
2302 u8 reserved_at_560[0x5];
2304 u8 srqn_rmpn_xrqn[0x18];
2306 u8 reserved_at_580[0x8];
2309 u8 hw_sq_wqebb_counter[0x10];
2310 u8 sw_sq_wqebb_counter[0x10];
2312 u8 hw_rq_counter[0x20];
2314 u8 sw_rq_counter[0x20];
2316 u8 reserved_at_600[0x20];
2318 u8 reserved_at_620[0xf];
2323 u8 dc_access_key[0x40];
2325 u8 reserved_at_680[0xc0];
2328 struct mlx5_ifc_roce_addr_layout_bits {
2329 u8 source_l3_address[16][0x8];
2331 u8 reserved_at_80[0x3];
2334 u8 source_mac_47_32[0x10];
2336 u8 source_mac_31_0[0x20];
2338 u8 reserved_at_c0[0x14];
2339 u8 roce_l3_type[0x4];
2340 u8 roce_version[0x8];
2342 u8 reserved_at_e0[0x20];
2345 union mlx5_ifc_hca_cap_union_bits {
2346 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2347 struct mlx5_ifc_odp_cap_bits odp_cap;
2348 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2349 struct mlx5_ifc_roce_cap_bits roce_cap;
2350 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2351 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2352 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2353 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2354 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2355 struct mlx5_ifc_qos_cap_bits qos_cap;
2356 struct mlx5_ifc_fpga_cap_bits fpga_cap;
2357 u8 reserved_at_0[0x8000];
2361 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2362 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2363 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2364 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2365 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2366 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2367 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
2368 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
2369 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2372 struct mlx5_ifc_vlan_bits {
2379 struct mlx5_ifc_flow_context_bits {
2380 struct mlx5_ifc_vlan_bits push_vlan;
2384 u8 reserved_at_40[0x8];
2387 u8 reserved_at_60[0x10];
2390 u8 reserved_at_80[0x8];
2391 u8 destination_list_size[0x18];
2393 u8 reserved_at_a0[0x8];
2394 u8 flow_counter_list_size[0x18];
2398 u8 modify_header_id[0x20];
2400 u8 reserved_at_100[0x100];
2402 struct mlx5_ifc_fte_match_param_bits match_value;
2404 u8 reserved_at_1200[0x600];
2406 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2410 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2411 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2414 struct mlx5_ifc_xrc_srqc_bits {
2416 u8 log_xrc_srq_size[0x4];
2417 u8 reserved_at_8[0x18];
2419 u8 wq_signature[0x1];
2421 u8 reserved_at_22[0x1];
2423 u8 basic_cyclic_rcv_wqe[0x1];
2424 u8 log_rq_stride[0x3];
2427 u8 page_offset[0x6];
2428 u8 reserved_at_46[0x2];
2431 u8 reserved_at_60[0x20];
2433 u8 user_index_equal_xrc_srqn[0x1];
2434 u8 reserved_at_81[0x1];
2435 u8 log_page_size[0x6];
2436 u8 user_index[0x18];
2438 u8 reserved_at_a0[0x20];
2440 u8 reserved_at_c0[0x8];
2446 u8 reserved_at_100[0x40];
2448 u8 db_record_addr_h[0x20];
2450 u8 db_record_addr_l[0x1e];
2451 u8 reserved_at_17e[0x2];
2453 u8 reserved_at_180[0x80];
2456 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2457 u8 counter_error_queues[0x20];
2459 u8 total_error_queues[0x20];
2461 u8 send_queue_priority_update_flow[0x20];
2463 u8 reserved_at_60[0x20];
2465 u8 nic_receive_steering_discard[0x40];
2467 u8 receive_discard_vport_down[0x40];
2469 u8 transmit_discard_vport_down[0x40];
2471 u8 reserved_at_140[0xec0];
2474 struct mlx5_ifc_traffic_counter_bits {
2480 struct mlx5_ifc_tisc_bits {
2481 u8 strict_lag_tx_port_affinity[0x1];
2482 u8 reserved_at_1[0x3];
2483 u8 lag_tx_port_affinity[0x04];
2485 u8 reserved_at_8[0x4];
2487 u8 reserved_at_10[0x10];
2489 u8 reserved_at_20[0x100];
2491 u8 reserved_at_120[0x8];
2492 u8 transport_domain[0x18];
2494 u8 reserved_at_140[0x8];
2495 u8 underlay_qpn[0x18];
2496 u8 reserved_at_160[0x3a0];
2500 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2501 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2505 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2506 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2510 MLX5_RX_HASH_FN_NONE = 0x0,
2511 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2512 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2516 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2517 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2520 struct mlx5_ifc_tirc_bits {
2521 u8 reserved_at_0[0x20];
2524 u8 reserved_at_24[0x1c];
2526 u8 reserved_at_40[0x40];
2528 u8 reserved_at_80[0x4];
2529 u8 lro_timeout_period_usecs[0x10];
2530 u8 lro_enable_mask[0x4];
2531 u8 lro_max_ip_payload_size[0x8];
2533 u8 reserved_at_a0[0x40];
2535 u8 reserved_at_e0[0x8];
2536 u8 inline_rqn[0x18];
2538 u8 rx_hash_symmetric[0x1];
2539 u8 reserved_at_101[0x1];
2540 u8 tunneled_offload_en[0x1];
2541 u8 reserved_at_103[0x5];
2542 u8 indirect_table[0x18];
2545 u8 reserved_at_124[0x2];
2546 u8 self_lb_block[0x2];
2547 u8 transport_domain[0x18];
2549 u8 rx_hash_toeplitz_key[10][0x20];
2551 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2553 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2555 u8 reserved_at_2c0[0x4c0];
2559 MLX5_SRQC_STATE_GOOD = 0x0,
2560 MLX5_SRQC_STATE_ERROR = 0x1,
2563 struct mlx5_ifc_srqc_bits {
2565 u8 log_srq_size[0x4];
2566 u8 reserved_at_8[0x18];
2568 u8 wq_signature[0x1];
2570 u8 reserved_at_22[0x1];
2572 u8 reserved_at_24[0x1];
2573 u8 log_rq_stride[0x3];
2576 u8 page_offset[0x6];
2577 u8 reserved_at_46[0x2];
2580 u8 reserved_at_60[0x20];
2582 u8 reserved_at_80[0x2];
2583 u8 log_page_size[0x6];
2584 u8 reserved_at_88[0x18];
2586 u8 reserved_at_a0[0x20];
2588 u8 reserved_at_c0[0x8];
2594 u8 reserved_at_100[0x40];
2598 u8 reserved_at_180[0x80];
2602 MLX5_SQC_STATE_RST = 0x0,
2603 MLX5_SQC_STATE_RDY = 0x1,
2604 MLX5_SQC_STATE_ERR = 0x3,
2607 struct mlx5_ifc_sqc_bits {
2611 u8 flush_in_error_en[0x1];
2612 u8 allow_multi_pkt_send_wqe[0x1];
2613 u8 min_wqe_inline_mode[0x3];
2618 u8 reserved_at_f[0x11];
2620 u8 reserved_at_20[0x8];
2621 u8 user_index[0x18];
2623 u8 reserved_at_40[0x8];
2626 u8 reserved_at_60[0x8];
2627 u8 hairpin_peer_rq[0x18];
2629 u8 reserved_at_80[0x10];
2630 u8 hairpin_peer_vhca[0x10];
2632 u8 reserved_at_a0[0x50];
2634 u8 packet_pacing_rate_limit_index[0x10];
2635 u8 tis_lst_sz[0x10];
2636 u8 reserved_at_110[0x10];
2638 u8 reserved_at_120[0x40];
2640 u8 reserved_at_160[0x8];
2643 struct mlx5_ifc_wq_bits wq;
2647 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2648 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2649 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2650 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2653 struct mlx5_ifc_scheduling_context_bits {
2654 u8 element_type[0x8];
2655 u8 reserved_at_8[0x18];
2657 u8 element_attributes[0x20];
2659 u8 parent_element_id[0x20];
2661 u8 reserved_at_60[0x40];
2665 u8 max_average_bw[0x20];
2667 u8 reserved_at_e0[0x120];
2670 struct mlx5_ifc_rqtc_bits {
2671 u8 reserved_at_0[0xa0];
2673 u8 reserved_at_a0[0x10];
2674 u8 rqt_max_size[0x10];
2676 u8 reserved_at_c0[0x10];
2677 u8 rqt_actual_size[0x10];
2679 u8 reserved_at_e0[0x6a0];
2681 struct mlx5_ifc_rq_num_bits rq_num[0];
2685 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2686 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2690 MLX5_RQC_STATE_RST = 0x0,
2691 MLX5_RQC_STATE_RDY = 0x1,
2692 MLX5_RQC_STATE_ERR = 0x3,
2695 struct mlx5_ifc_rqc_bits {
2697 u8 delay_drop_en[0x1];
2698 u8 scatter_fcs[0x1];
2700 u8 mem_rq_type[0x4];
2702 u8 reserved_at_c[0x1];
2703 u8 flush_in_error_en[0x1];
2705 u8 reserved_at_f[0x11];
2707 u8 reserved_at_20[0x8];
2708 u8 user_index[0x18];
2710 u8 reserved_at_40[0x8];
2713 u8 counter_set_id[0x8];
2714 u8 reserved_at_68[0x18];
2716 u8 reserved_at_80[0x8];
2719 u8 reserved_at_a0[0x8];
2720 u8 hairpin_peer_sq[0x18];
2722 u8 reserved_at_c0[0x10];
2723 u8 hairpin_peer_vhca[0x10];
2725 u8 reserved_at_e0[0xa0];
2727 struct mlx5_ifc_wq_bits wq;
2731 MLX5_RMPC_STATE_RDY = 0x1,
2732 MLX5_RMPC_STATE_ERR = 0x3,
2735 struct mlx5_ifc_rmpc_bits {
2736 u8 reserved_at_0[0x8];
2738 u8 reserved_at_c[0x14];
2740 u8 basic_cyclic_rcv_wqe[0x1];
2741 u8 reserved_at_21[0x1f];
2743 u8 reserved_at_40[0x140];
2745 struct mlx5_ifc_wq_bits wq;
2748 struct mlx5_ifc_nic_vport_context_bits {
2749 u8 reserved_at_0[0x5];
2750 u8 min_wqe_inline_mode[0x3];
2751 u8 reserved_at_8[0x15];
2752 u8 disable_mc_local_lb[0x1];
2753 u8 disable_uc_local_lb[0x1];
2756 u8 arm_change_event[0x1];
2757 u8 reserved_at_21[0x1a];
2758 u8 event_on_mtu[0x1];
2759 u8 event_on_promisc_change[0x1];
2760 u8 event_on_vlan_change[0x1];
2761 u8 event_on_mc_address_change[0x1];
2762 u8 event_on_uc_address_change[0x1];
2764 u8 reserved_at_40[0xc];
2766 u8 affiliation_criteria[0x4];
2767 u8 affiliated_vhca_id[0x10];
2769 u8 reserved_at_60[0xd0];
2773 u8 system_image_guid[0x40];
2777 u8 reserved_at_200[0x140];
2778 u8 qkey_violation_counter[0x10];
2779 u8 reserved_at_350[0x430];
2783 u8 promisc_all[0x1];
2784 u8 reserved_at_783[0x2];
2785 u8 allowed_list_type[0x3];
2786 u8 reserved_at_788[0xc];
2787 u8 allowed_list_size[0xc];
2789 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2791 u8 reserved_at_7e0[0x20];
2793 u8 current_uc_mac_address[0][0x40];
2797 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2798 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2799 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2800 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
2801 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
2804 struct mlx5_ifc_mkc_bits {
2805 u8 reserved_at_0[0x1];
2807 u8 reserved_at_2[0x1];
2808 u8 access_mode_4_2[0x3];
2809 u8 reserved_at_6[0x7];
2810 u8 relaxed_ordering_write[0x1];
2811 u8 reserved_at_e[0x1];
2812 u8 small_fence_on_rdma_read_response[0x1];
2819 u8 access_mode_1_0[0x2];
2820 u8 reserved_at_18[0x8];
2825 u8 reserved_at_40[0x20];
2830 u8 reserved_at_63[0x2];
2831 u8 expected_sigerr_count[0x1];
2832 u8 reserved_at_66[0x1];
2836 u8 start_addr[0x40];
2840 u8 bsf_octword_size[0x20];
2842 u8 reserved_at_120[0x80];
2844 u8 translations_octword_size[0x20];
2846 u8 reserved_at_1c0[0x1b];
2847 u8 log_page_size[0x5];
2849 u8 reserved_at_1e0[0x20];
2852 struct mlx5_ifc_pkey_bits {
2853 u8 reserved_at_0[0x10];
2857 struct mlx5_ifc_array128_auto_bits {
2858 u8 array128_auto[16][0x8];
2861 struct mlx5_ifc_hca_vport_context_bits {
2862 u8 field_select[0x20];
2864 u8 reserved_at_20[0xe0];
2866 u8 sm_virt_aware[0x1];
2869 u8 grh_required[0x1];
2870 u8 reserved_at_104[0xc];
2871 u8 port_physical_state[0x4];
2872 u8 vport_state_policy[0x4];
2874 u8 vport_state[0x4];
2876 u8 reserved_at_120[0x20];
2878 u8 system_image_guid[0x40];
2886 u8 cap_mask1_field_select[0x20];
2890 u8 cap_mask2_field_select[0x20];
2892 u8 reserved_at_280[0x80];
2895 u8 reserved_at_310[0x4];
2896 u8 init_type_reply[0x4];
2898 u8 subnet_timeout[0x5];
2902 u8 reserved_at_334[0xc];
2904 u8 qkey_violation_counter[0x10];
2905 u8 pkey_violation_counter[0x10];
2907 u8 reserved_at_360[0xca0];
2910 struct mlx5_ifc_esw_vport_context_bits {
2911 u8 reserved_at_0[0x3];
2912 u8 vport_svlan_strip[0x1];
2913 u8 vport_cvlan_strip[0x1];
2914 u8 vport_svlan_insert[0x1];
2915 u8 vport_cvlan_insert[0x2];
2916 u8 reserved_at_8[0x18];
2918 u8 reserved_at_20[0x20];
2927 u8 reserved_at_60[0x7a0];
2931 MLX5_EQC_STATUS_OK = 0x0,
2932 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2936 MLX5_EQC_ST_ARMED = 0x9,
2937 MLX5_EQC_ST_FIRED = 0xa,
2940 struct mlx5_ifc_eqc_bits {
2942 u8 reserved_at_4[0x9];
2945 u8 reserved_at_f[0x5];
2947 u8 reserved_at_18[0x8];
2949 u8 reserved_at_20[0x20];
2951 u8 reserved_at_40[0x14];
2952 u8 page_offset[0x6];
2953 u8 reserved_at_5a[0x6];
2955 u8 reserved_at_60[0x3];
2956 u8 log_eq_size[0x5];
2959 u8 reserved_at_80[0x20];
2961 u8 reserved_at_a0[0x18];
2964 u8 reserved_at_c0[0x3];
2965 u8 log_page_size[0x5];
2966 u8 reserved_at_c8[0x18];
2968 u8 reserved_at_e0[0x60];
2970 u8 reserved_at_140[0x8];
2971 u8 consumer_counter[0x18];
2973 u8 reserved_at_160[0x8];
2974 u8 producer_counter[0x18];
2976 u8 reserved_at_180[0x80];
2980 MLX5_DCTC_STATE_ACTIVE = 0x0,
2981 MLX5_DCTC_STATE_DRAINING = 0x1,
2982 MLX5_DCTC_STATE_DRAINED = 0x2,
2986 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2987 MLX5_DCTC_CS_RES_NA = 0x1,
2988 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2992 MLX5_DCTC_MTU_256_BYTES = 0x1,
2993 MLX5_DCTC_MTU_512_BYTES = 0x2,
2994 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2995 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2996 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2999 struct mlx5_ifc_dctc_bits {
3000 u8 reserved_at_0[0x4];
3002 u8 reserved_at_8[0x18];
3004 u8 reserved_at_20[0x8];
3005 u8 user_index[0x18];
3007 u8 reserved_at_40[0x8];
3010 u8 counter_set_id[0x8];
3011 u8 atomic_mode[0x4];
3015 u8 atomic_like_write_en[0x1];
3016 u8 latency_sensitive[0x1];
3019 u8 reserved_at_73[0xd];
3021 u8 reserved_at_80[0x8];
3023 u8 reserved_at_90[0x3];
3024 u8 min_rnr_nak[0x5];
3025 u8 reserved_at_98[0x8];
3027 u8 reserved_at_a0[0x8];
3030 u8 reserved_at_c0[0x8];
3034 u8 reserved_at_e8[0x4];
3035 u8 flow_label[0x14];
3037 u8 dc_access_key[0x40];
3039 u8 reserved_at_140[0x5];
3042 u8 pkey_index[0x10];
3044 u8 reserved_at_160[0x8];
3045 u8 my_addr_index[0x8];
3046 u8 reserved_at_170[0x8];
3049 u8 dc_access_key_violation_count[0x20];
3051 u8 reserved_at_1a0[0x14];
3057 u8 reserved_at_1c0[0x40];
3061 MLX5_CQC_STATUS_OK = 0x0,
3062 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3063 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3067 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3068 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3072 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3073 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3074 MLX5_CQC_ST_FIRED = 0xa,
3078 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3079 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3080 MLX5_CQ_PERIOD_NUM_MODES
3083 struct mlx5_ifc_cqc_bits {
3085 u8 reserved_at_4[0x4];
3088 u8 reserved_at_c[0x1];
3089 u8 scqe_break_moderation_en[0x1];
3091 u8 cq_period_mode[0x2];
3092 u8 cqe_comp_en[0x1];
3093 u8 mini_cqe_res_format[0x2];
3095 u8 reserved_at_18[0x8];
3097 u8 reserved_at_20[0x20];
3099 u8 reserved_at_40[0x14];
3100 u8 page_offset[0x6];
3101 u8 reserved_at_5a[0x6];
3103 u8 reserved_at_60[0x3];
3104 u8 log_cq_size[0x5];
3107 u8 reserved_at_80[0x4];
3109 u8 cq_max_count[0x10];
3111 u8 reserved_at_a0[0x18];
3114 u8 reserved_at_c0[0x3];
3115 u8 log_page_size[0x5];
3116 u8 reserved_at_c8[0x18];
3118 u8 reserved_at_e0[0x20];
3120 u8 reserved_at_100[0x8];
3121 u8 last_notified_index[0x18];
3123 u8 reserved_at_120[0x8];
3124 u8 last_solicit_index[0x18];
3126 u8 reserved_at_140[0x8];
3127 u8 consumer_counter[0x18];
3129 u8 reserved_at_160[0x8];
3130 u8 producer_counter[0x18];
3132 u8 reserved_at_180[0x40];
3137 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3138 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3139 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3140 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3141 u8 reserved_at_0[0x800];
3144 struct mlx5_ifc_query_adapter_param_block_bits {
3145 u8 reserved_at_0[0xc0];
3147 u8 reserved_at_c0[0x8];
3148 u8 ieee_vendor_id[0x18];
3150 u8 reserved_at_e0[0x10];
3151 u8 vsd_vendor_id[0x10];
3155 u8 vsd_contd_psid[16][0x8];
3159 MLX5_XRQC_STATE_GOOD = 0x0,
3160 MLX5_XRQC_STATE_ERROR = 0x1,
3164 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3165 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3169 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3172 struct mlx5_ifc_tag_matching_topology_context_bits {
3173 u8 log_matching_list_sz[0x4];
3174 u8 reserved_at_4[0xc];
3175 u8 append_next_index[0x10];
3177 u8 sw_phase_cnt[0x10];
3178 u8 hw_phase_cnt[0x10];
3180 u8 reserved_at_40[0x40];
3183 struct mlx5_ifc_xrqc_bits {
3186 u8 reserved_at_5[0xf];
3188 u8 reserved_at_18[0x4];
3191 u8 reserved_at_20[0x8];
3192 u8 user_index[0x18];
3194 u8 reserved_at_40[0x8];
3197 u8 reserved_at_60[0xa0];
3199 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3201 u8 reserved_at_180[0x280];
3203 struct mlx5_ifc_wq_bits wq;
3206 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3207 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3208 struct mlx5_ifc_resize_field_select_bits resize_field_select;
3209 u8 reserved_at_0[0x20];
3212 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3213 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3214 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3215 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3216 u8 reserved_at_0[0x20];
3219 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3220 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3221 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3222 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3223 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3224 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3225 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3226 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3227 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3228 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3229 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3230 u8 reserved_at_0[0x7c0];
3233 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3234 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3235 u8 reserved_at_0[0x7c0];
3238 union mlx5_ifc_event_auto_bits {
3239 struct mlx5_ifc_comp_event_bits comp_event;
3240 struct mlx5_ifc_dct_events_bits dct_events;
3241 struct mlx5_ifc_qp_events_bits qp_events;
3242 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3243 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3244 struct mlx5_ifc_cq_error_bits cq_error;
3245 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3246 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3247 struct mlx5_ifc_gpio_event_bits gpio_event;
3248 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3249 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3250 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3251 u8 reserved_at_0[0xe0];
3254 struct mlx5_ifc_health_buffer_bits {
3255 u8 reserved_at_0[0x100];
3257 u8 assert_existptr[0x20];
3259 u8 assert_callra[0x20];
3261 u8 reserved_at_140[0x40];
3263 u8 fw_version[0x20];
3267 u8 reserved_at_1c0[0x20];
3269 u8 irisc_index[0x8];
3274 struct mlx5_ifc_register_loopback_control_bits {
3276 u8 reserved_at_1[0x7];
3278 u8 reserved_at_10[0x10];
3280 u8 reserved_at_20[0x60];
3283 struct mlx5_ifc_vport_tc_element_bits {
3284 u8 traffic_class[0x4];
3285 u8 reserved_at_4[0xc];
3286 u8 vport_number[0x10];
3289 struct mlx5_ifc_vport_element_bits {
3290 u8 reserved_at_0[0x10];
3291 u8 vport_number[0x10];
3295 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3296 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3297 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3300 struct mlx5_ifc_tsar_element_bits {
3301 u8 reserved_at_0[0x8];
3303 u8 reserved_at_10[0x10];
3307 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3308 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3311 struct mlx5_ifc_teardown_hca_out_bits {
3313 u8 reserved_at_8[0x18];
3317 u8 reserved_at_40[0x3f];
3319 u8 force_state[0x1];
3323 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3324 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
3327 struct mlx5_ifc_teardown_hca_in_bits {
3329 u8 reserved_at_10[0x10];
3331 u8 reserved_at_20[0x10];
3334 u8 reserved_at_40[0x10];
3337 u8 reserved_at_60[0x20];
3340 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3342 u8 reserved_at_8[0x18];
3346 u8 reserved_at_40[0x40];
3349 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3351 u8 reserved_at_10[0x10];
3353 u8 reserved_at_20[0x10];
3356 u8 reserved_at_40[0x8];
3359 u8 reserved_at_60[0x20];
3361 u8 opt_param_mask[0x20];
3363 u8 reserved_at_a0[0x20];
3365 struct mlx5_ifc_qpc_bits qpc;
3367 u8 reserved_at_800[0x80];
3370 struct mlx5_ifc_sqd2rts_qp_out_bits {
3372 u8 reserved_at_8[0x18];
3376 u8 reserved_at_40[0x40];
3379 struct mlx5_ifc_sqd2rts_qp_in_bits {
3381 u8 reserved_at_10[0x10];
3383 u8 reserved_at_20[0x10];
3386 u8 reserved_at_40[0x8];
3389 u8 reserved_at_60[0x20];
3391 u8 opt_param_mask[0x20];
3393 u8 reserved_at_a0[0x20];
3395 struct mlx5_ifc_qpc_bits qpc;
3397 u8 reserved_at_800[0x80];
3400 struct mlx5_ifc_set_roce_address_out_bits {
3402 u8 reserved_at_8[0x18];
3406 u8 reserved_at_40[0x40];
3409 struct mlx5_ifc_set_roce_address_in_bits {
3411 u8 reserved_at_10[0x10];
3413 u8 reserved_at_20[0x10];
3416 u8 roce_address_index[0x10];
3417 u8 reserved_at_50[0xc];
3418 u8 vhca_port_num[0x4];
3420 u8 reserved_at_60[0x20];
3422 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3425 struct mlx5_ifc_set_mad_demux_out_bits {
3427 u8 reserved_at_8[0x18];
3431 u8 reserved_at_40[0x40];
3435 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3436 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3439 struct mlx5_ifc_set_mad_demux_in_bits {
3441 u8 reserved_at_10[0x10];
3443 u8 reserved_at_20[0x10];
3446 u8 reserved_at_40[0x20];
3448 u8 reserved_at_60[0x6];
3450 u8 reserved_at_68[0x18];
3453 struct mlx5_ifc_set_l2_table_entry_out_bits {
3455 u8 reserved_at_8[0x18];
3459 u8 reserved_at_40[0x40];
3462 struct mlx5_ifc_set_l2_table_entry_in_bits {
3464 u8 reserved_at_10[0x10];
3466 u8 reserved_at_20[0x10];
3469 u8 reserved_at_40[0x60];
3471 u8 reserved_at_a0[0x8];
3472 u8 table_index[0x18];
3474 u8 reserved_at_c0[0x20];
3476 u8 reserved_at_e0[0x13];
3480 struct mlx5_ifc_mac_address_layout_bits mac_address;
3482 u8 reserved_at_140[0xc0];
3485 struct mlx5_ifc_set_issi_out_bits {
3487 u8 reserved_at_8[0x18];
3491 u8 reserved_at_40[0x40];
3494 struct mlx5_ifc_set_issi_in_bits {
3496 u8 reserved_at_10[0x10];
3498 u8 reserved_at_20[0x10];
3501 u8 reserved_at_40[0x10];
3502 u8 current_issi[0x10];
3504 u8 reserved_at_60[0x20];
3507 struct mlx5_ifc_set_hca_cap_out_bits {
3509 u8 reserved_at_8[0x18];
3513 u8 reserved_at_40[0x40];
3516 struct mlx5_ifc_set_hca_cap_in_bits {
3518 u8 reserved_at_10[0x10];
3520 u8 reserved_at_20[0x10];
3523 u8 reserved_at_40[0x40];
3525 union mlx5_ifc_hca_cap_union_bits capability;
3529 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3530 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3531 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3532 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3535 struct mlx5_ifc_set_fte_out_bits {
3537 u8 reserved_at_8[0x18];
3541 u8 reserved_at_40[0x40];
3544 struct mlx5_ifc_set_fte_in_bits {
3546 u8 reserved_at_10[0x10];
3548 u8 reserved_at_20[0x10];
3551 u8 other_vport[0x1];
3552 u8 reserved_at_41[0xf];
3553 u8 vport_number[0x10];
3555 u8 reserved_at_60[0x20];
3558 u8 reserved_at_88[0x18];
3560 u8 reserved_at_a0[0x8];
3563 u8 reserved_at_c0[0x18];
3564 u8 modify_enable_mask[0x8];
3566 u8 reserved_at_e0[0x20];
3568 u8 flow_index[0x20];
3570 u8 reserved_at_120[0xe0];
3572 struct mlx5_ifc_flow_context_bits flow_context;
3575 struct mlx5_ifc_rts2rts_qp_out_bits {
3577 u8 reserved_at_8[0x18];
3581 u8 reserved_at_40[0x40];
3584 struct mlx5_ifc_rts2rts_qp_in_bits {
3586 u8 reserved_at_10[0x10];
3588 u8 reserved_at_20[0x10];
3591 u8 reserved_at_40[0x8];
3594 u8 reserved_at_60[0x20];
3596 u8 opt_param_mask[0x20];
3598 u8 reserved_at_a0[0x20];
3600 struct mlx5_ifc_qpc_bits qpc;
3602 u8 reserved_at_800[0x80];
3605 struct mlx5_ifc_rtr2rts_qp_out_bits {
3607 u8 reserved_at_8[0x18];
3611 u8 reserved_at_40[0x40];
3614 struct mlx5_ifc_rtr2rts_qp_in_bits {
3616 u8 reserved_at_10[0x10];
3618 u8 reserved_at_20[0x10];
3621 u8 reserved_at_40[0x8];
3624 u8 reserved_at_60[0x20];
3626 u8 opt_param_mask[0x20];
3628 u8 reserved_at_a0[0x20];
3630 struct mlx5_ifc_qpc_bits qpc;
3632 u8 reserved_at_800[0x80];
3635 struct mlx5_ifc_rst2init_qp_out_bits {
3637 u8 reserved_at_8[0x18];
3641 u8 reserved_at_40[0x40];
3644 struct mlx5_ifc_rst2init_qp_in_bits {
3646 u8 reserved_at_10[0x10];
3648 u8 reserved_at_20[0x10];
3651 u8 reserved_at_40[0x8];
3654 u8 reserved_at_60[0x20];
3656 u8 opt_param_mask[0x20];
3658 u8 reserved_at_a0[0x20];
3660 struct mlx5_ifc_qpc_bits qpc;
3662 u8 reserved_at_800[0x80];
3665 struct mlx5_ifc_query_xrq_out_bits {
3667 u8 reserved_at_8[0x18];
3671 u8 reserved_at_40[0x40];
3673 struct mlx5_ifc_xrqc_bits xrq_context;
3676 struct mlx5_ifc_query_xrq_in_bits {
3678 u8 reserved_at_10[0x10];
3680 u8 reserved_at_20[0x10];
3683 u8 reserved_at_40[0x8];
3686 u8 reserved_at_60[0x20];
3689 struct mlx5_ifc_query_xrc_srq_out_bits {
3691 u8 reserved_at_8[0x18];
3695 u8 reserved_at_40[0x40];
3697 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3699 u8 reserved_at_280[0x600];
3704 struct mlx5_ifc_query_xrc_srq_in_bits {
3706 u8 reserved_at_10[0x10];
3708 u8 reserved_at_20[0x10];
3711 u8 reserved_at_40[0x8];
3714 u8 reserved_at_60[0x20];
3718 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3719 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3722 struct mlx5_ifc_query_vport_state_out_bits {
3724 u8 reserved_at_8[0x18];
3728 u8 reserved_at_40[0x20];
3730 u8 reserved_at_60[0x18];
3731 u8 admin_state[0x4];
3736 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
3737 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
3740 struct mlx5_ifc_query_vport_state_in_bits {
3742 u8 reserved_at_10[0x10];
3744 u8 reserved_at_20[0x10];
3747 u8 other_vport[0x1];
3748 u8 reserved_at_41[0xf];
3749 u8 vport_number[0x10];
3751 u8 reserved_at_60[0x20];
3754 struct mlx5_ifc_query_vnic_env_out_bits {
3756 u8 reserved_at_8[0x18];
3760 u8 reserved_at_40[0x40];
3762 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
3766 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
3769 struct mlx5_ifc_query_vnic_env_in_bits {
3771 u8 reserved_at_10[0x10];
3773 u8 reserved_at_20[0x10];
3776 u8 other_vport[0x1];
3777 u8 reserved_at_41[0xf];
3778 u8 vport_number[0x10];
3780 u8 reserved_at_60[0x20];
3783 struct mlx5_ifc_query_vport_counter_out_bits {
3785 u8 reserved_at_8[0x18];
3789 u8 reserved_at_40[0x40];
3791 struct mlx5_ifc_traffic_counter_bits received_errors;
3793 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3795 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3797 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3799 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3801 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3803 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3805 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3807 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3809 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3811 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3813 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3815 u8 reserved_at_680[0xa00];
3819 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3822 struct mlx5_ifc_query_vport_counter_in_bits {
3824 u8 reserved_at_10[0x10];
3826 u8 reserved_at_20[0x10];
3829 u8 other_vport[0x1];
3830 u8 reserved_at_41[0xb];
3832 u8 vport_number[0x10];
3834 u8 reserved_at_60[0x60];
3837 u8 reserved_at_c1[0x1f];
3839 u8 reserved_at_e0[0x20];
3842 struct mlx5_ifc_query_tis_out_bits {
3844 u8 reserved_at_8[0x18];
3848 u8 reserved_at_40[0x40];
3850 struct mlx5_ifc_tisc_bits tis_context;
3853 struct mlx5_ifc_query_tis_in_bits {
3855 u8 reserved_at_10[0x10];
3857 u8 reserved_at_20[0x10];
3860 u8 reserved_at_40[0x8];
3863 u8 reserved_at_60[0x20];
3866 struct mlx5_ifc_query_tir_out_bits {
3868 u8 reserved_at_8[0x18];
3872 u8 reserved_at_40[0xc0];
3874 struct mlx5_ifc_tirc_bits tir_context;
3877 struct mlx5_ifc_query_tir_in_bits {
3879 u8 reserved_at_10[0x10];
3881 u8 reserved_at_20[0x10];
3884 u8 reserved_at_40[0x8];
3887 u8 reserved_at_60[0x20];
3890 struct mlx5_ifc_query_srq_out_bits {
3892 u8 reserved_at_8[0x18];
3896 u8 reserved_at_40[0x40];
3898 struct mlx5_ifc_srqc_bits srq_context_entry;
3900 u8 reserved_at_280[0x600];
3905 struct mlx5_ifc_query_srq_in_bits {
3907 u8 reserved_at_10[0x10];
3909 u8 reserved_at_20[0x10];
3912 u8 reserved_at_40[0x8];
3915 u8 reserved_at_60[0x20];
3918 struct mlx5_ifc_query_sq_out_bits {
3920 u8 reserved_at_8[0x18];
3924 u8 reserved_at_40[0xc0];
3926 struct mlx5_ifc_sqc_bits sq_context;
3929 struct mlx5_ifc_query_sq_in_bits {
3931 u8 reserved_at_10[0x10];
3933 u8 reserved_at_20[0x10];
3936 u8 reserved_at_40[0x8];
3939 u8 reserved_at_60[0x20];
3942 struct mlx5_ifc_query_special_contexts_out_bits {
3944 u8 reserved_at_8[0x18];
3948 u8 dump_fill_mkey[0x20];
3954 u8 reserved_at_a0[0x60];
3957 struct mlx5_ifc_query_special_contexts_in_bits {
3959 u8 reserved_at_10[0x10];
3961 u8 reserved_at_20[0x10];
3964 u8 reserved_at_40[0x40];
3967 struct mlx5_ifc_query_scheduling_element_out_bits {
3969 u8 reserved_at_10[0x10];
3971 u8 reserved_at_20[0x10];
3974 u8 reserved_at_40[0xc0];
3976 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3978 u8 reserved_at_300[0x100];
3982 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3985 struct mlx5_ifc_query_scheduling_element_in_bits {
3987 u8 reserved_at_10[0x10];
3989 u8 reserved_at_20[0x10];
3992 u8 scheduling_hierarchy[0x8];
3993 u8 reserved_at_48[0x18];
3995 u8 scheduling_element_id[0x20];
3997 u8 reserved_at_80[0x180];
4000 struct mlx5_ifc_query_rqt_out_bits {
4002 u8 reserved_at_8[0x18];
4006 u8 reserved_at_40[0xc0];
4008 struct mlx5_ifc_rqtc_bits rqt_context;
4011 struct mlx5_ifc_query_rqt_in_bits {
4013 u8 reserved_at_10[0x10];
4015 u8 reserved_at_20[0x10];
4018 u8 reserved_at_40[0x8];
4021 u8 reserved_at_60[0x20];
4024 struct mlx5_ifc_query_rq_out_bits {
4026 u8 reserved_at_8[0x18];
4030 u8 reserved_at_40[0xc0];
4032 struct mlx5_ifc_rqc_bits rq_context;
4035 struct mlx5_ifc_query_rq_in_bits {
4037 u8 reserved_at_10[0x10];
4039 u8 reserved_at_20[0x10];
4042 u8 reserved_at_40[0x8];
4045 u8 reserved_at_60[0x20];
4048 struct mlx5_ifc_query_roce_address_out_bits {
4050 u8 reserved_at_8[0x18];
4054 u8 reserved_at_40[0x40];
4056 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4059 struct mlx5_ifc_query_roce_address_in_bits {
4061 u8 reserved_at_10[0x10];
4063 u8 reserved_at_20[0x10];
4066 u8 roce_address_index[0x10];
4067 u8 reserved_at_50[0xc];
4068 u8 vhca_port_num[0x4];
4070 u8 reserved_at_60[0x20];
4073 struct mlx5_ifc_query_rmp_out_bits {
4075 u8 reserved_at_8[0x18];
4079 u8 reserved_at_40[0xc0];
4081 struct mlx5_ifc_rmpc_bits rmp_context;
4084 struct mlx5_ifc_query_rmp_in_bits {
4086 u8 reserved_at_10[0x10];
4088 u8 reserved_at_20[0x10];
4091 u8 reserved_at_40[0x8];
4094 u8 reserved_at_60[0x20];
4097 struct mlx5_ifc_query_qp_out_bits {
4099 u8 reserved_at_8[0x18];
4103 u8 reserved_at_40[0x40];
4105 u8 opt_param_mask[0x20];
4107 u8 reserved_at_a0[0x20];
4109 struct mlx5_ifc_qpc_bits qpc;
4111 u8 reserved_at_800[0x80];
4116 struct mlx5_ifc_query_qp_in_bits {
4118 u8 reserved_at_10[0x10];
4120 u8 reserved_at_20[0x10];
4123 u8 reserved_at_40[0x8];
4126 u8 reserved_at_60[0x20];
4129 struct mlx5_ifc_query_q_counter_out_bits {
4131 u8 reserved_at_8[0x18];
4135 u8 reserved_at_40[0x40];
4137 u8 rx_write_requests[0x20];
4139 u8 reserved_at_a0[0x20];
4141 u8 rx_read_requests[0x20];
4143 u8 reserved_at_e0[0x20];
4145 u8 rx_atomic_requests[0x20];
4147 u8 reserved_at_120[0x20];
4149 u8 rx_dct_connect[0x20];
4151 u8 reserved_at_160[0x20];
4153 u8 out_of_buffer[0x20];
4155 u8 reserved_at_1a0[0x20];
4157 u8 out_of_sequence[0x20];
4159 u8 reserved_at_1e0[0x20];
4161 u8 duplicate_request[0x20];
4163 u8 reserved_at_220[0x20];
4165 u8 rnr_nak_retry_err[0x20];
4167 u8 reserved_at_260[0x20];
4169 u8 packet_seq_err[0x20];
4171 u8 reserved_at_2a0[0x20];
4173 u8 implied_nak_seq_err[0x20];
4175 u8 reserved_at_2e0[0x20];
4177 u8 local_ack_timeout_err[0x20];
4179 u8 reserved_at_320[0xa0];
4181 u8 resp_local_length_error[0x20];
4183 u8 req_local_length_error[0x20];
4185 u8 resp_local_qp_error[0x20];
4187 u8 local_operation_error[0x20];
4189 u8 resp_local_protection[0x20];
4191 u8 req_local_protection[0x20];
4193 u8 resp_cqe_error[0x20];
4195 u8 req_cqe_error[0x20];
4197 u8 req_mw_binding[0x20];
4199 u8 req_bad_response[0x20];
4201 u8 req_remote_invalid_request[0x20];
4203 u8 resp_remote_invalid_request[0x20];
4205 u8 req_remote_access_errors[0x20];
4207 u8 resp_remote_access_errors[0x20];
4209 u8 req_remote_operation_errors[0x20];
4211 u8 req_transport_retries_exceeded[0x20];
4213 u8 cq_overflow[0x20];
4215 u8 resp_cqe_flush_error[0x20];
4217 u8 req_cqe_flush_error[0x20];
4219 u8 reserved_at_620[0x1e0];
4222 struct mlx5_ifc_query_q_counter_in_bits {
4224 u8 reserved_at_10[0x10];
4226 u8 reserved_at_20[0x10];
4229 u8 reserved_at_40[0x80];
4232 u8 reserved_at_c1[0x1f];
4234 u8 reserved_at_e0[0x18];
4235 u8 counter_set_id[0x8];
4238 struct mlx5_ifc_query_pages_out_bits {
4240 u8 reserved_at_8[0x18];
4244 u8 reserved_at_40[0x10];
4245 u8 function_id[0x10];
4251 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4252 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4253 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4256 struct mlx5_ifc_query_pages_in_bits {
4258 u8 reserved_at_10[0x10];
4260 u8 reserved_at_20[0x10];
4263 u8 reserved_at_40[0x10];
4264 u8 function_id[0x10];
4266 u8 reserved_at_60[0x20];
4269 struct mlx5_ifc_query_nic_vport_context_out_bits {
4271 u8 reserved_at_8[0x18];
4275 u8 reserved_at_40[0x40];
4277 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4280 struct mlx5_ifc_query_nic_vport_context_in_bits {
4282 u8 reserved_at_10[0x10];
4284 u8 reserved_at_20[0x10];
4287 u8 other_vport[0x1];
4288 u8 reserved_at_41[0xf];
4289 u8 vport_number[0x10];
4291 u8 reserved_at_60[0x5];
4292 u8 allowed_list_type[0x3];
4293 u8 reserved_at_68[0x18];
4296 struct mlx5_ifc_query_mkey_out_bits {
4298 u8 reserved_at_8[0x18];
4302 u8 reserved_at_40[0x40];
4304 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4306 u8 reserved_at_280[0x600];
4308 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4310 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4313 struct mlx5_ifc_query_mkey_in_bits {
4315 u8 reserved_at_10[0x10];
4317 u8 reserved_at_20[0x10];
4320 u8 reserved_at_40[0x8];
4321 u8 mkey_index[0x18];
4324 u8 reserved_at_61[0x1f];
4327 struct mlx5_ifc_query_mad_demux_out_bits {
4329 u8 reserved_at_8[0x18];
4333 u8 reserved_at_40[0x40];
4335 u8 mad_dumux_parameters_block[0x20];
4338 struct mlx5_ifc_query_mad_demux_in_bits {
4340 u8 reserved_at_10[0x10];
4342 u8 reserved_at_20[0x10];
4345 u8 reserved_at_40[0x40];
4348 struct mlx5_ifc_query_l2_table_entry_out_bits {
4350 u8 reserved_at_8[0x18];
4354 u8 reserved_at_40[0xa0];
4356 u8 reserved_at_e0[0x13];
4360 struct mlx5_ifc_mac_address_layout_bits mac_address;
4362 u8 reserved_at_140[0xc0];
4365 struct mlx5_ifc_query_l2_table_entry_in_bits {
4367 u8 reserved_at_10[0x10];
4369 u8 reserved_at_20[0x10];
4372 u8 reserved_at_40[0x60];
4374 u8 reserved_at_a0[0x8];
4375 u8 table_index[0x18];
4377 u8 reserved_at_c0[0x140];
4380 struct mlx5_ifc_query_issi_out_bits {
4382 u8 reserved_at_8[0x18];
4386 u8 reserved_at_40[0x10];
4387 u8 current_issi[0x10];
4389 u8 reserved_at_60[0xa0];
4391 u8 reserved_at_100[76][0x8];
4392 u8 supported_issi_dw0[0x20];
4395 struct mlx5_ifc_query_issi_in_bits {
4397 u8 reserved_at_10[0x10];
4399 u8 reserved_at_20[0x10];
4402 u8 reserved_at_40[0x40];
4405 struct mlx5_ifc_set_driver_version_out_bits {
4407 u8 reserved_0[0x18];
4410 u8 reserved_1[0x40];
4413 struct mlx5_ifc_set_driver_version_in_bits {
4415 u8 reserved_0[0x10];
4417 u8 reserved_1[0x10];
4420 u8 reserved_2[0x40];
4421 u8 driver_version[64][0x8];
4424 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4426 u8 reserved_at_8[0x18];
4430 u8 reserved_at_40[0x40];
4432 struct mlx5_ifc_pkey_bits pkey[0];
4435 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4437 u8 reserved_at_10[0x10];
4439 u8 reserved_at_20[0x10];
4442 u8 other_vport[0x1];
4443 u8 reserved_at_41[0xb];
4445 u8 vport_number[0x10];
4447 u8 reserved_at_60[0x10];
4448 u8 pkey_index[0x10];
4452 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4453 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4454 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4457 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4459 u8 reserved_at_8[0x18];
4463 u8 reserved_at_40[0x20];
4466 u8 reserved_at_70[0x10];
4468 struct mlx5_ifc_array128_auto_bits gid[0];
4471 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4473 u8 reserved_at_10[0x10];
4475 u8 reserved_at_20[0x10];
4478 u8 other_vport[0x1];
4479 u8 reserved_at_41[0xb];
4481 u8 vport_number[0x10];
4483 u8 reserved_at_60[0x10];
4487 struct mlx5_ifc_query_hca_vport_context_out_bits {
4489 u8 reserved_at_8[0x18];
4493 u8 reserved_at_40[0x40];
4495 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4498 struct mlx5_ifc_query_hca_vport_context_in_bits {
4500 u8 reserved_at_10[0x10];
4502 u8 reserved_at_20[0x10];
4505 u8 other_vport[0x1];
4506 u8 reserved_at_41[0xb];
4508 u8 vport_number[0x10];
4510 u8 reserved_at_60[0x20];
4513 struct mlx5_ifc_query_hca_cap_out_bits {
4515 u8 reserved_at_8[0x18];
4519 u8 reserved_at_40[0x40];
4521 union mlx5_ifc_hca_cap_union_bits capability;
4524 struct mlx5_ifc_query_hca_cap_in_bits {
4526 u8 reserved_at_10[0x10];
4528 u8 reserved_at_20[0x10];
4531 u8 reserved_at_40[0x40];
4534 struct mlx5_ifc_query_flow_table_out_bits {
4536 u8 reserved_at_8[0x18];
4540 u8 reserved_at_40[0x80];
4542 u8 reserved_at_c0[0x8];
4544 u8 reserved_at_d0[0x8];
4547 u8 reserved_at_e0[0x120];
4550 struct mlx5_ifc_query_flow_table_in_bits {
4552 u8 reserved_at_10[0x10];
4554 u8 reserved_at_20[0x10];
4557 u8 reserved_at_40[0x40];
4560 u8 reserved_at_88[0x18];
4562 u8 reserved_at_a0[0x8];
4565 u8 reserved_at_c0[0x140];
4568 struct mlx5_ifc_query_fte_out_bits {
4570 u8 reserved_at_8[0x18];
4574 u8 reserved_at_40[0x1c0];
4576 struct mlx5_ifc_flow_context_bits flow_context;
4579 struct mlx5_ifc_query_fte_in_bits {
4581 u8 reserved_at_10[0x10];
4583 u8 reserved_at_20[0x10];
4586 u8 reserved_at_40[0x40];
4589 u8 reserved_at_88[0x18];
4591 u8 reserved_at_a0[0x8];
4594 u8 reserved_at_c0[0x40];
4596 u8 flow_index[0x20];
4598 u8 reserved_at_120[0xe0];
4602 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4603 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4604 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4605 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0X3,
4608 struct mlx5_ifc_query_flow_group_out_bits {
4610 u8 reserved_at_8[0x18];
4614 u8 reserved_at_40[0xa0];
4616 u8 start_flow_index[0x20];
4618 u8 reserved_at_100[0x20];
4620 u8 end_flow_index[0x20];
4622 u8 reserved_at_140[0xa0];
4624 u8 reserved_at_1e0[0x18];
4625 u8 match_criteria_enable[0x8];
4627 struct mlx5_ifc_fte_match_param_bits match_criteria;
4629 u8 reserved_at_1200[0xe00];
4632 struct mlx5_ifc_query_flow_group_in_bits {
4634 u8 reserved_at_10[0x10];
4636 u8 reserved_at_20[0x10];
4639 u8 reserved_at_40[0x40];
4642 u8 reserved_at_88[0x18];
4644 u8 reserved_at_a0[0x8];
4649 u8 reserved_at_e0[0x120];
4652 struct mlx5_ifc_query_flow_counter_out_bits {
4654 u8 reserved_at_8[0x18];
4658 u8 reserved_at_40[0x40];
4660 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4663 struct mlx5_ifc_query_flow_counter_in_bits {
4665 u8 reserved_at_10[0x10];
4667 u8 reserved_at_20[0x10];
4670 u8 reserved_at_40[0x80];
4673 u8 reserved_at_c1[0xf];
4674 u8 num_of_counters[0x10];
4676 u8 flow_counter_id[0x20];
4679 struct mlx5_ifc_query_esw_vport_context_out_bits {
4681 u8 reserved_at_8[0x18];
4685 u8 reserved_at_40[0x40];
4687 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4690 struct mlx5_ifc_query_esw_vport_context_in_bits {
4692 u8 reserved_at_10[0x10];
4694 u8 reserved_at_20[0x10];
4697 u8 other_vport[0x1];
4698 u8 reserved_at_41[0xf];
4699 u8 vport_number[0x10];
4701 u8 reserved_at_60[0x20];
4704 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4706 u8 reserved_at_8[0x18];
4710 u8 reserved_at_40[0x40];
4713 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4714 u8 reserved_at_0[0x1c];
4715 u8 vport_cvlan_insert[0x1];
4716 u8 vport_svlan_insert[0x1];
4717 u8 vport_cvlan_strip[0x1];
4718 u8 vport_svlan_strip[0x1];
4721 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4723 u8 reserved_at_10[0x10];
4725 u8 reserved_at_20[0x10];
4728 u8 other_vport[0x1];
4729 u8 reserved_at_41[0xf];
4730 u8 vport_number[0x10];
4732 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4734 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4737 struct mlx5_ifc_query_eq_out_bits {
4739 u8 reserved_at_8[0x18];
4743 u8 reserved_at_40[0x40];
4745 struct mlx5_ifc_eqc_bits eq_context_entry;
4747 u8 reserved_at_280[0x40];
4749 u8 event_bitmask[0x40];
4751 u8 reserved_at_300[0x580];
4756 struct mlx5_ifc_query_eq_in_bits {
4758 u8 reserved_at_10[0x10];
4760 u8 reserved_at_20[0x10];
4763 u8 reserved_at_40[0x18];
4766 u8 reserved_at_60[0x20];
4769 struct mlx5_ifc_encap_header_in_bits {
4770 u8 reserved_at_0[0x5];
4771 u8 header_type[0x3];
4772 u8 reserved_at_8[0xe];
4773 u8 encap_header_size[0xa];
4775 u8 reserved_at_20[0x10];
4776 u8 encap_header[2][0x8];
4778 u8 more_encap_header[0][0x8];
4781 struct mlx5_ifc_query_encap_header_out_bits {
4783 u8 reserved_at_8[0x18];
4787 u8 reserved_at_40[0xa0];
4789 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4792 struct mlx5_ifc_query_encap_header_in_bits {
4794 u8 reserved_at_10[0x10];
4796 u8 reserved_at_20[0x10];
4801 u8 reserved_at_60[0xa0];
4804 struct mlx5_ifc_alloc_encap_header_out_bits {
4806 u8 reserved_at_8[0x18];
4812 u8 reserved_at_60[0x20];
4815 struct mlx5_ifc_alloc_encap_header_in_bits {
4817 u8 reserved_at_10[0x10];
4819 u8 reserved_at_20[0x10];
4822 u8 reserved_at_40[0xa0];
4824 struct mlx5_ifc_encap_header_in_bits encap_header;
4827 struct mlx5_ifc_dealloc_encap_header_out_bits {
4829 u8 reserved_at_8[0x18];
4833 u8 reserved_at_40[0x40];
4836 struct mlx5_ifc_dealloc_encap_header_in_bits {
4838 u8 reserved_at_10[0x10];
4840 u8 reserved_20[0x10];
4845 u8 reserved_60[0x20];
4848 struct mlx5_ifc_set_action_in_bits {
4849 u8 action_type[0x4];
4851 u8 reserved_at_10[0x3];
4853 u8 reserved_at_18[0x3];
4859 struct mlx5_ifc_add_action_in_bits {
4860 u8 action_type[0x4];
4862 u8 reserved_at_10[0x10];
4867 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4868 struct mlx5_ifc_set_action_in_bits set_action_in;
4869 struct mlx5_ifc_add_action_in_bits add_action_in;
4870 u8 reserved_at_0[0x40];
4874 MLX5_ACTION_TYPE_SET = 0x1,
4875 MLX5_ACTION_TYPE_ADD = 0x2,
4879 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
4880 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
4881 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
4882 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
4883 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
4884 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
4885 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
4886 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
4887 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
4888 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
4889 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
4890 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
4891 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
4892 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
4893 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
4894 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
4895 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
4896 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
4897 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
4898 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
4899 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
4900 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
4901 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
4904 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4906 u8 reserved_at_8[0x18];
4910 u8 modify_header_id[0x20];
4912 u8 reserved_at_60[0x20];
4915 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4917 u8 reserved_at_10[0x10];
4919 u8 reserved_at_20[0x10];
4922 u8 reserved_at_40[0x20];
4925 u8 reserved_at_68[0x10];
4926 u8 num_of_actions[0x8];
4928 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4931 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4933 u8 reserved_at_8[0x18];
4937 u8 reserved_at_40[0x40];
4940 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4942 u8 reserved_at_10[0x10];
4944 u8 reserved_at_20[0x10];
4947 u8 modify_header_id[0x20];
4949 u8 reserved_at_60[0x20];
4952 struct mlx5_ifc_query_dct_out_bits {
4954 u8 reserved_at_8[0x18];
4958 u8 reserved_at_40[0x40];
4960 struct mlx5_ifc_dctc_bits dct_context_entry;
4962 u8 reserved_at_280[0x180];
4965 struct mlx5_ifc_query_dct_in_bits {
4967 u8 reserved_at_10[0x10];
4969 u8 reserved_at_20[0x10];
4972 u8 reserved_at_40[0x8];
4975 u8 reserved_at_60[0x20];
4978 struct mlx5_ifc_query_cq_out_bits {
4980 u8 reserved_at_8[0x18];
4984 u8 reserved_at_40[0x40];
4986 struct mlx5_ifc_cqc_bits cq_context;
4988 u8 reserved_at_280[0x600];
4993 struct mlx5_ifc_query_cq_in_bits {
4995 u8 reserved_at_10[0x10];
4997 u8 reserved_at_20[0x10];
5000 u8 reserved_at_40[0x8];
5003 u8 reserved_at_60[0x20];
5006 struct mlx5_ifc_query_cong_status_out_bits {
5008 u8 reserved_at_8[0x18];
5012 u8 reserved_at_40[0x20];
5016 u8 reserved_at_62[0x1e];
5019 struct mlx5_ifc_query_cong_status_in_bits {
5021 u8 reserved_at_10[0x10];
5023 u8 reserved_at_20[0x10];
5026 u8 reserved_at_40[0x18];
5028 u8 cong_protocol[0x4];
5030 u8 reserved_at_60[0x20];
5033 struct mlx5_ifc_query_cong_statistics_out_bits {
5035 u8 reserved_at_8[0x18];
5039 u8 reserved_at_40[0x40];
5041 u8 rp_cur_flows[0x20];
5045 u8 rp_cnp_ignored_high[0x20];
5047 u8 rp_cnp_ignored_low[0x20];
5049 u8 rp_cnp_handled_high[0x20];
5051 u8 rp_cnp_handled_low[0x20];
5053 u8 reserved_at_140[0x100];
5055 u8 time_stamp_high[0x20];
5057 u8 time_stamp_low[0x20];
5059 u8 accumulators_period[0x20];
5061 u8 np_ecn_marked_roce_packets_high[0x20];
5063 u8 np_ecn_marked_roce_packets_low[0x20];
5065 u8 np_cnp_sent_high[0x20];
5067 u8 np_cnp_sent_low[0x20];
5069 u8 reserved_at_320[0x560];
5072 struct mlx5_ifc_query_cong_statistics_in_bits {
5074 u8 reserved_at_10[0x10];
5076 u8 reserved_at_20[0x10];
5080 u8 reserved_at_41[0x1f];
5082 u8 reserved_at_60[0x20];
5085 struct mlx5_ifc_query_cong_params_out_bits {
5087 u8 reserved_at_8[0x18];
5091 u8 reserved_at_40[0x40];
5093 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5096 struct mlx5_ifc_query_cong_params_in_bits {
5098 u8 reserved_at_10[0x10];
5100 u8 reserved_at_20[0x10];
5103 u8 reserved_at_40[0x1c];
5104 u8 cong_protocol[0x4];
5106 u8 reserved_at_60[0x20];
5109 struct mlx5_ifc_query_adapter_out_bits {
5111 u8 reserved_at_8[0x18];
5115 u8 reserved_at_40[0x40];
5117 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5120 struct mlx5_ifc_query_adapter_in_bits {
5122 u8 reserved_at_10[0x10];
5124 u8 reserved_at_20[0x10];
5127 u8 reserved_at_40[0x40];
5130 struct mlx5_ifc_qp_2rst_out_bits {
5132 u8 reserved_at_8[0x18];
5136 u8 reserved_at_40[0x40];
5139 struct mlx5_ifc_qp_2rst_in_bits {
5141 u8 reserved_at_10[0x10];
5143 u8 reserved_at_20[0x10];
5146 u8 reserved_at_40[0x8];
5149 u8 reserved_at_60[0x20];
5152 struct mlx5_ifc_qp_2err_out_bits {
5154 u8 reserved_at_8[0x18];
5158 u8 reserved_at_40[0x40];
5161 struct mlx5_ifc_qp_2err_in_bits {
5163 u8 reserved_at_10[0x10];
5165 u8 reserved_at_20[0x10];
5168 u8 reserved_at_40[0x8];
5171 u8 reserved_at_60[0x20];
5174 struct mlx5_ifc_page_fault_resume_out_bits {
5176 u8 reserved_at_8[0x18];
5180 u8 reserved_at_40[0x40];
5183 struct mlx5_ifc_page_fault_resume_in_bits {
5185 u8 reserved_at_10[0x10];
5187 u8 reserved_at_20[0x10];
5191 u8 reserved_at_41[0x4];
5192 u8 page_fault_type[0x3];
5195 u8 reserved_at_60[0x8];
5199 struct mlx5_ifc_nop_out_bits {
5201 u8 reserved_at_8[0x18];
5205 u8 reserved_at_40[0x40];
5208 struct mlx5_ifc_nop_in_bits {
5210 u8 reserved_at_10[0x10];
5212 u8 reserved_at_20[0x10];
5215 u8 reserved_at_40[0x40];
5218 struct mlx5_ifc_modify_vport_state_out_bits {
5220 u8 reserved_at_8[0x18];
5224 u8 reserved_at_40[0x40];
5227 struct mlx5_ifc_modify_vport_state_in_bits {
5229 u8 reserved_at_10[0x10];
5231 u8 reserved_at_20[0x10];
5234 u8 other_vport[0x1];
5235 u8 reserved_at_41[0xf];
5236 u8 vport_number[0x10];
5238 u8 reserved_at_60[0x18];
5239 u8 admin_state[0x4];
5240 u8 reserved_at_7c[0x4];
5243 struct mlx5_ifc_modify_tis_out_bits {
5245 u8 reserved_at_8[0x18];
5249 u8 reserved_at_40[0x40];
5252 struct mlx5_ifc_modify_tis_bitmask_bits {
5253 u8 reserved_at_0[0x20];
5255 u8 reserved_at_20[0x1d];
5256 u8 lag_tx_port_affinity[0x1];
5257 u8 strict_lag_tx_port_affinity[0x1];
5261 struct mlx5_ifc_modify_tis_in_bits {
5263 u8 reserved_at_10[0x10];
5265 u8 reserved_at_20[0x10];
5268 u8 reserved_at_40[0x8];
5271 u8 reserved_at_60[0x20];
5273 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5275 u8 reserved_at_c0[0x40];
5277 struct mlx5_ifc_tisc_bits ctx;
5280 struct mlx5_ifc_modify_tir_bitmask_bits {
5281 u8 reserved_at_0[0x20];
5283 u8 reserved_at_20[0x1b];
5285 u8 reserved_at_3c[0x1];
5287 u8 reserved_at_3e[0x1];
5291 struct mlx5_ifc_modify_tir_out_bits {
5293 u8 reserved_at_8[0x18];
5297 u8 reserved_at_40[0x40];
5300 struct mlx5_ifc_modify_tir_in_bits {
5302 u8 reserved_at_10[0x10];
5304 u8 reserved_at_20[0x10];
5307 u8 reserved_at_40[0x8];
5310 u8 reserved_at_60[0x20];
5312 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5314 u8 reserved_at_c0[0x40];
5316 struct mlx5_ifc_tirc_bits ctx;
5319 struct mlx5_ifc_modify_sq_out_bits {
5321 u8 reserved_at_8[0x18];
5325 u8 reserved_at_40[0x40];
5328 struct mlx5_ifc_modify_sq_in_bits {
5330 u8 reserved_at_10[0x10];
5332 u8 reserved_at_20[0x10];
5336 u8 reserved_at_44[0x4];
5339 u8 reserved_at_60[0x20];
5341 u8 modify_bitmask[0x40];
5343 u8 reserved_at_c0[0x40];
5345 struct mlx5_ifc_sqc_bits ctx;
5348 struct mlx5_ifc_modify_scheduling_element_out_bits {
5350 u8 reserved_at_8[0x18];
5354 u8 reserved_at_40[0x1c0];
5358 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5359 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5362 struct mlx5_ifc_modify_scheduling_element_in_bits {
5364 u8 reserved_at_10[0x10];
5366 u8 reserved_at_20[0x10];
5369 u8 scheduling_hierarchy[0x8];
5370 u8 reserved_at_48[0x18];
5372 u8 scheduling_element_id[0x20];
5374 u8 reserved_at_80[0x20];
5376 u8 modify_bitmask[0x20];
5378 u8 reserved_at_c0[0x40];
5380 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5382 u8 reserved_at_300[0x100];
5385 struct mlx5_ifc_modify_rqt_out_bits {
5387 u8 reserved_at_8[0x18];
5391 u8 reserved_at_40[0x40];
5394 struct mlx5_ifc_rqt_bitmask_bits {
5395 u8 reserved_at_0[0x20];
5397 u8 reserved_at_20[0x1f];
5401 struct mlx5_ifc_modify_rqt_in_bits {
5403 u8 reserved_at_10[0x10];
5405 u8 reserved_at_20[0x10];
5408 u8 reserved_at_40[0x8];
5411 u8 reserved_at_60[0x20];
5413 struct mlx5_ifc_rqt_bitmask_bits bitmask;
5415 u8 reserved_at_c0[0x40];
5417 struct mlx5_ifc_rqtc_bits ctx;
5420 struct mlx5_ifc_modify_rq_out_bits {
5422 u8 reserved_at_8[0x18];
5426 u8 reserved_at_40[0x40];
5430 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5431 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5432 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5435 struct mlx5_ifc_modify_rq_in_bits {
5437 u8 reserved_at_10[0x10];
5439 u8 reserved_at_20[0x10];
5443 u8 reserved_at_44[0x4];
5446 u8 reserved_at_60[0x20];
5448 u8 modify_bitmask[0x40];
5450 u8 reserved_at_c0[0x40];
5452 struct mlx5_ifc_rqc_bits ctx;
5455 struct mlx5_ifc_modify_rmp_out_bits {
5457 u8 reserved_at_8[0x18];
5461 u8 reserved_at_40[0x40];
5464 struct mlx5_ifc_rmp_bitmask_bits {
5465 u8 reserved_at_0[0x20];
5467 u8 reserved_at_20[0x1f];
5471 struct mlx5_ifc_modify_rmp_in_bits {
5473 u8 reserved_at_10[0x10];
5475 u8 reserved_at_20[0x10];
5479 u8 reserved_at_44[0x4];
5482 u8 reserved_at_60[0x20];
5484 struct mlx5_ifc_rmp_bitmask_bits bitmask;
5486 u8 reserved_at_c0[0x40];
5488 struct mlx5_ifc_rmpc_bits ctx;
5491 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5493 u8 reserved_at_8[0x18];
5497 u8 reserved_at_40[0x40];
5500 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5501 u8 reserved_at_0[0x12];
5502 u8 affiliation[0x1];
5503 u8 reserved_at_e[0x1];
5504 u8 disable_uc_local_lb[0x1];
5505 u8 disable_mc_local_lb[0x1];
5510 u8 change_event[0x1];
5512 u8 permanent_address[0x1];
5513 u8 addresses_list[0x1];
5515 u8 reserved_at_1f[0x1];
5518 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5520 u8 reserved_at_10[0x10];
5522 u8 reserved_at_20[0x10];
5525 u8 other_vport[0x1];
5526 u8 reserved_at_41[0xf];
5527 u8 vport_number[0x10];
5529 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5531 u8 reserved_at_80[0x780];
5533 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5536 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5538 u8 reserved_at_8[0x18];
5542 u8 reserved_at_40[0x40];
5545 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5547 u8 reserved_at_10[0x10];
5549 u8 reserved_at_20[0x10];
5552 u8 other_vport[0x1];
5553 u8 reserved_at_41[0xb];
5555 u8 vport_number[0x10];
5557 u8 reserved_at_60[0x20];
5559 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5562 struct mlx5_ifc_modify_cq_out_bits {
5564 u8 reserved_at_8[0x18];
5568 u8 reserved_at_40[0x40];
5572 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5573 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5576 struct mlx5_ifc_modify_cq_in_bits {
5578 u8 reserved_at_10[0x10];
5580 u8 reserved_at_20[0x10];
5583 u8 reserved_at_40[0x8];
5586 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5588 struct mlx5_ifc_cqc_bits cq_context;
5590 u8 reserved_at_280[0x600];
5595 struct mlx5_ifc_modify_cong_status_out_bits {
5597 u8 reserved_at_8[0x18];
5601 u8 reserved_at_40[0x40];
5604 struct mlx5_ifc_modify_cong_status_in_bits {
5606 u8 reserved_at_10[0x10];
5608 u8 reserved_at_20[0x10];
5611 u8 reserved_at_40[0x18];
5613 u8 cong_protocol[0x4];
5617 u8 reserved_at_62[0x1e];
5620 struct mlx5_ifc_modify_cong_params_out_bits {
5622 u8 reserved_at_8[0x18];
5626 u8 reserved_at_40[0x40];
5629 struct mlx5_ifc_modify_cong_params_in_bits {
5631 u8 reserved_at_10[0x10];
5633 u8 reserved_at_20[0x10];
5636 u8 reserved_at_40[0x1c];
5637 u8 cong_protocol[0x4];
5639 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5641 u8 reserved_at_80[0x80];
5643 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5646 struct mlx5_ifc_manage_pages_out_bits {
5648 u8 reserved_at_8[0x18];
5652 u8 output_num_entries[0x20];
5654 u8 reserved_at_60[0x20];
5660 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5661 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5662 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5665 struct mlx5_ifc_manage_pages_in_bits {
5667 u8 reserved_at_10[0x10];
5669 u8 reserved_at_20[0x10];
5672 u8 reserved_at_40[0x10];
5673 u8 function_id[0x10];
5675 u8 input_num_entries[0x20];
5680 struct mlx5_ifc_mad_ifc_out_bits {
5682 u8 reserved_at_8[0x18];
5686 u8 reserved_at_40[0x40];
5688 u8 response_mad_packet[256][0x8];
5691 struct mlx5_ifc_mad_ifc_in_bits {
5693 u8 reserved_at_10[0x10];
5695 u8 reserved_at_20[0x10];
5698 u8 remote_lid[0x10];
5699 u8 reserved_at_50[0x8];
5702 u8 reserved_at_60[0x20];
5707 struct mlx5_ifc_init_hca_out_bits {
5709 u8 reserved_at_8[0x18];
5713 u8 reserved_at_40[0x40];
5716 struct mlx5_ifc_init_hca_in_bits {
5718 u8 reserved_at_10[0x10];
5720 u8 reserved_at_20[0x10];
5723 u8 reserved_at_40[0x40];
5724 u8 sw_owner_id[4][0x20];
5727 struct mlx5_ifc_init2rtr_qp_out_bits {
5729 u8 reserved_at_8[0x18];
5733 u8 reserved_at_40[0x40];
5736 struct mlx5_ifc_init2rtr_qp_in_bits {
5738 u8 reserved_at_10[0x10];
5740 u8 reserved_at_20[0x10];
5743 u8 reserved_at_40[0x8];
5746 u8 reserved_at_60[0x20];
5748 u8 opt_param_mask[0x20];
5750 u8 reserved_at_a0[0x20];
5752 struct mlx5_ifc_qpc_bits qpc;
5754 u8 reserved_at_800[0x80];
5757 struct mlx5_ifc_init2init_qp_out_bits {
5759 u8 reserved_at_8[0x18];
5763 u8 reserved_at_40[0x40];
5766 struct mlx5_ifc_init2init_qp_in_bits {
5768 u8 reserved_at_10[0x10];
5770 u8 reserved_at_20[0x10];
5773 u8 reserved_at_40[0x8];
5776 u8 reserved_at_60[0x20];
5778 u8 opt_param_mask[0x20];
5780 u8 reserved_at_a0[0x20];
5782 struct mlx5_ifc_qpc_bits qpc;
5784 u8 reserved_at_800[0x80];
5787 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5789 u8 reserved_at_8[0x18];
5793 u8 reserved_at_40[0x40];
5795 u8 packet_headers_log[128][0x8];
5797 u8 packet_syndrome[64][0x8];
5800 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5802 u8 reserved_at_10[0x10];
5804 u8 reserved_at_20[0x10];
5807 u8 reserved_at_40[0x40];
5810 struct mlx5_ifc_gen_eqe_in_bits {
5812 u8 reserved_at_10[0x10];
5814 u8 reserved_at_20[0x10];
5817 u8 reserved_at_40[0x18];
5820 u8 reserved_at_60[0x20];
5825 struct mlx5_ifc_gen_eq_out_bits {
5827 u8 reserved_at_8[0x18];
5831 u8 reserved_at_40[0x40];
5834 struct mlx5_ifc_enable_hca_out_bits {
5836 u8 reserved_at_8[0x18];
5840 u8 reserved_at_40[0x20];
5843 struct mlx5_ifc_enable_hca_in_bits {
5845 u8 reserved_at_10[0x10];
5847 u8 reserved_at_20[0x10];
5850 u8 reserved_at_40[0x10];
5851 u8 function_id[0x10];
5853 u8 reserved_at_60[0x20];
5856 struct mlx5_ifc_drain_dct_out_bits {
5858 u8 reserved_at_8[0x18];
5862 u8 reserved_at_40[0x40];
5865 struct mlx5_ifc_drain_dct_in_bits {
5867 u8 reserved_at_10[0x10];
5869 u8 reserved_at_20[0x10];
5872 u8 reserved_at_40[0x8];
5875 u8 reserved_at_60[0x20];
5878 struct mlx5_ifc_disable_hca_out_bits {
5880 u8 reserved_at_8[0x18];
5884 u8 reserved_at_40[0x20];
5887 struct mlx5_ifc_disable_hca_in_bits {
5889 u8 reserved_at_10[0x10];
5891 u8 reserved_at_20[0x10];
5894 u8 reserved_at_40[0x10];
5895 u8 function_id[0x10];
5897 u8 reserved_at_60[0x20];
5900 struct mlx5_ifc_detach_from_mcg_out_bits {
5902 u8 reserved_at_8[0x18];
5906 u8 reserved_at_40[0x40];
5909 struct mlx5_ifc_detach_from_mcg_in_bits {
5911 u8 reserved_at_10[0x10];
5913 u8 reserved_at_20[0x10];
5916 u8 reserved_at_40[0x8];
5919 u8 reserved_at_60[0x20];
5921 u8 multicast_gid[16][0x8];
5924 struct mlx5_ifc_destroy_xrq_out_bits {
5926 u8 reserved_at_8[0x18];
5930 u8 reserved_at_40[0x40];
5933 struct mlx5_ifc_destroy_xrq_in_bits {
5935 u8 reserved_at_10[0x10];
5937 u8 reserved_at_20[0x10];
5940 u8 reserved_at_40[0x8];
5943 u8 reserved_at_60[0x20];
5946 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5948 u8 reserved_at_8[0x18];
5952 u8 reserved_at_40[0x40];
5955 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5957 u8 reserved_at_10[0x10];
5959 u8 reserved_at_20[0x10];
5962 u8 reserved_at_40[0x8];
5965 u8 reserved_at_60[0x20];
5968 struct mlx5_ifc_destroy_tis_out_bits {
5970 u8 reserved_at_8[0x18];
5974 u8 reserved_at_40[0x40];
5977 struct mlx5_ifc_destroy_tis_in_bits {
5979 u8 reserved_at_10[0x10];
5981 u8 reserved_at_20[0x10];
5984 u8 reserved_at_40[0x8];
5987 u8 reserved_at_60[0x20];
5990 struct mlx5_ifc_destroy_tir_out_bits {
5992 u8 reserved_at_8[0x18];
5996 u8 reserved_at_40[0x40];
5999 struct mlx5_ifc_destroy_tir_in_bits {
6001 u8 reserved_at_10[0x10];
6003 u8 reserved_at_20[0x10];
6006 u8 reserved_at_40[0x8];
6009 u8 reserved_at_60[0x20];
6012 struct mlx5_ifc_destroy_srq_out_bits {
6014 u8 reserved_at_8[0x18];
6018 u8 reserved_at_40[0x40];
6021 struct mlx5_ifc_destroy_srq_in_bits {
6023 u8 reserved_at_10[0x10];
6025 u8 reserved_at_20[0x10];
6028 u8 reserved_at_40[0x8];
6031 u8 reserved_at_60[0x20];
6034 struct mlx5_ifc_destroy_sq_out_bits {
6036 u8 reserved_at_8[0x18];
6040 u8 reserved_at_40[0x40];
6043 struct mlx5_ifc_destroy_sq_in_bits {
6045 u8 reserved_at_10[0x10];
6047 u8 reserved_at_20[0x10];
6050 u8 reserved_at_40[0x8];
6053 u8 reserved_at_60[0x20];
6056 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6058 u8 reserved_at_8[0x18];
6062 u8 reserved_at_40[0x1c0];
6065 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6067 u8 reserved_at_10[0x10];
6069 u8 reserved_at_20[0x10];
6072 u8 scheduling_hierarchy[0x8];
6073 u8 reserved_at_48[0x18];
6075 u8 scheduling_element_id[0x20];
6077 u8 reserved_at_80[0x180];
6080 struct mlx5_ifc_destroy_rqt_out_bits {
6082 u8 reserved_at_8[0x18];
6086 u8 reserved_at_40[0x40];
6089 struct mlx5_ifc_destroy_rqt_in_bits {
6091 u8 reserved_at_10[0x10];
6093 u8 reserved_at_20[0x10];
6096 u8 reserved_at_40[0x8];
6099 u8 reserved_at_60[0x20];
6102 struct mlx5_ifc_destroy_rq_out_bits {
6104 u8 reserved_at_8[0x18];
6108 u8 reserved_at_40[0x40];
6111 struct mlx5_ifc_destroy_rq_in_bits {
6113 u8 reserved_at_10[0x10];
6115 u8 reserved_at_20[0x10];
6118 u8 reserved_at_40[0x8];
6121 u8 reserved_at_60[0x20];
6124 struct mlx5_ifc_set_delay_drop_params_in_bits {
6126 u8 reserved_at_10[0x10];
6128 u8 reserved_at_20[0x10];
6131 u8 reserved_at_40[0x20];
6133 u8 reserved_at_60[0x10];
6134 u8 delay_drop_timeout[0x10];
6137 struct mlx5_ifc_set_delay_drop_params_out_bits {
6139 u8 reserved_at_8[0x18];
6143 u8 reserved_at_40[0x40];
6146 struct mlx5_ifc_destroy_rmp_out_bits {
6148 u8 reserved_at_8[0x18];
6152 u8 reserved_at_40[0x40];
6155 struct mlx5_ifc_destroy_rmp_in_bits {
6157 u8 reserved_at_10[0x10];
6159 u8 reserved_at_20[0x10];
6162 u8 reserved_at_40[0x8];
6165 u8 reserved_at_60[0x20];
6168 struct mlx5_ifc_destroy_qp_out_bits {
6170 u8 reserved_at_8[0x18];
6174 u8 reserved_at_40[0x40];
6177 struct mlx5_ifc_destroy_qp_in_bits {
6179 u8 reserved_at_10[0x10];
6181 u8 reserved_at_20[0x10];
6184 u8 reserved_at_40[0x8];
6187 u8 reserved_at_60[0x20];
6190 struct mlx5_ifc_destroy_psv_out_bits {
6192 u8 reserved_at_8[0x18];
6196 u8 reserved_at_40[0x40];
6199 struct mlx5_ifc_destroy_psv_in_bits {
6201 u8 reserved_at_10[0x10];
6203 u8 reserved_at_20[0x10];
6206 u8 reserved_at_40[0x8];
6209 u8 reserved_at_60[0x20];
6212 struct mlx5_ifc_destroy_mkey_out_bits {
6214 u8 reserved_at_8[0x18];
6218 u8 reserved_at_40[0x40];
6221 struct mlx5_ifc_destroy_mkey_in_bits {
6223 u8 reserved_at_10[0x10];
6225 u8 reserved_at_20[0x10];
6228 u8 reserved_at_40[0x8];
6229 u8 mkey_index[0x18];
6231 u8 reserved_at_60[0x20];
6234 struct mlx5_ifc_destroy_flow_table_out_bits {
6236 u8 reserved_at_8[0x18];
6240 u8 reserved_at_40[0x40];
6243 struct mlx5_ifc_destroy_flow_table_in_bits {
6245 u8 reserved_at_10[0x10];
6247 u8 reserved_at_20[0x10];
6250 u8 other_vport[0x1];
6251 u8 reserved_at_41[0xf];
6252 u8 vport_number[0x10];
6254 u8 reserved_at_60[0x20];
6257 u8 reserved_at_88[0x18];
6259 u8 reserved_at_a0[0x8];
6262 u8 reserved_at_c0[0x140];
6265 struct mlx5_ifc_destroy_flow_group_out_bits {
6267 u8 reserved_at_8[0x18];
6271 u8 reserved_at_40[0x40];
6274 struct mlx5_ifc_destroy_flow_group_in_bits {
6276 u8 reserved_at_10[0x10];
6278 u8 reserved_at_20[0x10];
6281 u8 other_vport[0x1];
6282 u8 reserved_at_41[0xf];
6283 u8 vport_number[0x10];
6285 u8 reserved_at_60[0x20];
6288 u8 reserved_at_88[0x18];
6290 u8 reserved_at_a0[0x8];
6295 u8 reserved_at_e0[0x120];
6298 struct mlx5_ifc_destroy_eq_out_bits {
6300 u8 reserved_at_8[0x18];
6304 u8 reserved_at_40[0x40];
6307 struct mlx5_ifc_destroy_eq_in_bits {
6309 u8 reserved_at_10[0x10];
6311 u8 reserved_at_20[0x10];
6314 u8 reserved_at_40[0x18];
6317 u8 reserved_at_60[0x20];
6320 struct mlx5_ifc_destroy_dct_out_bits {
6322 u8 reserved_at_8[0x18];
6326 u8 reserved_at_40[0x40];
6329 struct mlx5_ifc_destroy_dct_in_bits {
6331 u8 reserved_at_10[0x10];
6333 u8 reserved_at_20[0x10];
6336 u8 reserved_at_40[0x8];
6339 u8 reserved_at_60[0x20];
6342 struct mlx5_ifc_destroy_cq_out_bits {
6344 u8 reserved_at_8[0x18];
6348 u8 reserved_at_40[0x40];
6351 struct mlx5_ifc_destroy_cq_in_bits {
6353 u8 reserved_at_10[0x10];
6355 u8 reserved_at_20[0x10];
6358 u8 reserved_at_40[0x8];
6361 u8 reserved_at_60[0x20];
6364 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6366 u8 reserved_at_8[0x18];
6370 u8 reserved_at_40[0x40];
6373 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6375 u8 reserved_at_10[0x10];
6377 u8 reserved_at_20[0x10];
6380 u8 reserved_at_40[0x20];
6382 u8 reserved_at_60[0x10];
6383 u8 vxlan_udp_port[0x10];
6386 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6388 u8 reserved_at_8[0x18];
6392 u8 reserved_at_40[0x40];
6395 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6397 u8 reserved_at_10[0x10];
6399 u8 reserved_at_20[0x10];
6402 u8 reserved_at_40[0x60];
6404 u8 reserved_at_a0[0x8];
6405 u8 table_index[0x18];
6407 u8 reserved_at_c0[0x140];
6410 struct mlx5_ifc_delete_fte_out_bits {
6412 u8 reserved_at_8[0x18];
6416 u8 reserved_at_40[0x40];
6419 struct mlx5_ifc_delete_fte_in_bits {
6421 u8 reserved_at_10[0x10];
6423 u8 reserved_at_20[0x10];
6426 u8 other_vport[0x1];
6427 u8 reserved_at_41[0xf];
6428 u8 vport_number[0x10];
6430 u8 reserved_at_60[0x20];
6433 u8 reserved_at_88[0x18];
6435 u8 reserved_at_a0[0x8];
6438 u8 reserved_at_c0[0x40];
6440 u8 flow_index[0x20];
6442 u8 reserved_at_120[0xe0];
6445 struct mlx5_ifc_dealloc_xrcd_out_bits {
6447 u8 reserved_at_8[0x18];
6451 u8 reserved_at_40[0x40];
6454 struct mlx5_ifc_dealloc_xrcd_in_bits {
6456 u8 reserved_at_10[0x10];
6458 u8 reserved_at_20[0x10];
6461 u8 reserved_at_40[0x8];
6464 u8 reserved_at_60[0x20];
6467 struct mlx5_ifc_dealloc_uar_out_bits {
6469 u8 reserved_at_8[0x18];
6473 u8 reserved_at_40[0x40];
6476 struct mlx5_ifc_dealloc_uar_in_bits {
6478 u8 reserved_at_10[0x10];
6480 u8 reserved_at_20[0x10];
6483 u8 reserved_at_40[0x8];
6486 u8 reserved_at_60[0x20];
6489 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6491 u8 reserved_at_8[0x18];
6495 u8 reserved_at_40[0x40];
6498 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6500 u8 reserved_at_10[0x10];
6502 u8 reserved_at_20[0x10];
6505 u8 reserved_at_40[0x8];
6506 u8 transport_domain[0x18];
6508 u8 reserved_at_60[0x20];
6511 struct mlx5_ifc_dealloc_q_counter_out_bits {
6513 u8 reserved_at_8[0x18];
6517 u8 reserved_at_40[0x40];
6520 struct mlx5_ifc_dealloc_q_counter_in_bits {
6522 u8 reserved_at_10[0x10];
6524 u8 reserved_at_20[0x10];
6527 u8 reserved_at_40[0x18];
6528 u8 counter_set_id[0x8];
6530 u8 reserved_at_60[0x20];
6533 struct mlx5_ifc_dealloc_pd_out_bits {
6535 u8 reserved_at_8[0x18];
6539 u8 reserved_at_40[0x40];
6542 struct mlx5_ifc_dealloc_pd_in_bits {
6544 u8 reserved_at_10[0x10];
6546 u8 reserved_at_20[0x10];
6549 u8 reserved_at_40[0x8];
6552 u8 reserved_at_60[0x20];
6555 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6557 u8 reserved_at_8[0x18];
6561 u8 reserved_at_40[0x40];
6564 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6566 u8 reserved_at_10[0x10];
6568 u8 reserved_at_20[0x10];
6571 u8 flow_counter_id[0x20];
6573 u8 reserved_at_60[0x20];
6576 struct mlx5_ifc_create_xrq_out_bits {
6578 u8 reserved_at_8[0x18];
6582 u8 reserved_at_40[0x8];
6585 u8 reserved_at_60[0x20];
6588 struct mlx5_ifc_create_xrq_in_bits {
6590 u8 reserved_at_10[0x10];
6592 u8 reserved_at_20[0x10];
6595 u8 reserved_at_40[0x40];
6597 struct mlx5_ifc_xrqc_bits xrq_context;
6600 struct mlx5_ifc_create_xrc_srq_out_bits {
6602 u8 reserved_at_8[0x18];
6606 u8 reserved_at_40[0x8];
6609 u8 reserved_at_60[0x20];
6612 struct mlx5_ifc_create_xrc_srq_in_bits {
6614 u8 reserved_at_10[0x10];
6616 u8 reserved_at_20[0x10];
6619 u8 reserved_at_40[0x40];
6621 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6623 u8 reserved_at_280[0x600];
6628 struct mlx5_ifc_create_tis_out_bits {
6630 u8 reserved_at_8[0x18];
6634 u8 reserved_at_40[0x8];
6637 u8 reserved_at_60[0x20];
6640 struct mlx5_ifc_create_tis_in_bits {
6642 u8 reserved_at_10[0x10];
6644 u8 reserved_at_20[0x10];
6647 u8 reserved_at_40[0xc0];
6649 struct mlx5_ifc_tisc_bits ctx;
6652 struct mlx5_ifc_create_tir_out_bits {
6654 u8 reserved_at_8[0x18];
6658 u8 reserved_at_40[0x8];
6661 u8 reserved_at_60[0x20];
6664 struct mlx5_ifc_create_tir_in_bits {
6666 u8 reserved_at_10[0x10];
6668 u8 reserved_at_20[0x10];
6671 u8 reserved_at_40[0xc0];
6673 struct mlx5_ifc_tirc_bits ctx;
6676 struct mlx5_ifc_create_srq_out_bits {
6678 u8 reserved_at_8[0x18];
6682 u8 reserved_at_40[0x8];
6685 u8 reserved_at_60[0x20];
6688 struct mlx5_ifc_create_srq_in_bits {
6690 u8 reserved_at_10[0x10];
6692 u8 reserved_at_20[0x10];
6695 u8 reserved_at_40[0x40];
6697 struct mlx5_ifc_srqc_bits srq_context_entry;
6699 u8 reserved_at_280[0x600];
6704 struct mlx5_ifc_create_sq_out_bits {
6706 u8 reserved_at_8[0x18];
6710 u8 reserved_at_40[0x8];
6713 u8 reserved_at_60[0x20];
6716 struct mlx5_ifc_create_sq_in_bits {
6718 u8 reserved_at_10[0x10];
6720 u8 reserved_at_20[0x10];
6723 u8 reserved_at_40[0xc0];
6725 struct mlx5_ifc_sqc_bits ctx;
6728 struct mlx5_ifc_create_scheduling_element_out_bits {
6730 u8 reserved_at_8[0x18];
6734 u8 reserved_at_40[0x40];
6736 u8 scheduling_element_id[0x20];
6738 u8 reserved_at_a0[0x160];
6741 struct mlx5_ifc_create_scheduling_element_in_bits {
6743 u8 reserved_at_10[0x10];
6745 u8 reserved_at_20[0x10];
6748 u8 scheduling_hierarchy[0x8];
6749 u8 reserved_at_48[0x18];
6751 u8 reserved_at_60[0xa0];
6753 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6755 u8 reserved_at_300[0x100];
6758 struct mlx5_ifc_create_rqt_out_bits {
6760 u8 reserved_at_8[0x18];
6764 u8 reserved_at_40[0x8];
6767 u8 reserved_at_60[0x20];
6770 struct mlx5_ifc_create_rqt_in_bits {
6772 u8 reserved_at_10[0x10];
6774 u8 reserved_at_20[0x10];
6777 u8 reserved_at_40[0xc0];
6779 struct mlx5_ifc_rqtc_bits rqt_context;
6782 struct mlx5_ifc_create_rq_out_bits {
6784 u8 reserved_at_8[0x18];
6788 u8 reserved_at_40[0x8];
6791 u8 reserved_at_60[0x20];
6794 struct mlx5_ifc_create_rq_in_bits {
6796 u8 reserved_at_10[0x10];
6798 u8 reserved_at_20[0x10];
6801 u8 reserved_at_40[0xc0];
6803 struct mlx5_ifc_rqc_bits ctx;
6806 struct mlx5_ifc_create_rmp_out_bits {
6808 u8 reserved_at_8[0x18];
6812 u8 reserved_at_40[0x8];
6815 u8 reserved_at_60[0x20];
6818 struct mlx5_ifc_create_rmp_in_bits {
6820 u8 reserved_at_10[0x10];
6822 u8 reserved_at_20[0x10];
6825 u8 reserved_at_40[0xc0];
6827 struct mlx5_ifc_rmpc_bits ctx;
6830 struct mlx5_ifc_create_qp_out_bits {
6832 u8 reserved_at_8[0x18];
6836 u8 reserved_at_40[0x8];
6839 u8 reserved_at_60[0x20];
6842 struct mlx5_ifc_create_qp_in_bits {
6844 u8 reserved_at_10[0x10];
6846 u8 reserved_at_20[0x10];
6849 u8 reserved_at_40[0x40];
6851 u8 opt_param_mask[0x20];
6853 u8 reserved_at_a0[0x20];
6855 struct mlx5_ifc_qpc_bits qpc;
6857 u8 reserved_at_800[0x80];
6862 struct mlx5_ifc_create_psv_out_bits {
6864 u8 reserved_at_8[0x18];
6868 u8 reserved_at_40[0x40];
6870 u8 reserved_at_80[0x8];
6871 u8 psv0_index[0x18];
6873 u8 reserved_at_a0[0x8];
6874 u8 psv1_index[0x18];
6876 u8 reserved_at_c0[0x8];
6877 u8 psv2_index[0x18];
6879 u8 reserved_at_e0[0x8];
6880 u8 psv3_index[0x18];
6883 struct mlx5_ifc_create_psv_in_bits {
6885 u8 reserved_at_10[0x10];
6887 u8 reserved_at_20[0x10];
6891 u8 reserved_at_44[0x4];
6894 u8 reserved_at_60[0x20];
6897 struct mlx5_ifc_create_mkey_out_bits {
6899 u8 reserved_at_8[0x18];
6903 u8 reserved_at_40[0x8];
6904 u8 mkey_index[0x18];
6906 u8 reserved_at_60[0x20];
6909 struct mlx5_ifc_create_mkey_in_bits {
6911 u8 reserved_at_10[0x10];
6913 u8 reserved_at_20[0x10];
6916 u8 reserved_at_40[0x20];
6919 u8 reserved_at_61[0x1f];
6921 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6923 u8 reserved_at_280[0x80];
6925 u8 translations_octword_actual_size[0x20];
6927 u8 reserved_at_320[0x560];
6929 u8 klm_pas_mtt[0][0x20];
6932 struct mlx5_ifc_create_flow_table_out_bits {
6934 u8 reserved_at_8[0x18];
6938 u8 reserved_at_40[0x8];
6941 u8 reserved_at_60[0x20];
6944 struct mlx5_ifc_flow_table_context_bits {
6947 u8 reserved_at_2[0x2];
6948 u8 table_miss_action[0x4];
6950 u8 reserved_at_10[0x8];
6953 u8 reserved_at_20[0x8];
6954 u8 table_miss_id[0x18];
6956 u8 reserved_at_40[0x8];
6957 u8 lag_master_next_table_id[0x18];
6959 u8 reserved_at_60[0xe0];
6962 struct mlx5_ifc_create_flow_table_in_bits {
6964 u8 reserved_at_10[0x10];
6966 u8 reserved_at_20[0x10];
6969 u8 other_vport[0x1];
6970 u8 reserved_at_41[0xf];
6971 u8 vport_number[0x10];
6973 u8 reserved_at_60[0x20];
6976 u8 reserved_at_88[0x18];
6978 u8 reserved_at_a0[0x20];
6980 struct mlx5_ifc_flow_table_context_bits flow_table_context;
6983 struct mlx5_ifc_create_flow_group_out_bits {
6985 u8 reserved_at_8[0x18];
6989 u8 reserved_at_40[0x8];
6992 u8 reserved_at_60[0x20];
6996 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6997 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6998 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6999 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7002 struct mlx5_ifc_create_flow_group_in_bits {
7004 u8 reserved_at_10[0x10];
7006 u8 reserved_at_20[0x10];
7009 u8 other_vport[0x1];
7010 u8 reserved_at_41[0xf];
7011 u8 vport_number[0x10];
7013 u8 reserved_at_60[0x20];
7016 u8 reserved_at_88[0x18];
7018 u8 reserved_at_a0[0x8];
7021 u8 source_eswitch_owner_vhca_id_valid[0x1];
7023 u8 reserved_at_c1[0x1f];
7025 u8 start_flow_index[0x20];
7027 u8 reserved_at_100[0x20];
7029 u8 end_flow_index[0x20];
7031 u8 reserved_at_140[0xa0];
7033 u8 reserved_at_1e0[0x18];
7034 u8 match_criteria_enable[0x8];
7036 struct mlx5_ifc_fte_match_param_bits match_criteria;
7038 u8 reserved_at_1200[0xe00];
7041 struct mlx5_ifc_create_eq_out_bits {
7043 u8 reserved_at_8[0x18];
7047 u8 reserved_at_40[0x18];
7050 u8 reserved_at_60[0x20];
7053 struct mlx5_ifc_create_eq_in_bits {
7055 u8 reserved_at_10[0x10];
7057 u8 reserved_at_20[0x10];
7060 u8 reserved_at_40[0x40];
7062 struct mlx5_ifc_eqc_bits eq_context_entry;
7064 u8 reserved_at_280[0x40];
7066 u8 event_bitmask[0x40];
7068 u8 reserved_at_300[0x580];
7073 struct mlx5_ifc_create_dct_out_bits {
7075 u8 reserved_at_8[0x18];
7079 u8 reserved_at_40[0x8];
7082 u8 reserved_at_60[0x20];
7085 struct mlx5_ifc_create_dct_in_bits {
7087 u8 reserved_at_10[0x10];
7089 u8 reserved_at_20[0x10];
7092 u8 reserved_at_40[0x40];
7094 struct mlx5_ifc_dctc_bits dct_context_entry;
7096 u8 reserved_at_280[0x180];
7099 struct mlx5_ifc_create_cq_out_bits {
7101 u8 reserved_at_8[0x18];
7105 u8 reserved_at_40[0x8];
7108 u8 reserved_at_60[0x20];
7111 struct mlx5_ifc_create_cq_in_bits {
7113 u8 reserved_at_10[0x10];
7115 u8 reserved_at_20[0x10];
7118 u8 reserved_at_40[0x40];
7120 struct mlx5_ifc_cqc_bits cq_context;
7122 u8 reserved_at_280[0x600];
7127 struct mlx5_ifc_config_int_moderation_out_bits {
7129 u8 reserved_at_8[0x18];
7133 u8 reserved_at_40[0x4];
7135 u8 int_vector[0x10];
7137 u8 reserved_at_60[0x20];
7141 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
7142 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
7145 struct mlx5_ifc_config_int_moderation_in_bits {
7147 u8 reserved_at_10[0x10];
7149 u8 reserved_at_20[0x10];
7152 u8 reserved_at_40[0x4];
7154 u8 int_vector[0x10];
7156 u8 reserved_at_60[0x20];
7159 struct mlx5_ifc_attach_to_mcg_out_bits {
7161 u8 reserved_at_8[0x18];
7165 u8 reserved_at_40[0x40];
7168 struct mlx5_ifc_attach_to_mcg_in_bits {
7170 u8 reserved_at_10[0x10];
7172 u8 reserved_at_20[0x10];
7175 u8 reserved_at_40[0x8];
7178 u8 reserved_at_60[0x20];
7180 u8 multicast_gid[16][0x8];
7183 struct mlx5_ifc_arm_xrq_out_bits {
7185 u8 reserved_at_8[0x18];
7189 u8 reserved_at_40[0x40];
7192 struct mlx5_ifc_arm_xrq_in_bits {
7194 u8 reserved_at_10[0x10];
7196 u8 reserved_at_20[0x10];
7199 u8 reserved_at_40[0x8];
7202 u8 reserved_at_60[0x10];
7206 struct mlx5_ifc_arm_xrc_srq_out_bits {
7208 u8 reserved_at_8[0x18];
7212 u8 reserved_at_40[0x40];
7216 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7219 struct mlx5_ifc_arm_xrc_srq_in_bits {
7221 u8 reserved_at_10[0x10];
7223 u8 reserved_at_20[0x10];
7226 u8 reserved_at_40[0x8];
7229 u8 reserved_at_60[0x10];
7233 struct mlx5_ifc_arm_rq_out_bits {
7235 u8 reserved_at_8[0x18];
7239 u8 reserved_at_40[0x40];
7243 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7244 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7247 struct mlx5_ifc_arm_rq_in_bits {
7249 u8 reserved_at_10[0x10];
7251 u8 reserved_at_20[0x10];
7254 u8 reserved_at_40[0x8];
7255 u8 srq_number[0x18];
7257 u8 reserved_at_60[0x10];
7261 struct mlx5_ifc_arm_dct_out_bits {
7263 u8 reserved_at_8[0x18];
7267 u8 reserved_at_40[0x40];
7270 struct mlx5_ifc_arm_dct_in_bits {
7272 u8 reserved_at_10[0x10];
7274 u8 reserved_at_20[0x10];
7277 u8 reserved_at_40[0x8];
7278 u8 dct_number[0x18];
7280 u8 reserved_at_60[0x20];
7283 struct mlx5_ifc_alloc_xrcd_out_bits {
7285 u8 reserved_at_8[0x18];
7289 u8 reserved_at_40[0x8];
7292 u8 reserved_at_60[0x20];
7295 struct mlx5_ifc_alloc_xrcd_in_bits {
7297 u8 reserved_at_10[0x10];
7299 u8 reserved_at_20[0x10];
7302 u8 reserved_at_40[0x40];
7305 struct mlx5_ifc_alloc_uar_out_bits {
7307 u8 reserved_at_8[0x18];
7311 u8 reserved_at_40[0x8];
7314 u8 reserved_at_60[0x20];
7317 struct mlx5_ifc_alloc_uar_in_bits {
7319 u8 reserved_at_10[0x10];
7321 u8 reserved_at_20[0x10];
7324 u8 reserved_at_40[0x40];
7327 struct mlx5_ifc_alloc_transport_domain_out_bits {
7329 u8 reserved_at_8[0x18];
7333 u8 reserved_at_40[0x8];
7334 u8 transport_domain[0x18];
7336 u8 reserved_at_60[0x20];
7339 struct mlx5_ifc_alloc_transport_domain_in_bits {
7341 u8 reserved_at_10[0x10];
7343 u8 reserved_at_20[0x10];
7346 u8 reserved_at_40[0x40];
7349 struct mlx5_ifc_alloc_q_counter_out_bits {
7351 u8 reserved_at_8[0x18];
7355 u8 reserved_at_40[0x18];
7356 u8 counter_set_id[0x8];
7358 u8 reserved_at_60[0x20];
7361 struct mlx5_ifc_alloc_q_counter_in_bits {
7363 u8 reserved_at_10[0x10];
7365 u8 reserved_at_20[0x10];
7368 u8 reserved_at_40[0x40];
7371 struct mlx5_ifc_alloc_pd_out_bits {
7373 u8 reserved_at_8[0x18];
7377 u8 reserved_at_40[0x8];
7380 u8 reserved_at_60[0x20];
7383 struct mlx5_ifc_alloc_pd_in_bits {
7385 u8 reserved_at_10[0x10];
7387 u8 reserved_at_20[0x10];
7390 u8 reserved_at_40[0x40];
7393 struct mlx5_ifc_alloc_flow_counter_out_bits {
7395 u8 reserved_at_8[0x18];
7399 u8 flow_counter_id[0x20];
7401 u8 reserved_at_60[0x20];
7404 struct mlx5_ifc_alloc_flow_counter_in_bits {
7406 u8 reserved_at_10[0x10];
7408 u8 reserved_at_20[0x10];
7411 u8 reserved_at_40[0x40];
7414 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7416 u8 reserved_at_8[0x18];
7420 u8 reserved_at_40[0x40];
7423 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7425 u8 reserved_at_10[0x10];
7427 u8 reserved_at_20[0x10];
7430 u8 reserved_at_40[0x20];
7432 u8 reserved_at_60[0x10];
7433 u8 vxlan_udp_port[0x10];
7436 struct mlx5_ifc_set_pp_rate_limit_out_bits {
7438 u8 reserved_at_8[0x18];
7442 u8 reserved_at_40[0x40];
7445 struct mlx5_ifc_set_pp_rate_limit_in_bits {
7447 u8 reserved_at_10[0x10];
7449 u8 reserved_at_20[0x10];
7452 u8 reserved_at_40[0x10];
7453 u8 rate_limit_index[0x10];
7455 u8 reserved_at_60[0x20];
7457 u8 rate_limit[0x20];
7459 u8 burst_upper_bound[0x20];
7461 u8 reserved_at_c0[0x10];
7462 u8 typical_packet_size[0x10];
7464 u8 reserved_at_e0[0x120];
7467 struct mlx5_ifc_access_register_out_bits {
7469 u8 reserved_at_8[0x18];
7473 u8 reserved_at_40[0x40];
7475 u8 register_data[0][0x20];
7479 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7480 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7483 struct mlx5_ifc_access_register_in_bits {
7485 u8 reserved_at_10[0x10];
7487 u8 reserved_at_20[0x10];
7490 u8 reserved_at_40[0x10];
7491 u8 register_id[0x10];
7495 u8 register_data[0][0x20];
7498 struct mlx5_ifc_sltp_reg_bits {
7503 u8 reserved_at_12[0x2];
7505 u8 reserved_at_18[0x8];
7507 u8 reserved_at_20[0x20];
7509 u8 reserved_at_40[0x7];
7515 u8 reserved_at_60[0xc];
7516 u8 ob_preemp_mode[0x4];
7520 u8 reserved_at_80[0x20];
7523 struct mlx5_ifc_slrg_reg_bits {
7528 u8 reserved_at_12[0x2];
7530 u8 reserved_at_18[0x8];
7532 u8 time_to_link_up[0x10];
7533 u8 reserved_at_30[0xc];
7534 u8 grade_lane_speed[0x4];
7536 u8 grade_version[0x8];
7539 u8 reserved_at_60[0x4];
7540 u8 height_grade_type[0x4];
7541 u8 height_grade[0x18];
7546 u8 reserved_at_a0[0x10];
7547 u8 height_sigma[0x10];
7549 u8 reserved_at_c0[0x20];
7551 u8 reserved_at_e0[0x4];
7552 u8 phase_grade_type[0x4];
7553 u8 phase_grade[0x18];
7555 u8 reserved_at_100[0x8];
7556 u8 phase_eo_pos[0x8];
7557 u8 reserved_at_110[0x8];
7558 u8 phase_eo_neg[0x8];
7560 u8 ffe_set_tested[0x10];
7561 u8 test_errors_per_lane[0x10];
7564 struct mlx5_ifc_pvlc_reg_bits {
7565 u8 reserved_at_0[0x8];
7567 u8 reserved_at_10[0x10];
7569 u8 reserved_at_20[0x1c];
7572 u8 reserved_at_40[0x1c];
7575 u8 reserved_at_60[0x1c];
7576 u8 vl_operational[0x4];
7579 struct mlx5_ifc_pude_reg_bits {
7582 u8 reserved_at_10[0x4];
7583 u8 admin_status[0x4];
7584 u8 reserved_at_18[0x4];
7585 u8 oper_status[0x4];
7587 u8 reserved_at_20[0x60];
7590 struct mlx5_ifc_ptys_reg_bits {
7591 u8 reserved_at_0[0x1];
7592 u8 an_disable_admin[0x1];
7593 u8 an_disable_cap[0x1];
7594 u8 reserved_at_3[0x5];
7596 u8 reserved_at_10[0xd];
7600 u8 reserved_at_24[0x3c];
7602 u8 eth_proto_capability[0x20];
7604 u8 ib_link_width_capability[0x10];
7605 u8 ib_proto_capability[0x10];
7607 u8 reserved_at_a0[0x20];
7609 u8 eth_proto_admin[0x20];
7611 u8 ib_link_width_admin[0x10];
7612 u8 ib_proto_admin[0x10];
7614 u8 reserved_at_100[0x20];
7616 u8 eth_proto_oper[0x20];
7618 u8 ib_link_width_oper[0x10];
7619 u8 ib_proto_oper[0x10];
7621 u8 reserved_at_160[0x1c];
7622 u8 connector_type[0x4];
7624 u8 eth_proto_lp_advertise[0x20];
7626 u8 reserved_at_1a0[0x60];
7629 struct mlx5_ifc_mlcr_reg_bits {
7630 u8 reserved_at_0[0x8];
7632 u8 reserved_at_10[0x20];
7634 u8 beacon_duration[0x10];
7635 u8 reserved_at_40[0x10];
7637 u8 beacon_remain[0x10];
7640 struct mlx5_ifc_ptas_reg_bits {
7641 u8 reserved_at_0[0x20];
7643 u8 algorithm_options[0x10];
7644 u8 reserved_at_30[0x4];
7645 u8 repetitions_mode[0x4];
7646 u8 num_of_repetitions[0x8];
7648 u8 grade_version[0x8];
7649 u8 height_grade_type[0x4];
7650 u8 phase_grade_type[0x4];
7651 u8 height_grade_weight[0x8];
7652 u8 phase_grade_weight[0x8];
7654 u8 gisim_measure_bits[0x10];
7655 u8 adaptive_tap_measure_bits[0x10];
7657 u8 ber_bath_high_error_threshold[0x10];
7658 u8 ber_bath_mid_error_threshold[0x10];
7660 u8 ber_bath_low_error_threshold[0x10];
7661 u8 one_ratio_high_threshold[0x10];
7663 u8 one_ratio_high_mid_threshold[0x10];
7664 u8 one_ratio_low_mid_threshold[0x10];
7666 u8 one_ratio_low_threshold[0x10];
7667 u8 ndeo_error_threshold[0x10];
7669 u8 mixer_offset_step_size[0x10];
7670 u8 reserved_at_110[0x8];
7671 u8 mix90_phase_for_voltage_bath[0x8];
7673 u8 mixer_offset_start[0x10];
7674 u8 mixer_offset_end[0x10];
7676 u8 reserved_at_140[0x15];
7677 u8 ber_test_time[0xb];
7680 struct mlx5_ifc_pspa_reg_bits {
7684 u8 reserved_at_18[0x8];
7686 u8 reserved_at_20[0x20];
7689 struct mlx5_ifc_pqdr_reg_bits {
7690 u8 reserved_at_0[0x8];
7692 u8 reserved_at_10[0x5];
7694 u8 reserved_at_18[0x6];
7697 u8 reserved_at_20[0x20];
7699 u8 reserved_at_40[0x10];
7700 u8 min_threshold[0x10];
7702 u8 reserved_at_60[0x10];
7703 u8 max_threshold[0x10];
7705 u8 reserved_at_80[0x10];
7706 u8 mark_probability_denominator[0x10];
7708 u8 reserved_at_a0[0x60];
7711 struct mlx5_ifc_ppsc_reg_bits {
7712 u8 reserved_at_0[0x8];
7714 u8 reserved_at_10[0x10];
7716 u8 reserved_at_20[0x60];
7718 u8 reserved_at_80[0x1c];
7721 u8 reserved_at_a0[0x1c];
7722 u8 wrps_status[0x4];
7724 u8 reserved_at_c0[0x8];
7725 u8 up_threshold[0x8];
7726 u8 reserved_at_d0[0x8];
7727 u8 down_threshold[0x8];
7729 u8 reserved_at_e0[0x20];
7731 u8 reserved_at_100[0x1c];
7734 u8 reserved_at_120[0x1c];
7735 u8 srps_status[0x4];
7737 u8 reserved_at_140[0x40];
7740 struct mlx5_ifc_pplr_reg_bits {
7741 u8 reserved_at_0[0x8];
7743 u8 reserved_at_10[0x10];
7745 u8 reserved_at_20[0x8];
7747 u8 reserved_at_30[0x8];
7751 struct mlx5_ifc_pplm_reg_bits {
7752 u8 reserved_at_0[0x8];
7754 u8 reserved_at_10[0x10];
7756 u8 reserved_at_20[0x20];
7758 u8 port_profile_mode[0x8];
7759 u8 static_port_profile[0x8];
7760 u8 active_port_profile[0x8];
7761 u8 reserved_at_58[0x8];
7763 u8 retransmission_active[0x8];
7764 u8 fec_mode_active[0x18];
7766 u8 reserved_at_80[0x20];
7769 struct mlx5_ifc_ppcnt_reg_bits {
7773 u8 reserved_at_12[0x8];
7777 u8 reserved_at_21[0x1c];
7780 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7783 struct mlx5_ifc_mpcnt_reg_bits {
7784 u8 reserved_at_0[0x8];
7786 u8 reserved_at_10[0xa];
7790 u8 reserved_at_21[0x1f];
7792 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7795 struct mlx5_ifc_ppad_reg_bits {
7796 u8 reserved_at_0[0x3];
7798 u8 reserved_at_4[0x4];
7804 u8 reserved_at_40[0x40];
7807 struct mlx5_ifc_pmtu_reg_bits {
7808 u8 reserved_at_0[0x8];
7810 u8 reserved_at_10[0x10];
7813 u8 reserved_at_30[0x10];
7816 u8 reserved_at_50[0x10];
7819 u8 reserved_at_70[0x10];
7822 struct mlx5_ifc_pmpr_reg_bits {
7823 u8 reserved_at_0[0x8];
7825 u8 reserved_at_10[0x10];
7827 u8 reserved_at_20[0x18];
7828 u8 attenuation_5g[0x8];
7830 u8 reserved_at_40[0x18];
7831 u8 attenuation_7g[0x8];
7833 u8 reserved_at_60[0x18];
7834 u8 attenuation_12g[0x8];
7837 struct mlx5_ifc_pmpe_reg_bits {
7838 u8 reserved_at_0[0x8];
7840 u8 reserved_at_10[0xc];
7841 u8 module_status[0x4];
7843 u8 reserved_at_20[0x60];
7846 struct mlx5_ifc_pmpc_reg_bits {
7847 u8 module_state_updated[32][0x8];
7850 struct mlx5_ifc_pmlpn_reg_bits {
7851 u8 reserved_at_0[0x4];
7852 u8 mlpn_status[0x4];
7854 u8 reserved_at_10[0x10];
7857 u8 reserved_at_21[0x1f];
7860 struct mlx5_ifc_pmlp_reg_bits {
7862 u8 reserved_at_1[0x7];
7864 u8 reserved_at_10[0x8];
7867 u8 lane0_module_mapping[0x20];
7869 u8 lane1_module_mapping[0x20];
7871 u8 lane2_module_mapping[0x20];
7873 u8 lane3_module_mapping[0x20];
7875 u8 reserved_at_a0[0x160];
7878 struct mlx5_ifc_pmaos_reg_bits {
7879 u8 reserved_at_0[0x8];
7881 u8 reserved_at_10[0x4];
7882 u8 admin_status[0x4];
7883 u8 reserved_at_18[0x4];
7884 u8 oper_status[0x4];
7888 u8 reserved_at_22[0x1c];
7891 u8 reserved_at_40[0x40];
7894 struct mlx5_ifc_plpc_reg_bits {
7895 u8 reserved_at_0[0x4];
7897 u8 reserved_at_10[0x4];
7899 u8 reserved_at_18[0x8];
7901 u8 reserved_at_20[0x10];
7902 u8 lane_speed[0x10];
7904 u8 reserved_at_40[0x17];
7906 u8 fec_mode_policy[0x8];
7908 u8 retransmission_capability[0x8];
7909 u8 fec_mode_capability[0x18];
7911 u8 retransmission_support_admin[0x8];
7912 u8 fec_mode_support_admin[0x18];
7914 u8 retransmission_request_admin[0x8];
7915 u8 fec_mode_request_admin[0x18];
7917 u8 reserved_at_c0[0x80];
7920 struct mlx5_ifc_plib_reg_bits {
7921 u8 reserved_at_0[0x8];
7923 u8 reserved_at_10[0x8];
7926 u8 reserved_at_20[0x60];
7929 struct mlx5_ifc_plbf_reg_bits {
7930 u8 reserved_at_0[0x8];
7932 u8 reserved_at_10[0xd];
7935 u8 reserved_at_20[0x20];
7938 struct mlx5_ifc_pipg_reg_bits {
7939 u8 reserved_at_0[0x8];
7941 u8 reserved_at_10[0x10];
7944 u8 reserved_at_21[0x19];
7946 u8 reserved_at_3e[0x2];
7949 struct mlx5_ifc_pifr_reg_bits {
7950 u8 reserved_at_0[0x8];
7952 u8 reserved_at_10[0x10];
7954 u8 reserved_at_20[0xe0];
7956 u8 port_filter[8][0x20];
7958 u8 port_filter_update_en[8][0x20];
7961 struct mlx5_ifc_pfcc_reg_bits {
7962 u8 reserved_at_0[0x8];
7964 u8 reserved_at_10[0xb];
7965 u8 ppan_mask_n[0x1];
7966 u8 minor_stall_mask[0x1];
7967 u8 critical_stall_mask[0x1];
7968 u8 reserved_at_1e[0x2];
7971 u8 reserved_at_24[0x4];
7972 u8 prio_mask_tx[0x8];
7973 u8 reserved_at_30[0x8];
7974 u8 prio_mask_rx[0x8];
7978 u8 pptx_mask_n[0x1];
7979 u8 reserved_at_43[0x5];
7981 u8 reserved_at_50[0x10];
7985 u8 pprx_mask_n[0x1];
7986 u8 reserved_at_63[0x5];
7988 u8 reserved_at_70[0x10];
7990 u8 device_stall_minor_watermark[0x10];
7991 u8 device_stall_critical_watermark[0x10];
7993 u8 reserved_at_a0[0x60];
7996 struct mlx5_ifc_pelc_reg_bits {
7998 u8 reserved_at_4[0x4];
8000 u8 reserved_at_10[0x10];
8003 u8 op_capability[0x8];
8009 u8 capability[0x40];
8015 u8 reserved_at_140[0x80];
8018 struct mlx5_ifc_peir_reg_bits {
8019 u8 reserved_at_0[0x8];
8021 u8 reserved_at_10[0x10];
8023 u8 reserved_at_20[0xc];
8024 u8 error_count[0x4];
8025 u8 reserved_at_30[0x10];
8027 u8 reserved_at_40[0xc];
8029 u8 reserved_at_50[0x8];
8033 struct mlx5_ifc_pcam_enhanced_features_bits {
8034 u8 reserved_at_0[0x76];
8037 u8 reserved_at_77[0x4];
8038 u8 rx_buffer_fullness_counters[0x1];
8039 u8 ptys_connector_type[0x1];
8040 u8 reserved_at_7d[0x1];
8041 u8 ppcnt_discard_group[0x1];
8042 u8 ppcnt_statistical_group[0x1];
8045 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8046 u8 port_access_reg_cap_mask_127_to_96[0x20];
8047 u8 port_access_reg_cap_mask_95_to_64[0x20];
8048 u8 port_access_reg_cap_mask_63_to_32[0x20];
8050 u8 port_access_reg_cap_mask_31_to_13[0x13];
8053 u8 port_access_reg_cap_mask_10_to_0[0xb];
8056 struct mlx5_ifc_pcam_reg_bits {
8057 u8 reserved_at_0[0x8];
8058 u8 feature_group[0x8];
8059 u8 reserved_at_10[0x8];
8060 u8 access_reg_group[0x8];
8062 u8 reserved_at_20[0x20];
8065 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8066 u8 reserved_at_0[0x80];
8067 } port_access_reg_cap_mask;
8069 u8 reserved_at_c0[0x80];
8072 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8073 u8 reserved_at_0[0x80];
8076 u8 reserved_at_1c0[0xc0];
8079 struct mlx5_ifc_mcam_enhanced_features_bits {
8080 u8 reserved_at_0[0x7b];
8081 u8 pcie_outbound_stalled[0x1];
8082 u8 tx_overflow_buffer_pkt[0x1];
8083 u8 mtpps_enh_out_per_adj[0x1];
8085 u8 pcie_performance_group[0x1];
8088 struct mlx5_ifc_mcam_access_reg_bits {
8089 u8 reserved_at_0[0x1c];
8093 u8 reserved_at_1f[0x1];
8095 u8 regs_95_to_64[0x20];
8096 u8 regs_63_to_32[0x20];
8097 u8 regs_31_to_0[0x20];
8100 struct mlx5_ifc_mcam_reg_bits {
8101 u8 reserved_at_0[0x8];
8102 u8 feature_group[0x8];
8103 u8 reserved_at_10[0x8];
8104 u8 access_reg_group[0x8];
8106 u8 reserved_at_20[0x20];
8109 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8110 u8 reserved_at_0[0x80];
8111 } mng_access_reg_cap_mask;
8113 u8 reserved_at_c0[0x80];
8116 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8117 u8 reserved_at_0[0x80];
8118 } mng_feature_cap_mask;
8120 u8 reserved_at_1c0[0x80];
8123 struct mlx5_ifc_qcam_access_reg_cap_mask {
8124 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
8126 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
8130 u8 qcam_access_reg_cap_mask_0[0x1];
8133 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8134 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
8135 u8 qpts_trust_both[0x1];
8138 struct mlx5_ifc_qcam_reg_bits {
8139 u8 reserved_at_0[0x8];
8140 u8 feature_group[0x8];
8141 u8 reserved_at_10[0x8];
8142 u8 access_reg_group[0x8];
8143 u8 reserved_at_20[0x20];
8146 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8147 u8 reserved_at_0[0x80];
8148 } qos_access_reg_cap_mask;
8150 u8 reserved_at_c0[0x80];
8153 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8154 u8 reserved_at_0[0x80];
8155 } qos_feature_cap_mask;
8157 u8 reserved_at_1c0[0x80];
8160 struct mlx5_ifc_pcap_reg_bits {
8161 u8 reserved_at_0[0x8];
8163 u8 reserved_at_10[0x10];
8165 u8 port_capability_mask[4][0x20];
8168 struct mlx5_ifc_paos_reg_bits {
8171 u8 reserved_at_10[0x4];
8172 u8 admin_status[0x4];
8173 u8 reserved_at_18[0x4];
8174 u8 oper_status[0x4];
8178 u8 reserved_at_22[0x1c];
8181 u8 reserved_at_40[0x40];
8184 struct mlx5_ifc_pamp_reg_bits {
8185 u8 reserved_at_0[0x8];
8186 u8 opamp_group[0x8];
8187 u8 reserved_at_10[0xc];
8188 u8 opamp_group_type[0x4];
8190 u8 start_index[0x10];
8191 u8 reserved_at_30[0x4];
8192 u8 num_of_indices[0xc];
8194 u8 index_data[18][0x10];
8197 struct mlx5_ifc_pcmr_reg_bits {
8198 u8 reserved_at_0[0x8];
8200 u8 reserved_at_10[0x2e];
8202 u8 reserved_at_3f[0x1f];
8204 u8 reserved_at_5f[0x1];
8207 struct mlx5_ifc_lane_2_module_mapping_bits {
8208 u8 reserved_at_0[0x6];
8210 u8 reserved_at_8[0x6];
8212 u8 reserved_at_10[0x8];
8216 struct mlx5_ifc_bufferx_reg_bits {
8217 u8 reserved_at_0[0x6];
8220 u8 reserved_at_8[0xc];
8223 u8 xoff_threshold[0x10];
8224 u8 xon_threshold[0x10];
8227 struct mlx5_ifc_set_node_in_bits {
8228 u8 node_description[64][0x8];
8231 struct mlx5_ifc_register_power_settings_bits {
8232 u8 reserved_at_0[0x18];
8233 u8 power_settings_level[0x8];
8235 u8 reserved_at_20[0x60];
8238 struct mlx5_ifc_register_host_endianness_bits {
8240 u8 reserved_at_1[0x1f];
8242 u8 reserved_at_20[0x60];
8245 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8246 u8 reserved_at_0[0x20];
8250 u8 addressh_63_32[0x20];
8252 u8 addressl_31_0[0x20];
8255 struct mlx5_ifc_ud_adrs_vector_bits {
8259 u8 reserved_at_41[0x7];
8260 u8 destination_qp_dct[0x18];
8262 u8 static_rate[0x4];
8263 u8 sl_eth_prio[0x4];
8266 u8 rlid_udp_sport[0x10];
8268 u8 reserved_at_80[0x20];
8270 u8 rmac_47_16[0x20];
8276 u8 reserved_at_e0[0x1];
8278 u8 reserved_at_e2[0x2];
8279 u8 src_addr_index[0x8];
8280 u8 flow_label[0x14];
8282 u8 rgid_rip[16][0x8];
8285 struct mlx5_ifc_pages_req_event_bits {
8286 u8 reserved_at_0[0x10];
8287 u8 function_id[0x10];
8291 u8 reserved_at_40[0xa0];
8294 struct mlx5_ifc_eqe_bits {
8295 u8 reserved_at_0[0x8];
8297 u8 reserved_at_10[0x8];
8298 u8 event_sub_type[0x8];
8300 u8 reserved_at_20[0xe0];
8302 union mlx5_ifc_event_auto_bits event_data;
8304 u8 reserved_at_1e0[0x10];
8306 u8 reserved_at_1f8[0x7];
8311 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
8314 struct mlx5_ifc_cmd_queue_entry_bits {
8316 u8 reserved_at_8[0x18];
8318 u8 input_length[0x20];
8320 u8 input_mailbox_pointer_63_32[0x20];
8322 u8 input_mailbox_pointer_31_9[0x17];
8323 u8 reserved_at_77[0x9];
8325 u8 command_input_inline_data[16][0x8];
8327 u8 command_output_inline_data[16][0x8];
8329 u8 output_mailbox_pointer_63_32[0x20];
8331 u8 output_mailbox_pointer_31_9[0x17];
8332 u8 reserved_at_1b7[0x9];
8334 u8 output_length[0x20];
8338 u8 reserved_at_1f0[0x8];
8343 struct mlx5_ifc_cmd_out_bits {
8345 u8 reserved_at_8[0x18];
8349 u8 command_output[0x20];
8352 struct mlx5_ifc_cmd_in_bits {
8354 u8 reserved_at_10[0x10];
8356 u8 reserved_at_20[0x10];
8359 u8 command[0][0x20];
8362 struct mlx5_ifc_cmd_if_box_bits {
8363 u8 mailbox_data[512][0x8];
8365 u8 reserved_at_1000[0x180];
8367 u8 next_pointer_63_32[0x20];
8369 u8 next_pointer_31_10[0x16];
8370 u8 reserved_at_11b6[0xa];
8372 u8 block_number[0x20];
8374 u8 reserved_at_11e0[0x8];
8376 u8 ctrl_signature[0x8];
8380 struct mlx5_ifc_mtt_bits {
8381 u8 ptag_63_32[0x20];
8384 u8 reserved_at_38[0x6];
8389 struct mlx5_ifc_query_wol_rol_out_bits {
8391 u8 reserved_at_8[0x18];
8395 u8 reserved_at_40[0x10];
8399 u8 reserved_at_60[0x20];
8402 struct mlx5_ifc_query_wol_rol_in_bits {
8404 u8 reserved_at_10[0x10];
8406 u8 reserved_at_20[0x10];
8409 u8 reserved_at_40[0x40];
8412 struct mlx5_ifc_set_wol_rol_out_bits {
8414 u8 reserved_at_8[0x18];
8418 u8 reserved_at_40[0x40];
8421 struct mlx5_ifc_set_wol_rol_in_bits {
8423 u8 reserved_at_10[0x10];
8425 u8 reserved_at_20[0x10];
8428 u8 rol_mode_valid[0x1];
8429 u8 wol_mode_valid[0x1];
8430 u8 reserved_at_42[0xe];
8434 u8 reserved_at_60[0x20];
8438 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8439 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8440 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8444 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8445 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8446 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8450 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8451 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8452 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8453 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8454 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8455 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8456 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8457 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8458 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8459 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8460 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8463 struct mlx5_ifc_initial_seg_bits {
8464 u8 fw_rev_minor[0x10];
8465 u8 fw_rev_major[0x10];
8467 u8 cmd_interface_rev[0x10];
8468 u8 fw_rev_subminor[0x10];
8470 u8 reserved_at_40[0x40];
8472 u8 cmdq_phy_addr_63_32[0x20];
8474 u8 cmdq_phy_addr_31_12[0x14];
8475 u8 reserved_at_b4[0x2];
8476 u8 nic_interface[0x2];
8477 u8 log_cmdq_size[0x4];
8478 u8 log_cmdq_stride[0x4];
8480 u8 command_doorbell_vector[0x20];
8482 u8 reserved_at_e0[0xf00];
8484 u8 initializing[0x1];
8485 u8 reserved_at_fe1[0x4];
8486 u8 nic_interface_supported[0x3];
8487 u8 reserved_at_fe8[0x18];
8489 struct mlx5_ifc_health_buffer_bits health_buffer;
8491 u8 no_dram_nic_offset[0x20];
8493 u8 reserved_at_1220[0x6e40];
8495 u8 reserved_at_8060[0x1f];
8498 u8 health_syndrome[0x8];
8499 u8 health_counter[0x18];
8501 u8 reserved_at_80a0[0x17fc0];
8504 struct mlx5_ifc_mtpps_reg_bits {
8505 u8 reserved_at_0[0xc];
8506 u8 cap_number_of_pps_pins[0x4];
8507 u8 reserved_at_10[0x4];
8508 u8 cap_max_num_of_pps_in_pins[0x4];
8509 u8 reserved_at_18[0x4];
8510 u8 cap_max_num_of_pps_out_pins[0x4];
8512 u8 reserved_at_20[0x24];
8513 u8 cap_pin_3_mode[0x4];
8514 u8 reserved_at_48[0x4];
8515 u8 cap_pin_2_mode[0x4];
8516 u8 reserved_at_50[0x4];
8517 u8 cap_pin_1_mode[0x4];
8518 u8 reserved_at_58[0x4];
8519 u8 cap_pin_0_mode[0x4];
8521 u8 reserved_at_60[0x4];
8522 u8 cap_pin_7_mode[0x4];
8523 u8 reserved_at_68[0x4];
8524 u8 cap_pin_6_mode[0x4];
8525 u8 reserved_at_70[0x4];
8526 u8 cap_pin_5_mode[0x4];
8527 u8 reserved_at_78[0x4];
8528 u8 cap_pin_4_mode[0x4];
8530 u8 field_select[0x20];
8531 u8 reserved_at_a0[0x60];
8534 u8 reserved_at_101[0xb];
8536 u8 reserved_at_110[0x4];
8540 u8 reserved_at_120[0x20];
8542 u8 time_stamp[0x40];
8544 u8 out_pulse_duration[0x10];
8545 u8 out_periodic_adjustment[0x10];
8546 u8 enhanced_out_periodic_adjustment[0x20];
8548 u8 reserved_at_1c0[0x20];
8551 struct mlx5_ifc_mtppse_reg_bits {
8552 u8 reserved_at_0[0x18];
8555 u8 reserved_at_21[0x1b];
8556 u8 event_generation_mode[0x4];
8557 u8 reserved_at_40[0x40];
8560 struct mlx5_ifc_mcqi_cap_bits {
8561 u8 supported_info_bitmask[0x20];
8563 u8 component_size[0x20];
8565 u8 max_component_size[0x20];
8567 u8 log_mcda_word_size[0x4];
8568 u8 reserved_at_64[0xc];
8569 u8 mcda_max_write_size[0x10];
8572 u8 reserved_at_81[0x1];
8573 u8 match_chip_id[0x1];
8575 u8 check_user_timestamp[0x1];
8576 u8 match_base_guid_mac[0x1];
8577 u8 reserved_at_86[0x1a];
8580 struct mlx5_ifc_mcqi_reg_bits {
8581 u8 read_pending_component[0x1];
8582 u8 reserved_at_1[0xf];
8583 u8 component_index[0x10];
8585 u8 reserved_at_20[0x20];
8587 u8 reserved_at_40[0x1b];
8594 u8 reserved_at_a0[0x10];
8600 struct mlx5_ifc_mcc_reg_bits {
8601 u8 reserved_at_0[0x4];
8602 u8 time_elapsed_since_last_cmd[0xc];
8603 u8 reserved_at_10[0x8];
8604 u8 instruction[0x8];
8606 u8 reserved_at_20[0x10];
8607 u8 component_index[0x10];
8609 u8 reserved_at_40[0x8];
8610 u8 update_handle[0x18];
8612 u8 handle_owner_type[0x4];
8613 u8 handle_owner_host_id[0x4];
8614 u8 reserved_at_68[0x1];
8615 u8 control_progress[0x7];
8617 u8 reserved_at_78[0x4];
8618 u8 control_state[0x4];
8620 u8 component_size[0x20];
8622 u8 reserved_at_a0[0x60];
8625 struct mlx5_ifc_mcda_reg_bits {
8626 u8 reserved_at_0[0x8];
8627 u8 update_handle[0x18];
8631 u8 reserved_at_40[0x10];
8634 u8 reserved_at_60[0x20];
8639 union mlx5_ifc_ports_control_registers_document_bits {
8640 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8641 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8642 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8643 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8644 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8645 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8646 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8647 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8648 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8649 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8650 struct mlx5_ifc_paos_reg_bits paos_reg;
8651 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8652 struct mlx5_ifc_peir_reg_bits peir_reg;
8653 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8654 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8655 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8656 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8657 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8658 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8659 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8660 struct mlx5_ifc_plib_reg_bits plib_reg;
8661 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8662 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8663 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8664 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8665 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8666 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8667 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8668 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8669 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8670 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8671 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8672 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8673 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8674 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8675 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8676 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8677 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8678 struct mlx5_ifc_ptys_reg_bits ptys_reg;
8679 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8680 struct mlx5_ifc_pude_reg_bits pude_reg;
8681 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8682 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8683 struct mlx5_ifc_sltp_reg_bits sltp_reg;
8684 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8685 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8686 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
8687 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8688 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8689 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8690 struct mlx5_ifc_mcc_reg_bits mcc_reg;
8691 struct mlx5_ifc_mcda_reg_bits mcda_reg;
8692 u8 reserved_at_0[0x60e0];
8695 union mlx5_ifc_debug_enhancements_document_bits {
8696 struct mlx5_ifc_health_buffer_bits health_buffer;
8697 u8 reserved_at_0[0x200];
8700 union mlx5_ifc_uplink_pci_interface_document_bits {
8701 struct mlx5_ifc_initial_seg_bits initial_seg;
8702 u8 reserved_at_0[0x20060];
8705 struct mlx5_ifc_set_flow_table_root_out_bits {
8707 u8 reserved_at_8[0x18];
8711 u8 reserved_at_40[0x40];
8714 struct mlx5_ifc_set_flow_table_root_in_bits {
8716 u8 reserved_at_10[0x10];
8718 u8 reserved_at_20[0x10];
8721 u8 other_vport[0x1];
8722 u8 reserved_at_41[0xf];
8723 u8 vport_number[0x10];
8725 u8 reserved_at_60[0x20];
8728 u8 reserved_at_88[0x18];
8730 u8 reserved_at_a0[0x8];
8733 u8 reserved_at_c0[0x8];
8734 u8 underlay_qpn[0x18];
8735 u8 reserved_at_e0[0x120];
8739 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8740 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8743 struct mlx5_ifc_modify_flow_table_out_bits {
8745 u8 reserved_at_8[0x18];
8749 u8 reserved_at_40[0x40];
8752 struct mlx5_ifc_modify_flow_table_in_bits {
8754 u8 reserved_at_10[0x10];
8756 u8 reserved_at_20[0x10];
8759 u8 other_vport[0x1];
8760 u8 reserved_at_41[0xf];
8761 u8 vport_number[0x10];
8763 u8 reserved_at_60[0x10];
8764 u8 modify_field_select[0x10];
8767 u8 reserved_at_88[0x18];
8769 u8 reserved_at_a0[0x8];
8772 struct mlx5_ifc_flow_table_context_bits flow_table_context;
8775 struct mlx5_ifc_ets_tcn_config_reg_bits {
8779 u8 reserved_at_3[0x9];
8781 u8 reserved_at_10[0x9];
8782 u8 bw_allocation[0x7];
8784 u8 reserved_at_20[0xc];
8785 u8 max_bw_units[0x4];
8786 u8 reserved_at_30[0x8];
8787 u8 max_bw_value[0x8];
8790 struct mlx5_ifc_ets_global_config_reg_bits {
8791 u8 reserved_at_0[0x2];
8793 u8 reserved_at_3[0x1d];
8795 u8 reserved_at_20[0xc];
8796 u8 max_bw_units[0x4];
8797 u8 reserved_at_30[0x8];
8798 u8 max_bw_value[0x8];
8801 struct mlx5_ifc_qetc_reg_bits {
8802 u8 reserved_at_0[0x8];
8803 u8 port_number[0x8];
8804 u8 reserved_at_10[0x30];
8806 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8807 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8810 struct mlx5_ifc_qpdpm_dscp_reg_bits {
8812 u8 reserved_at_01[0x0b];
8816 struct mlx5_ifc_qpdpm_reg_bits {
8817 u8 reserved_at_0[0x8];
8819 u8 reserved_at_10[0x10];
8820 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
8823 struct mlx5_ifc_qpts_reg_bits {
8824 u8 reserved_at_0[0x8];
8826 u8 reserved_at_10[0x2d];
8827 u8 trust_state[0x3];
8830 struct mlx5_ifc_pptb_reg_bits {
8831 u8 reserved_at_0[0x2];
8833 u8 reserved_at_4[0x4];
8835 u8 reserved_at_10[0x6];
8840 u8 prio_x_buff[0x20];
8843 u8 reserved_at_48[0x10];
8845 u8 untagged_buff[0x4];
8848 struct mlx5_ifc_pbmc_reg_bits {
8849 u8 reserved_at_0[0x8];
8851 u8 reserved_at_10[0x10];
8853 u8 xoff_timer_value[0x10];
8854 u8 xoff_refresh[0x10];
8856 u8 reserved_at_40[0x9];
8857 u8 fullness_threshold[0x7];
8858 u8 port_buffer_size[0x10];
8860 struct mlx5_ifc_bufferx_reg_bits buffer[10];
8862 u8 reserved_at_2e0[0x40];
8865 struct mlx5_ifc_qtct_reg_bits {
8866 u8 reserved_at_0[0x8];
8867 u8 port_number[0x8];
8868 u8 reserved_at_10[0xd];
8871 u8 reserved_at_20[0x1d];
8875 struct mlx5_ifc_mcia_reg_bits {
8877 u8 reserved_at_1[0x7];
8879 u8 reserved_at_10[0x8];
8882 u8 i2c_device_address[0x8];
8883 u8 page_number[0x8];
8884 u8 device_address[0x10];
8886 u8 reserved_at_40[0x10];
8889 u8 reserved_at_60[0x20];
8905 struct mlx5_ifc_dcbx_param_bits {
8906 u8 dcbx_cee_cap[0x1];
8907 u8 dcbx_ieee_cap[0x1];
8908 u8 dcbx_standby_cap[0x1];
8909 u8 reserved_at_0[0x5];
8910 u8 port_number[0x8];
8911 u8 reserved_at_10[0xa];
8912 u8 max_application_table_size[6];
8913 u8 reserved_at_20[0x15];
8914 u8 version_oper[0x3];
8915 u8 reserved_at_38[5];
8916 u8 version_admin[0x3];
8917 u8 willing_admin[0x1];
8918 u8 reserved_at_41[0x3];
8919 u8 pfc_cap_oper[0x4];
8920 u8 reserved_at_48[0x4];
8921 u8 pfc_cap_admin[0x4];
8922 u8 reserved_at_50[0x4];
8923 u8 num_of_tc_oper[0x4];
8924 u8 reserved_at_58[0x4];
8925 u8 num_of_tc_admin[0x4];
8926 u8 remote_willing[0x1];
8927 u8 reserved_at_61[3];
8928 u8 remote_pfc_cap[4];
8929 u8 reserved_at_68[0x14];
8930 u8 remote_num_of_tc[0x4];
8931 u8 reserved_at_80[0x18];
8933 u8 reserved_at_a0[0x160];
8936 struct mlx5_ifc_lagc_bits {
8937 u8 reserved_at_0[0x1d];
8940 u8 reserved_at_20[0x14];
8941 u8 tx_remap_affinity_2[0x4];
8942 u8 reserved_at_38[0x4];
8943 u8 tx_remap_affinity_1[0x4];
8946 struct mlx5_ifc_create_lag_out_bits {
8948 u8 reserved_at_8[0x18];
8952 u8 reserved_at_40[0x40];
8955 struct mlx5_ifc_create_lag_in_bits {
8957 u8 reserved_at_10[0x10];
8959 u8 reserved_at_20[0x10];
8962 struct mlx5_ifc_lagc_bits ctx;
8965 struct mlx5_ifc_modify_lag_out_bits {
8967 u8 reserved_at_8[0x18];
8971 u8 reserved_at_40[0x40];
8974 struct mlx5_ifc_modify_lag_in_bits {
8976 u8 reserved_at_10[0x10];
8978 u8 reserved_at_20[0x10];
8981 u8 reserved_at_40[0x20];
8982 u8 field_select[0x20];
8984 struct mlx5_ifc_lagc_bits ctx;
8987 struct mlx5_ifc_query_lag_out_bits {
8989 u8 reserved_at_8[0x18];
8993 u8 reserved_at_40[0x40];
8995 struct mlx5_ifc_lagc_bits ctx;
8998 struct mlx5_ifc_query_lag_in_bits {
9000 u8 reserved_at_10[0x10];
9002 u8 reserved_at_20[0x10];
9005 u8 reserved_at_40[0x40];
9008 struct mlx5_ifc_destroy_lag_out_bits {
9010 u8 reserved_at_8[0x18];
9014 u8 reserved_at_40[0x40];
9017 struct mlx5_ifc_destroy_lag_in_bits {
9019 u8 reserved_at_10[0x10];
9021 u8 reserved_at_20[0x10];
9024 u8 reserved_at_40[0x40];
9027 struct mlx5_ifc_create_vport_lag_out_bits {
9029 u8 reserved_at_8[0x18];
9033 u8 reserved_at_40[0x40];
9036 struct mlx5_ifc_create_vport_lag_in_bits {
9038 u8 reserved_at_10[0x10];
9040 u8 reserved_at_20[0x10];
9043 u8 reserved_at_40[0x40];
9046 struct mlx5_ifc_destroy_vport_lag_out_bits {
9048 u8 reserved_at_8[0x18];
9052 u8 reserved_at_40[0x40];
9055 struct mlx5_ifc_destroy_vport_lag_in_bits {
9057 u8 reserved_at_10[0x10];
9059 u8 reserved_at_20[0x10];
9062 u8 reserved_at_40[0x40];
9065 struct mlx5_ifc_alloc_memic_in_bits {
9067 u8 reserved_at_10[0x10];
9069 u8 reserved_at_20[0x10];
9072 u8 reserved_at_30[0x20];
9074 u8 reserved_at_40[0x18];
9075 u8 log_memic_addr_alignment[0x8];
9077 u8 range_start_addr[0x40];
9079 u8 range_size[0x20];
9081 u8 memic_size[0x20];
9084 struct mlx5_ifc_alloc_memic_out_bits {
9086 u8 reserved_at_8[0x18];
9090 u8 memic_start_addr[0x40];
9093 struct mlx5_ifc_dealloc_memic_in_bits {
9095 u8 reserved_at_10[0x10];
9097 u8 reserved_at_20[0x10];
9100 u8 reserved_at_40[0x40];
9102 u8 memic_start_addr[0x40];
9104 u8 memic_size[0x20];
9106 u8 reserved_at_e0[0x20];
9109 struct mlx5_ifc_dealloc_memic_out_bits {
9111 u8 reserved_at_8[0x18];
9115 u8 reserved_at_40[0x40];
9118 #endif /* MLX5_IFC_H */