1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Xilinx Zynq MPSoC Firmware layer
5 * Copyright (C) 2014-2019 Xilinx
7 * Michal Simek <michal.simek@xilinx.com>
8 * Davorin Mista <davorin.mista@aggios.com>
9 * Jolly Shah <jollys@xilinx.com>
10 * Rajan Vaja <rajanv@xilinx.com>
13 #ifndef __FIRMWARE_ZYNQMP_H__
14 #define __FIRMWARE_ZYNQMP_H__
16 #include <linux/err.h>
18 #define ZYNQMP_PM_VERSION_MAJOR 1
19 #define ZYNQMP_PM_VERSION_MINOR 0
21 #define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
22 ZYNQMP_PM_VERSION_MINOR)
24 #define ZYNQMP_TZ_VERSION_MAJOR 1
25 #define ZYNQMP_TZ_VERSION_MINOR 0
27 #define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
28 ZYNQMP_TZ_VERSION_MINOR)
30 /* SMC SIP service Call Function Identifier Prefix */
31 #define PM_SIP_SVC 0xC2000000
32 #define PM_GET_TRUSTZONE_VERSION 0xa03
33 #define PM_SET_SUSPEND_MODE 0xa02
34 #define GET_CALLBACK_DATA 0xa01
36 /* Number of 32bits values in payload */
37 #define PAYLOAD_ARG_CNT 4U
39 /* Number of arguments for a callback */
42 /* Payload size (consists of callback API ID + arguments) */
43 #define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
45 #define ZYNQMP_PM_MAX_QOS 100U
47 #define GSS_NUM_REGS (4)
49 /* Node capabilities */
50 #define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
51 #define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
52 #define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
53 #define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
56 * Firmware FPGA Manager flags
57 * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration
58 * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
60 #define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U
61 #define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)
64 PM_GET_API_VERSION = 1,
65 PM_SYSTEM_SHUTDOWN = 12,
68 PM_SET_REQUIREMENT = 15,
70 PM_RESET_GET_STATUS = 18,
71 PM_PM_INIT_FINALIZE = 21,
73 PM_FPGA_GET_STATUS = 23,
78 PM_CLOCK_DISABLE = 37,
79 PM_CLOCK_GETSTATE = 38,
80 PM_CLOCK_SETDIVIDER = 39,
81 PM_CLOCK_GETDIVIDER = 40,
82 PM_CLOCK_SETRATE = 41,
83 PM_CLOCK_GETRATE = 42,
84 PM_CLOCK_SETPARENT = 43,
85 PM_CLOCK_GETPARENT = 44,
87 PM_FEATURE_CHECK = 63,
90 /* PMU-FW return status codes */
93 XST_PM_NO_FEATURE = 19,
94 XST_PM_INTERNAL = 2000,
95 XST_PM_CONFLICT = 2001,
96 XST_PM_NO_ACCESS = 2002,
97 XST_PM_INVALID_NODE = 2003,
98 XST_PM_DOUBLE_REQ = 2004,
99 XST_PM_ABORT_SUSPEND = 2005,
100 XST_PM_MULT_USER = 2008,
104 IOCTL_SD_DLL_RESET = 6,
105 IOCTL_SET_SD_TAPDELAY = 7,
106 IOCTL_SET_PLL_FRAC_MODE = 8,
107 IOCTL_GET_PLL_FRAC_MODE = 9,
108 IOCTL_SET_PLL_FRAC_DATA = 10,
109 IOCTL_GET_PLL_FRAC_DATA = 11,
110 IOCTL_WRITE_GGS = 12,
112 IOCTL_WRITE_PGGS = 14,
113 IOCTL_READ_PGGS = 15,
114 /* Set healthy bit value */
115 IOCTL_SET_BOOT_HEALTH_STATUS = 17,
120 PM_QID_CLOCK_GET_NAME = 1,
121 PM_QID_CLOCK_GET_TOPOLOGY = 2,
122 PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,
123 PM_QID_CLOCK_GET_PARENTS = 4,
124 PM_QID_CLOCK_GET_ATTRIBUTES = 5,
125 PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
126 PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
129 enum zynqmp_pm_reset_action {
130 PM_RESET_ACTION_RELEASE = 0,
131 PM_RESET_ACTION_ASSERT = 1,
132 PM_RESET_ACTION_PULSE = 2,
135 enum zynqmp_pm_reset {
136 ZYNQMP_PM_RESET_START = 1000,
137 ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
138 ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001,
139 ZYNQMP_PM_RESET_PCIE_CTRL = 1002,
140 ZYNQMP_PM_RESET_DP = 1003,
141 ZYNQMP_PM_RESET_SWDT_CRF = 1004,
142 ZYNQMP_PM_RESET_AFI_FM5 = 1005,
143 ZYNQMP_PM_RESET_AFI_FM4 = 1006,
144 ZYNQMP_PM_RESET_AFI_FM3 = 1007,
145 ZYNQMP_PM_RESET_AFI_FM2 = 1008,
146 ZYNQMP_PM_RESET_AFI_FM1 = 1009,
147 ZYNQMP_PM_RESET_AFI_FM0 = 1010,
148 ZYNQMP_PM_RESET_GDMA = 1011,
149 ZYNQMP_PM_RESET_GPU_PP1 = 1012,
150 ZYNQMP_PM_RESET_GPU_PP0 = 1013,
151 ZYNQMP_PM_RESET_GPU = 1014,
152 ZYNQMP_PM_RESET_GT = 1015,
153 ZYNQMP_PM_RESET_SATA = 1016,
154 ZYNQMP_PM_RESET_ACPU3_PWRON = 1017,
155 ZYNQMP_PM_RESET_ACPU2_PWRON = 1018,
156 ZYNQMP_PM_RESET_ACPU1_PWRON = 1019,
157 ZYNQMP_PM_RESET_ACPU0_PWRON = 1020,
158 ZYNQMP_PM_RESET_APU_L2 = 1021,
159 ZYNQMP_PM_RESET_ACPU3 = 1022,
160 ZYNQMP_PM_RESET_ACPU2 = 1023,
161 ZYNQMP_PM_RESET_ACPU1 = 1024,
162 ZYNQMP_PM_RESET_ACPU0 = 1025,
163 ZYNQMP_PM_RESET_DDR = 1026,
164 ZYNQMP_PM_RESET_APM_FPD = 1027,
165 ZYNQMP_PM_RESET_SOFT = 1028,
166 ZYNQMP_PM_RESET_GEM0 = 1029,
167 ZYNQMP_PM_RESET_GEM1 = 1030,
168 ZYNQMP_PM_RESET_GEM2 = 1031,
169 ZYNQMP_PM_RESET_GEM3 = 1032,
170 ZYNQMP_PM_RESET_QSPI = 1033,
171 ZYNQMP_PM_RESET_UART0 = 1034,
172 ZYNQMP_PM_RESET_UART1 = 1035,
173 ZYNQMP_PM_RESET_SPI0 = 1036,
174 ZYNQMP_PM_RESET_SPI1 = 1037,
175 ZYNQMP_PM_RESET_SDIO0 = 1038,
176 ZYNQMP_PM_RESET_SDIO1 = 1039,
177 ZYNQMP_PM_RESET_CAN0 = 1040,
178 ZYNQMP_PM_RESET_CAN1 = 1041,
179 ZYNQMP_PM_RESET_I2C0 = 1042,
180 ZYNQMP_PM_RESET_I2C1 = 1043,
181 ZYNQMP_PM_RESET_TTC0 = 1044,
182 ZYNQMP_PM_RESET_TTC1 = 1045,
183 ZYNQMP_PM_RESET_TTC2 = 1046,
184 ZYNQMP_PM_RESET_TTC3 = 1047,
185 ZYNQMP_PM_RESET_SWDT_CRL = 1048,
186 ZYNQMP_PM_RESET_NAND = 1049,
187 ZYNQMP_PM_RESET_ADMA = 1050,
188 ZYNQMP_PM_RESET_GPIO = 1051,
189 ZYNQMP_PM_RESET_IOU_CC = 1052,
190 ZYNQMP_PM_RESET_TIMESTAMP = 1053,
191 ZYNQMP_PM_RESET_RPU_R50 = 1054,
192 ZYNQMP_PM_RESET_RPU_R51 = 1055,
193 ZYNQMP_PM_RESET_RPU_AMBA = 1056,
194 ZYNQMP_PM_RESET_OCM = 1057,
195 ZYNQMP_PM_RESET_RPU_PGE = 1058,
196 ZYNQMP_PM_RESET_USB0_CORERESET = 1059,
197 ZYNQMP_PM_RESET_USB1_CORERESET = 1060,
198 ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061,
199 ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062,
200 ZYNQMP_PM_RESET_USB0_APB = 1063,
201 ZYNQMP_PM_RESET_USB1_APB = 1064,
202 ZYNQMP_PM_RESET_IPI = 1065,
203 ZYNQMP_PM_RESET_APM_LPD = 1066,
204 ZYNQMP_PM_RESET_RTC = 1067,
205 ZYNQMP_PM_RESET_SYSMON = 1068,
206 ZYNQMP_PM_RESET_AFI_FM6 = 1069,
207 ZYNQMP_PM_RESET_LPD_SWDT = 1070,
208 ZYNQMP_PM_RESET_FPD = 1071,
209 ZYNQMP_PM_RESET_RPU_DBG1 = 1072,
210 ZYNQMP_PM_RESET_RPU_DBG0 = 1073,
211 ZYNQMP_PM_RESET_DBG_LPD = 1074,
212 ZYNQMP_PM_RESET_DBG_FPD = 1075,
213 ZYNQMP_PM_RESET_APLL = 1076,
214 ZYNQMP_PM_RESET_DPLL = 1077,
215 ZYNQMP_PM_RESET_VPLL = 1078,
216 ZYNQMP_PM_RESET_IOPLL = 1079,
217 ZYNQMP_PM_RESET_RPLL = 1080,
218 ZYNQMP_PM_RESET_GPO3_PL_0 = 1081,
219 ZYNQMP_PM_RESET_GPO3_PL_1 = 1082,
220 ZYNQMP_PM_RESET_GPO3_PL_2 = 1083,
221 ZYNQMP_PM_RESET_GPO3_PL_3 = 1084,
222 ZYNQMP_PM_RESET_GPO3_PL_4 = 1085,
223 ZYNQMP_PM_RESET_GPO3_PL_5 = 1086,
224 ZYNQMP_PM_RESET_GPO3_PL_6 = 1087,
225 ZYNQMP_PM_RESET_GPO3_PL_7 = 1088,
226 ZYNQMP_PM_RESET_GPO3_PL_8 = 1089,
227 ZYNQMP_PM_RESET_GPO3_PL_9 = 1090,
228 ZYNQMP_PM_RESET_GPO3_PL_10 = 1091,
229 ZYNQMP_PM_RESET_GPO3_PL_11 = 1092,
230 ZYNQMP_PM_RESET_GPO3_PL_12 = 1093,
231 ZYNQMP_PM_RESET_GPO3_PL_13 = 1094,
232 ZYNQMP_PM_RESET_GPO3_PL_14 = 1095,
233 ZYNQMP_PM_RESET_GPO3_PL_15 = 1096,
234 ZYNQMP_PM_RESET_GPO3_PL_16 = 1097,
235 ZYNQMP_PM_RESET_GPO3_PL_17 = 1098,
236 ZYNQMP_PM_RESET_GPO3_PL_18 = 1099,
237 ZYNQMP_PM_RESET_GPO3_PL_19 = 1100,
238 ZYNQMP_PM_RESET_GPO3_PL_20 = 1101,
239 ZYNQMP_PM_RESET_GPO3_PL_21 = 1102,
240 ZYNQMP_PM_RESET_GPO3_PL_22 = 1103,
241 ZYNQMP_PM_RESET_GPO3_PL_23 = 1104,
242 ZYNQMP_PM_RESET_GPO3_PL_24 = 1105,
243 ZYNQMP_PM_RESET_GPO3_PL_25 = 1106,
244 ZYNQMP_PM_RESET_GPO3_PL_26 = 1107,
245 ZYNQMP_PM_RESET_GPO3_PL_27 = 1108,
246 ZYNQMP_PM_RESET_GPO3_PL_28 = 1109,
247 ZYNQMP_PM_RESET_GPO3_PL_29 = 1110,
248 ZYNQMP_PM_RESET_GPO3_PL_30 = 1111,
249 ZYNQMP_PM_RESET_GPO3_PL_31 = 1112,
250 ZYNQMP_PM_RESET_RPU_LS = 1113,
251 ZYNQMP_PM_RESET_PS_ONLY = 1114,
252 ZYNQMP_PM_RESET_PL = 1115,
253 ZYNQMP_PM_RESET_PS_PL0 = 1116,
254 ZYNQMP_PM_RESET_PS_PL1 = 1117,
255 ZYNQMP_PM_RESET_PS_PL2 = 1118,
256 ZYNQMP_PM_RESET_PS_PL3 = 1119,
257 ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
260 enum zynqmp_pm_suspend_reason {
261 SUSPEND_POWER_REQUEST = 201,
263 SUSPEND_SYSTEM_SHUTDOWN = 203,
266 enum zynqmp_pm_request_ack {
267 ZYNQMP_PM_REQUEST_ACK_NO = 1,
268 ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2,
269 ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3,
277 enum tap_delay_type {
278 PM_TAPDELAY_INPUT = 0,
279 PM_TAPDELAY_OUTPUT = 1,
282 enum dll_reset_type {
283 PM_DLL_RESET_ASSERT = 0,
284 PM_DLL_RESET_RELEASE = 1,
285 PM_DLL_RESET_PULSE = 2,
288 enum zynqmp_pm_shutdown_type {
289 ZYNQMP_PM_SHUTDOWN_TYPE_SHUTDOWN = 0,
290 ZYNQMP_PM_SHUTDOWN_TYPE_RESET = 1,
291 ZYNQMP_PM_SHUTDOWN_TYPE_SETSCOPE_ONLY = 2,
294 enum zynqmp_pm_shutdown_subtype {
295 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SUBSYSTEM = 0,
296 ZYNQMP_PM_SHUTDOWN_SUBTYPE_PS_ONLY = 1,
297 ZYNQMP_PM_SHUTDOWN_SUBTYPE_SYSTEM = 2,
301 * struct zynqmp_pm_query_data - PM query data
303 * @arg1: Argument 1 of query data
304 * @arg2: Argument 2 of query data
305 * @arg3: Argument 3 of query data
307 struct zynqmp_pm_query_data {
314 int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
315 u32 arg2, u32 arg3, u32 *ret_payload);
317 #if IS_REACHABLE(CONFIG_ZYNQMP_FIRMWARE)
318 int zynqmp_pm_get_api_version(u32 *version);
319 int zynqmp_pm_get_chipid(u32 *idcode, u32 *version);
320 int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out);
321 int zynqmp_pm_clock_enable(u32 clock_id);
322 int zynqmp_pm_clock_disable(u32 clock_id);
323 int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state);
324 int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider);
325 int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider);
326 int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate);
327 int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate);
328 int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id);
329 int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id);
330 int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode);
331 int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode);
332 int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data);
333 int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data);
334 int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value);
335 int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type);
336 int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
337 const enum zynqmp_pm_reset_action assert_flag);
338 int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status);
339 int zynqmp_pm_init_finalize(void);
340 int zynqmp_pm_set_suspend_mode(u32 mode);
341 int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
342 const u32 qos, const enum zynqmp_pm_request_ack ack);
343 int zynqmp_pm_release_node(const u32 node);
344 int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
346 const enum zynqmp_pm_request_ack ack);
347 int zynqmp_pm_aes_engine(const u64 address, u32 *out);
348 int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags);
349 int zynqmp_pm_fpga_get_status(u32 *value);
350 int zynqmp_pm_write_ggs(u32 index, u32 value);
351 int zynqmp_pm_read_ggs(u32 index, u32 *value);
352 int zynqmp_pm_write_pggs(u32 index, u32 value);
353 int zynqmp_pm_read_pggs(u32 index, u32 *value);
354 int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype);
355 int zynqmp_pm_set_boot_health_status(u32 value);
357 static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
359 return ERR_PTR(-ENODEV);
362 static inline int zynqmp_pm_get_api_version(u32 *version)
367 static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version)
372 static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata,
378 static inline int zynqmp_pm_clock_enable(u32 clock_id)
383 static inline int zynqmp_pm_clock_disable(u32 clock_id)
388 static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state)
393 static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider)
398 static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider)
403 static inline int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate)
408 static inline int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate)
413 static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id)
418 static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
423 static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode)
428 static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode)
433 static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data)
438 static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data)
443 static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value)
448 static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type)
453 static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset,
454 const enum zynqmp_pm_reset_action assert_flag)
459 static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset,
465 static inline int zynqmp_pm_init_finalize(void)
470 static inline int zynqmp_pm_set_suspend_mode(u32 mode)
475 static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
477 const enum zynqmp_pm_request_ack ack)
482 static inline int zynqmp_pm_release_node(const u32 node)
487 static inline int zynqmp_pm_set_requirement(const u32 node,
488 const u32 capabilities,
490 const enum zynqmp_pm_request_ack ack)
495 static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out)
500 static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size,
506 static inline int zynqmp_pm_fpga_get_status(u32 *value)
511 static inline int zynqmp_pm_write_ggs(u32 index, u32 value)
516 static inline int zynqmp_pm_read_ggs(u32 index, u32 *value)
521 static inline int zynqmp_pm_write_pggs(u32 index, u32 value)
526 static inline int zynqmp_pm_read_pggs(u32 index, u32 *value)
531 static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype)
536 static inline int zynqmp_pm_set_boot_health_status(u32 value)
542 #endif /* __FIRMWARE_ZYNQMP_H__ */