1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Xilinx Zynq MPSoC Firmware layer
5 * Copyright (C) 2014-2018 Xilinx
7 * Michal Simek <michal.simek@xilinx.com>
8 * Davorin Mista <davorin.mista@aggios.com>
9 * Jolly Shah <jollys@xilinx.com>
10 * Rajan Vaja <rajanv@xilinx.com>
13 #ifndef __FIRMWARE_ZYNQMP_H__
14 #define __FIRMWARE_ZYNQMP_H__
16 #define ZYNQMP_PM_VERSION_MAJOR 1
17 #define ZYNQMP_PM_VERSION_MINOR 0
19 #define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \
20 ZYNQMP_PM_VERSION_MINOR)
22 #define ZYNQMP_TZ_VERSION_MAJOR 1
23 #define ZYNQMP_TZ_VERSION_MINOR 0
25 #define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \
26 ZYNQMP_TZ_VERSION_MINOR)
28 /* SMC SIP service Call Function Identifier Prefix */
29 #define PM_SIP_SVC 0xC2000000
30 #define PM_GET_TRUSTZONE_VERSION 0xa03
31 #define PM_SET_SUSPEND_MODE 0xa02
32 #define GET_CALLBACK_DATA 0xa01
34 /* Number of 32bits values in payload */
35 #define PAYLOAD_ARG_CNT 4U
37 /* Number of arguments for a callback */
40 /* Payload size (consists of callback API ID + arguments) */
41 #define CB_PAYLOAD_SIZE (CB_ARG_CNT + 1)
43 #define ZYNQMP_PM_MAX_QOS 100U
45 /* Node capabilities */
46 #define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
47 #define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
48 #define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
49 #define ZYNQMP_PM_CAPABILITY_POWER 0x8U
52 PM_GET_API_VERSION = 1,
58 PM_PM_INIT_FINALIZE = 21,
73 /* PMU-FW return status codes */
76 XST_PM_INTERNAL = 2000,
85 IOCTL_SET_PLL_FRAC_MODE = 8,
86 IOCTL_GET_PLL_FRAC_MODE,
87 IOCTL_SET_PLL_FRAC_DATA,
88 IOCTL_GET_PLL_FRAC_DATA,
93 PM_QID_CLOCK_GET_NAME,
94 PM_QID_CLOCK_GET_TOPOLOGY,
95 PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
96 PM_QID_CLOCK_GET_PARENTS,
97 PM_QID_CLOCK_GET_ATTRIBUTES,
98 PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
101 enum zynqmp_pm_reset_action {
102 PM_RESET_ACTION_RELEASE,
103 PM_RESET_ACTION_ASSERT,
104 PM_RESET_ACTION_PULSE,
107 enum zynqmp_pm_reset {
108 ZYNQMP_PM_RESET_START = 1000,
109 ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
110 ZYNQMP_PM_RESET_PCIE_BRIDGE,
111 ZYNQMP_PM_RESET_PCIE_CTRL,
113 ZYNQMP_PM_RESET_SWDT_CRF,
114 ZYNQMP_PM_RESET_AFI_FM5,
115 ZYNQMP_PM_RESET_AFI_FM4,
116 ZYNQMP_PM_RESET_AFI_FM3,
117 ZYNQMP_PM_RESET_AFI_FM2,
118 ZYNQMP_PM_RESET_AFI_FM1,
119 ZYNQMP_PM_RESET_AFI_FM0,
120 ZYNQMP_PM_RESET_GDMA,
121 ZYNQMP_PM_RESET_GPU_PP1,
122 ZYNQMP_PM_RESET_GPU_PP0,
125 ZYNQMP_PM_RESET_SATA,
126 ZYNQMP_PM_RESET_ACPU3_PWRON,
127 ZYNQMP_PM_RESET_ACPU2_PWRON,
128 ZYNQMP_PM_RESET_ACPU1_PWRON,
129 ZYNQMP_PM_RESET_ACPU0_PWRON,
130 ZYNQMP_PM_RESET_APU_L2,
131 ZYNQMP_PM_RESET_ACPU3,
132 ZYNQMP_PM_RESET_ACPU2,
133 ZYNQMP_PM_RESET_ACPU1,
134 ZYNQMP_PM_RESET_ACPU0,
136 ZYNQMP_PM_RESET_APM_FPD,
137 ZYNQMP_PM_RESET_SOFT,
138 ZYNQMP_PM_RESET_GEM0,
139 ZYNQMP_PM_RESET_GEM1,
140 ZYNQMP_PM_RESET_GEM2,
141 ZYNQMP_PM_RESET_GEM3,
142 ZYNQMP_PM_RESET_QSPI,
143 ZYNQMP_PM_RESET_UART0,
144 ZYNQMP_PM_RESET_UART1,
145 ZYNQMP_PM_RESET_SPI0,
146 ZYNQMP_PM_RESET_SPI1,
147 ZYNQMP_PM_RESET_SDIO0,
148 ZYNQMP_PM_RESET_SDIO1,
149 ZYNQMP_PM_RESET_CAN0,
150 ZYNQMP_PM_RESET_CAN1,
151 ZYNQMP_PM_RESET_I2C0,
152 ZYNQMP_PM_RESET_I2C1,
153 ZYNQMP_PM_RESET_TTC0,
154 ZYNQMP_PM_RESET_TTC1,
155 ZYNQMP_PM_RESET_TTC2,
156 ZYNQMP_PM_RESET_TTC3,
157 ZYNQMP_PM_RESET_SWDT_CRL,
158 ZYNQMP_PM_RESET_NAND,
159 ZYNQMP_PM_RESET_ADMA,
160 ZYNQMP_PM_RESET_GPIO,
161 ZYNQMP_PM_RESET_IOU_CC,
162 ZYNQMP_PM_RESET_TIMESTAMP,
163 ZYNQMP_PM_RESET_RPU_R50,
164 ZYNQMP_PM_RESET_RPU_R51,
165 ZYNQMP_PM_RESET_RPU_AMBA,
167 ZYNQMP_PM_RESET_RPU_PGE,
168 ZYNQMP_PM_RESET_USB0_CORERESET,
169 ZYNQMP_PM_RESET_USB1_CORERESET,
170 ZYNQMP_PM_RESET_USB0_HIBERRESET,
171 ZYNQMP_PM_RESET_USB1_HIBERRESET,
172 ZYNQMP_PM_RESET_USB0_APB,
173 ZYNQMP_PM_RESET_USB1_APB,
175 ZYNQMP_PM_RESET_APM_LPD,
177 ZYNQMP_PM_RESET_SYSMON,
178 ZYNQMP_PM_RESET_AFI_FM6,
179 ZYNQMP_PM_RESET_LPD_SWDT,
181 ZYNQMP_PM_RESET_RPU_DBG1,
182 ZYNQMP_PM_RESET_RPU_DBG0,
183 ZYNQMP_PM_RESET_DBG_LPD,
184 ZYNQMP_PM_RESET_DBG_FPD,
185 ZYNQMP_PM_RESET_APLL,
186 ZYNQMP_PM_RESET_DPLL,
187 ZYNQMP_PM_RESET_VPLL,
188 ZYNQMP_PM_RESET_IOPLL,
189 ZYNQMP_PM_RESET_RPLL,
190 ZYNQMP_PM_RESET_GPO3_PL_0,
191 ZYNQMP_PM_RESET_GPO3_PL_1,
192 ZYNQMP_PM_RESET_GPO3_PL_2,
193 ZYNQMP_PM_RESET_GPO3_PL_3,
194 ZYNQMP_PM_RESET_GPO3_PL_4,
195 ZYNQMP_PM_RESET_GPO3_PL_5,
196 ZYNQMP_PM_RESET_GPO3_PL_6,
197 ZYNQMP_PM_RESET_GPO3_PL_7,
198 ZYNQMP_PM_RESET_GPO3_PL_8,
199 ZYNQMP_PM_RESET_GPO3_PL_9,
200 ZYNQMP_PM_RESET_GPO3_PL_10,
201 ZYNQMP_PM_RESET_GPO3_PL_11,
202 ZYNQMP_PM_RESET_GPO3_PL_12,
203 ZYNQMP_PM_RESET_GPO3_PL_13,
204 ZYNQMP_PM_RESET_GPO3_PL_14,
205 ZYNQMP_PM_RESET_GPO3_PL_15,
206 ZYNQMP_PM_RESET_GPO3_PL_16,
207 ZYNQMP_PM_RESET_GPO3_PL_17,
208 ZYNQMP_PM_RESET_GPO3_PL_18,
209 ZYNQMP_PM_RESET_GPO3_PL_19,
210 ZYNQMP_PM_RESET_GPO3_PL_20,
211 ZYNQMP_PM_RESET_GPO3_PL_21,
212 ZYNQMP_PM_RESET_GPO3_PL_22,
213 ZYNQMP_PM_RESET_GPO3_PL_23,
214 ZYNQMP_PM_RESET_GPO3_PL_24,
215 ZYNQMP_PM_RESET_GPO3_PL_25,
216 ZYNQMP_PM_RESET_GPO3_PL_26,
217 ZYNQMP_PM_RESET_GPO3_PL_27,
218 ZYNQMP_PM_RESET_GPO3_PL_28,
219 ZYNQMP_PM_RESET_GPO3_PL_29,
220 ZYNQMP_PM_RESET_GPO3_PL_30,
221 ZYNQMP_PM_RESET_GPO3_PL_31,
222 ZYNQMP_PM_RESET_RPU_LS,
223 ZYNQMP_PM_RESET_PS_ONLY,
225 ZYNQMP_PM_RESET_PS_PL0,
226 ZYNQMP_PM_RESET_PS_PL1,
227 ZYNQMP_PM_RESET_PS_PL2,
228 ZYNQMP_PM_RESET_PS_PL3,
229 ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
232 enum zynqmp_pm_suspend_reason {
233 SUSPEND_POWER_REQUEST = 201,
235 SUSPEND_SYSTEM_SHUTDOWN,
238 enum zynqmp_pm_request_ack {
239 ZYNQMP_PM_REQUEST_ACK_NO = 1,
240 ZYNQMP_PM_REQUEST_ACK_BLOCKING,
241 ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING,
245 * struct zynqmp_pm_query_data - PM query data
247 * @arg1: Argument 1 of query data
248 * @arg2: Argument 2 of query data
249 * @arg3: Argument 3 of query data
251 struct zynqmp_pm_query_data {
258 struct zynqmp_eemi_ops {
259 int (*get_api_version)(u32 *version);
260 int (*get_chipid)(u32 *idcode, u32 *version);
261 int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out);
262 int (*clock_enable)(u32 clock_id);
263 int (*clock_disable)(u32 clock_id);
264 int (*clock_getstate)(u32 clock_id, u32 *state);
265 int (*clock_setdivider)(u32 clock_id, u32 divider);
266 int (*clock_getdivider)(u32 clock_id, u32 *divider);
267 int (*clock_setrate)(u32 clock_id, u64 rate);
268 int (*clock_getrate)(u32 clock_id, u64 *rate);
269 int (*clock_setparent)(u32 clock_id, u32 parent_id);
270 int (*clock_getparent)(u32 clock_id, u32 *parent_id);
271 int (*ioctl)(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, u32 *out);
272 int (*reset_assert)(const enum zynqmp_pm_reset reset,
273 const enum zynqmp_pm_reset_action assert_flag);
274 int (*reset_get_status)(const enum zynqmp_pm_reset reset, u32 *status);
275 int (*init_finalize)(void);
276 int (*set_suspend_mode)(u32 mode);
277 int (*request_node)(const u32 node,
278 const u32 capabilities,
280 const enum zynqmp_pm_request_ack ack);
281 int (*release_node)(const u32 node);
282 int (*set_requirement)(const u32 node,
283 const u32 capabilities,
285 const enum zynqmp_pm_request_ack ack);
288 int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,
289 u32 arg2, u32 arg3, u32 *ret_payload);
291 #if IS_REACHABLE(CONFIG_ARCH_ZYNQMP)
292 const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void);
294 static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void)
300 #endif /* __FIRMWARE_ZYNQMP_H__ */