1 /* SPDX-License-Identifier: MIT */
3 * Copyright (C) 2017 Google, Inc.
6 * Sean Paul <seanpaul@chromium.org>
9 #ifndef _DRM_HDCP_H_INCLUDED_
10 #define _DRM_HDCP_H_INCLUDED_
12 /* Period of hdcp checks (to ensure we're still authenticated) */
13 #define DRM_HDCP_CHECK_PERIOD_MS (128 * 16)
15 /* Shared lengths/masks between HDMI/DVI/DisplayPort */
16 #define DRM_HDCP_AN_LEN 8
17 #define DRM_HDCP_BSTATUS_LEN 2
18 #define DRM_HDCP_KSV_LEN 5
19 #define DRM_HDCP_RI_LEN 2
20 #define DRM_HDCP_V_PRIME_PART_LEN 4
21 #define DRM_HDCP_V_PRIME_NUM_PARTS 5
22 #define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x7f)
23 #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3))
24 #define DRM_HDCP_MAX_DEVICE_EXCEEDED(x) (x & BIT(7))
26 /* Slave address for the HDCP registers in the receiver */
27 #define DRM_HDCP_DDC_ADDR 0x3A
29 /* HDCP register offsets for HDMI/DVI devices */
30 #define DRM_HDCP_DDC_BKSV 0x00
31 #define DRM_HDCP_DDC_RI_PRIME 0x08
32 #define DRM_HDCP_DDC_AKSV 0x10
33 #define DRM_HDCP_DDC_AN 0x18
34 #define DRM_HDCP_DDC_V_PRIME(h) (0x20 + h * 4)
35 #define DRM_HDCP_DDC_BCAPS 0x40
36 #define DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT BIT(6)
37 #define DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY BIT(5)
38 #define DRM_HDCP_DDC_BSTATUS 0x41
39 #define DRM_HDCP_DDC_KSV_FIFO 0x43
41 #define DRM_HDCP_1_4_SRM_ID 0x8
42 #define DRM_HDCP_1_4_VRL_LENGTH_SIZE 3
43 #define DRM_HDCP_1_4_DCP_SIG_SIZE 40
45 /* Protocol message definition for HDCP2.2 specification */
47 * Protected content streams are classified into 2 types:
48 * - Type0: Can be transmitted with HDCP 1.4+
49 * - Type1: Can be transmitted with HDCP 2.2+
51 #define HDCP_STREAM_TYPE0 0x00
52 #define HDCP_STREAM_TYPE1 0x01
55 #define HDCP_2_2_NULL_MSG 1
56 #define HDCP_2_2_AKE_INIT 2
57 #define HDCP_2_2_AKE_SEND_CERT 3
58 #define HDCP_2_2_AKE_NO_STORED_KM 4
59 #define HDCP_2_2_AKE_STORED_KM 5
60 #define HDCP_2_2_AKE_SEND_HPRIME 7
61 #define HDCP_2_2_AKE_SEND_PAIRING_INFO 8
62 #define HDCP_2_2_LC_INIT 9
63 #define HDCP_2_2_LC_SEND_LPRIME 10
64 #define HDCP_2_2_SKE_SEND_EKS 11
65 #define HDCP_2_2_REP_SEND_RECVID_LIST 12
66 #define HDCP_2_2_REP_SEND_ACK 15
67 #define HDCP_2_2_REP_STREAM_MANAGE 16
68 #define HDCP_2_2_REP_STREAM_READY 17
69 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50
71 #define HDCP_2_2_RTX_LEN 8
72 #define HDCP_2_2_RRX_LEN 8
74 #define HDCP_2_2_K_PUB_RX_MOD_N_LEN 128
75 #define HDCP_2_2_K_PUB_RX_EXP_E_LEN 3
76 #define HDCP_2_2_K_PUB_RX_LEN (HDCP_2_2_K_PUB_RX_MOD_N_LEN + \
77 HDCP_2_2_K_PUB_RX_EXP_E_LEN)
79 #define HDCP_2_2_DCP_LLC_SIG_LEN 384
81 #define HDCP_2_2_E_KPUB_KM_LEN 128
82 #define HDCP_2_2_E_KH_KM_M_LEN (16 + 16)
83 #define HDCP_2_2_H_PRIME_LEN 32
84 #define HDCP_2_2_E_KH_KM_LEN 16
85 #define HDCP_2_2_RN_LEN 8
86 #define HDCP_2_2_L_PRIME_LEN 32
87 #define HDCP_2_2_E_DKEY_KS_LEN 16
88 #define HDCP_2_2_RIV_LEN 8
89 #define HDCP_2_2_SEQ_NUM_LEN 3
90 #define HDCP_2_2_V_PRIME_HALF_LEN (HDCP_2_2_L_PRIME_LEN / 2)
91 #define HDCP_2_2_RECEIVER_ID_LEN DRM_HDCP_KSV_LEN
92 #define HDCP_2_2_MAX_DEVICE_COUNT 31
93 #define HDCP_2_2_RECEIVER_IDS_MAX_LEN (HDCP_2_2_RECEIVER_ID_LEN * \
94 HDCP_2_2_MAX_DEVICE_COUNT)
95 #define HDCP_2_2_MPRIME_LEN 32
97 /* Following Macros take a byte at a time for bit(s) masking */
99 * TODO: This has to be changed for DP MST, as multiple stream on
100 * same port is possible.
101 * For HDCP2.2 on HDMI and DP SST this value is always 1.
103 #define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1
104 #define HDCP_2_2_TXCAP_MASK_LEN 2
105 #define HDCP_2_2_RXCAPS_LEN 3
106 #define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0))
107 #define HDCP_2_2_DP_HDCP_CAPABLE(x) ((x) & BIT(1))
108 #define HDCP_2_2_RXINFO_LEN 2
110 /* HDCP1.x compliant device in downstream */
111 #define HDCP_2_2_HDCP1_DEVICE_CONNECTED(x) ((x) & BIT(0))
113 /* HDCP2.0 Compliant repeater in downstream */
114 #define HDCP_2_2_HDCP_2_0_REP_CONNECTED(x) ((x) & BIT(1))
115 #define HDCP_2_2_MAX_CASCADE_EXCEEDED(x) ((x) & BIT(2))
116 #define HDCP_2_2_MAX_DEVS_EXCEEDED(x) ((x) & BIT(3))
117 #define HDCP_2_2_DEV_COUNT_LO(x) (((x) & (0xF << 4)) >> 4)
118 #define HDCP_2_2_DEV_COUNT_HI(x) ((x) & BIT(0))
119 #define HDCP_2_2_DEPTH(x) (((x) & (0x7 << 1)) >> 1)
121 struct hdcp2_cert_rx {
122 u8 receiver_id[HDCP_2_2_RECEIVER_ID_LEN];
123 u8 kpub_rx[HDCP_2_2_K_PUB_RX_LEN];
125 u8 dcp_signature[HDCP_2_2_DCP_LLC_SIG_LEN];
128 struct hdcp2_streamid_type {
134 * The TxCaps field specified in the HDCP HDMI, DP specs
135 * This field is big endian as specified in the errata.
137 struct hdcp2_tx_caps {
138 /* Transmitter must set this to 0x2 */
141 /* Reserved for HDCP and DP Spec. Read as Zero */
142 u8 tx_cap_mask[HDCP_2_2_TXCAP_MASK_LEN];
145 /* Main structures for HDCP2.2 protocol communication */
146 struct hdcp2_ake_init {
148 u8 r_tx[HDCP_2_2_RTX_LEN];
149 struct hdcp2_tx_caps tx_caps;
152 struct hdcp2_ake_send_cert {
154 struct hdcp2_cert_rx cert_rx;
155 u8 r_rx[HDCP_2_2_RRX_LEN];
156 u8 rx_caps[HDCP_2_2_RXCAPS_LEN];
159 struct hdcp2_ake_no_stored_km {
161 u8 e_kpub_km[HDCP_2_2_E_KPUB_KM_LEN];
164 struct hdcp2_ake_stored_km {
166 u8 e_kh_km_m[HDCP_2_2_E_KH_KM_M_LEN];
169 struct hdcp2_ake_send_hprime {
171 u8 h_prime[HDCP_2_2_H_PRIME_LEN];
174 struct hdcp2_ake_send_pairing_info {
176 u8 e_kh_km[HDCP_2_2_E_KH_KM_LEN];
179 struct hdcp2_lc_init {
181 u8 r_n[HDCP_2_2_RN_LEN];
184 struct hdcp2_lc_send_lprime {
186 u8 l_prime[HDCP_2_2_L_PRIME_LEN];
189 struct hdcp2_ske_send_eks {
191 u8 e_dkey_ks[HDCP_2_2_E_DKEY_KS_LEN];
192 u8 riv[HDCP_2_2_RIV_LEN];
195 struct hdcp2_rep_send_receiverid_list {
197 u8 rx_info[HDCP_2_2_RXINFO_LEN];
198 u8 seq_num_v[HDCP_2_2_SEQ_NUM_LEN];
199 u8 v_prime[HDCP_2_2_V_PRIME_HALF_LEN];
200 u8 receiver_ids[HDCP_2_2_RECEIVER_IDS_MAX_LEN];
203 struct hdcp2_rep_send_ack {
205 u8 v[HDCP_2_2_V_PRIME_HALF_LEN];
208 struct hdcp2_rep_stream_manage {
210 u8 seq_num_m[HDCP_2_2_SEQ_NUM_LEN];
212 struct hdcp2_streamid_type streams[HDCP_2_2_MAX_CONTENT_STREAMS_CNT];
215 struct hdcp2_rep_stream_ready {
217 u8 m_prime[HDCP_2_2_MPRIME_LEN];
220 struct hdcp2_dp_errata_stream_type {
225 /* HDCP2.2 TIMEOUTs in mSec */
226 #define HDCP_2_2_CERT_TIMEOUT_MS 100
227 #define HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS 1000
228 #define HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS 200
229 #define HDCP_2_2_PAIRING_TIMEOUT_MS 200
230 #define HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS 20
231 #define HDCP_2_2_DP_LPRIME_TIMEOUT_MS 7
232 #define HDCP_2_2_RECVID_LIST_TIMEOUT_MS 3000
233 #define HDCP_2_2_STREAM_READY_TIMEOUT_MS 100
235 /* HDMI HDCP2.2 Register Offsets */
236 #define HDCP_2_2_HDMI_REG_VER_OFFSET 0x50
237 #define HDCP_2_2_HDMI_REG_WR_MSG_OFFSET 0x60
238 #define HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET 0x70
239 #define HDCP_2_2_HDMI_REG_RD_MSG_OFFSET 0x80
240 #define HDCP_2_2_HDMI_REG_DBG_OFFSET 0xC0
242 #define HDCP_2_2_HDMI_SUPPORT_MASK BIT(2)
243 #define HDCP_2_2_RX_CAPS_VERSION_VAL 0x02
244 #define HDCP_2_2_SEQ_NUM_MAX 0xFFFFFF
245 #define HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN 200
247 /* Below macros take a byte at a time and mask the bit(s) */
248 #define HDCP_2_2_HDMI_RXSTATUS_LEN 2
249 #define HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(x) ((x) & 0x3)
250 #define HDCP_2_2_HDMI_RXSTATUS_READY(x) ((x) & BIT(2))
251 #define HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))