drivers/video/pxafb.c

   1 /*
   2  *  linux/drivers/video/pxafb.c
   3  *
   4  *  Copyright (C) 1999 Eric A. Thomas.
   5  *  Copyright (C) 2004 Jean-Frederic Clere.
   6  *  Copyright (C) 2004 Ian Campbell.
   7  *  Copyright (C) 2004 Jeff Lackey.
   8  *   Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
   9  *  which in turn is
  10  *   Based on acornfb.c Copyright (C) Russell King.
  11  *
  12  * This file is subject to the terms and conditions of the GNU General Public
  13  * License.  See the file COPYING in the main directory of this archive for
  14  * more details.
  15  *
  16  *              Intel PXA250/210 LCD Controller Frame Buffer Driver
  17  *
  18  * Please direct your questions and comments on this driver to the following
  19  * email address:
  20  *
  21  *      linux-arm-kernel@lists.arm.linux.org.uk
  22  *
  23  * Add support for overlay1 and overlay2 based on pxafb_overlay.c:
  24  *
  25  *   Copyright (C) 2004, Intel Corporation
  26  *
  27  *     2003/08/27: <yu.tang@intel.com>
  28  *     2004/03/10: <stanley.cai@intel.com>
  29  *     2004/10/28: <yan.yin@intel.com>
  30  *
  31  *   Copyright (C) 2006-2008 Marvell International Ltd.
  32  *   All Rights Reserved
  33  */
  34
  35 #include <linux/module.h>
  36 #include <linux/moduleparam.h>
  37 #include <linux/kernel.h>
  38 #include <linux/sched.h>
  39 #include <linux/errno.h>
  40 #include <linux/string.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/slab.h>
  43 #include <linux/mm.h>
  44 #include <linux/fb.h>
  45 #include <linux/delay.h>
  46 #include <linux/init.h>
  47 #include <linux/ioport.h>
  48 #include <linux/cpufreq.h>
  49 #include <linux/platform_device.h>
  50 #include <linux/dma-mapping.h>
  51 #include <linux/clk.h>
  52 #include <linux/err.h>
  53 #include <linux/completion.h>
  54 #include <linux/mutex.h>
  55 #include <linux/kthread.h>
  56 #include <linux/freezer.h>
  57
  58 #include <mach/hardware.h>
  59 #include <asm/io.h>
  60 #include <asm/irq.h>
  61 #include <asm/div64.h>
  62 #include <mach/bitfield.h>
  63 #include <mach/pxafb.h>
  64
  65 /*
  66  * Complain if VAR is out of range.
  67  */
  68 #define DEBUG_VAR 1
  69
  70 #include "pxafb.h"
  71
  72 /* Bits which should not be set in machine configuration structures */
  73 #define LCCR0_INVALID_CONFIG_MASK       (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
  74                                          LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
  75                                          LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
  76
  77 #define LCCR3_INVALID_CONFIG_MASK       (LCCR3_HSP | LCCR3_VSP |\
  78                                          LCCR3_PCD | LCCR3_BPP(0xf))
  79
  80 static int pxafb_activate_var(struct fb_var_screeninfo *var,
  81                                 struct pxafb_info *);
  82 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
  83 static void setup_base_frame(struct pxafb_info *fbi,
  84                              struct fb_var_screeninfo *var, int branch);
  85 static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
  86                            unsigned long offset, size_t size);
  87
  88 static unsigned long video_mem_size = 0;
  89
  90 static inline unsigned long
  91 lcd_readl(struct pxafb_info *fbi, unsigned int off)
  92 {
  93         return __raw_readl(fbi->mmio_base + off);
  94 }
  95
  96 static inline void
  97 lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
  98 {
  99         __raw_writel(val, fbi->mmio_base + off);
 100 }
 101
 102 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
 103 {
 104         unsigned long flags;
 105
 106         local_irq_save(flags);
 107         /*
 108          * We need to handle two requests being made at the same time.
 109          * There are two important cases:
 110          *  1. When we are changing VT (C_REENABLE) while unblanking
 111          *     (C_ENABLE) We must perform the unblanking, which will
 112          *     do our REENABLE for us.
 113          *  2. When we are blanking, but immediately unblank before
 114          *     we have blanked.  We do the "REENABLE" thing here as
 115          *     well, just to be sure.
 116          */
 117         if (fbi->task_state == C_ENABLE && state == C_REENABLE)
 118                 state = (u_int) -1;
 119         if (fbi->task_state == C_DISABLE && state == C_ENABLE)
 120                 state = C_REENABLE;
 121
 122         if (state != (u_int)-1) {
 123                 fbi->task_state = state;
 124                 schedule_work(&fbi->task);
 125         }
 126         local_irq_restore(flags);
 127 }
 128
 129 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
 130 {
 131         chan &= 0xffff;
 132         chan >>= 16 - bf->length;
 133         return chan << bf->offset;
 134 }
 135
 136 static int
 137 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
 138                        u_int trans, struct fb_info *info)
 139 {
 140         struct pxafb_info *fbi = (struct pxafb_info *)info;
 141         u_int val;
 142
 143         if (regno >= fbi->palette_size)
 144                 return 1;
 145
 146         if (fbi->fb.var.grayscale) {
 147                 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
 148                 return 0;
 149         }
 150
 151         switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
 152         case LCCR4_PAL_FOR_0:
 153                 val  = ((red   >>  0) & 0xf800);
 154                 val |= ((green >>  5) & 0x07e0);
 155                 val |= ((blue  >> 11) & 0x001f);
 156                 fbi->palette_cpu[regno] = val;
 157                 break;
 158         case LCCR4_PAL_FOR_1:
 159                 val  = ((red   << 8) & 0x00f80000);
 160                 val |= ((green >> 0) & 0x0000fc00);
 161                 val |= ((blue  >> 8) & 0x000000f8);
 162                 ((u32 *)(fbi->palette_cpu))[regno] = val;
 163                 break;
 164         case LCCR4_PAL_FOR_2:
 165                 val  = ((red   << 8) & 0x00fc0000);
 166                 val |= ((green >> 0) & 0x0000fc00);
 167                 val |= ((blue  >> 8) & 0x000000fc);
 168                 ((u32 *)(fbi->palette_cpu))[regno] = val;
 169                 break;
 170         case LCCR4_PAL_FOR_3:
 171                 val  = ((red   << 8) & 0x00ff0000);
 172                 val |= ((green >> 0) & 0x0000ff00);
 173                 val |= ((blue  >> 8) & 0x000000ff);
 174                 ((u32 *)(fbi->palette_cpu))[regno] = val;
 175                 break;
 176         }
 177
 178         return 0;
 179 }
 180
 181 static int
 182 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 183                    u_int trans, struct fb_info *info)
 184 {
 185         struct pxafb_info *fbi = (struct pxafb_info *)info;
 186         unsigned int val;
 187         int ret = 1;
 188
 189         /*
 190          * If inverse mode was selected, invert all the colours
 191          * rather than the register number.  The register number
 192          * is what you poke into the framebuffer to produce the
 193          * colour you requested.
 194          */
 195         if (fbi->cmap_inverse) {
 196                 red   = 0xffff - red;
 197                 green = 0xffff - green;
 198                 blue  = 0xffff - blue;
 199         }
 200
 201         /*
 202          * If greyscale is true, then we convert the RGB value
 203          * to greyscale no matter what visual we are using.
 204          */
 205         if (fbi->fb.var.grayscale)
 206                 red = green = blue = (19595 * red + 38470 * green +
 207                                         7471 * blue) >> 16;
 208
 209         switch (fbi->fb.fix.visual) {
 210         case FB_VISUAL_TRUECOLOR:
 211                 /*
 212                  * 16-bit True Colour.  We encode the RGB value
 213                  * according to the RGB bitfield information.
 214                  */
 215                 if (regno < 16) {
 216                         u32 *pal = fbi->fb.pseudo_palette;
 217
 218                         val  = chan_to_field(red, &fbi->fb.var.red);
 219                         val |= chan_to_field(green, &fbi->fb.var.green);
 220                         val |= chan_to_field(blue, &fbi->fb.var.blue);
 221
 222                         pal[regno] = val;
 223                         ret = 0;
 224                 }
 225                 break;
 226
 227         case FB_VISUAL_STATIC_PSEUDOCOLOR:
 228         case FB_VISUAL_PSEUDOCOLOR:
 229                 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
 230                 break;
 231         }
 232
 233         return ret;
 234 }
 235
 236 /* calculate pixel depth, transparency bit included, >=16bpp formats _only_ */
 237 static inline int var_to_depth(struct fb_var_screeninfo *var)
 238 {
 239         return var->red.length + var->green.length +
 240                 var->blue.length + var->transp.length;
 241 }
 242
 243 /* calculate 4-bit BPP value for LCCR3 and OVLxC1 */
 244 static int pxafb_var_to_bpp(struct fb_var_screeninfo *var)
 245 {
 246         int bpp = -EINVAL;
 247
 248         switch (var->bits_per_pixel) {
 249         case 1:  bpp = 0; break;
 250         case 2:  bpp = 1; break;
 251         case 4:  bpp = 2; break;
 252         case 8:  bpp = 3; break;
 253         case 16: bpp = 4; break;
 254         case 24:
 255                 switch (var_to_depth(var)) {
 256                 case 18: bpp = 6; break; /* 18-bits/pixel packed */
 257                 case 19: bpp = 8; break; /* 19-bits/pixel packed */
 258                 case 24: bpp = 9; break;
 259                 }
 260                 break;
 261         case 32:
 262                 switch (var_to_depth(var)) {
 263                 case 18: bpp = 5; break; /* 18-bits/pixel unpacked */
 264                 case 19: bpp = 7; break; /* 19-bits/pixel unpacked */
 265                 case 25: bpp = 10; break;
 266                 }
 267                 break;
 268         }
 269         return bpp;
 270 }
 271
 272 /*
 273  *  pxafb_var_to_lccr3():
 274  *    Convert a bits per pixel value to the correct bit pattern for LCCR3
 275  *
 276  *  NOTE: for PXA27x with overlays support, the LCCR3_PDFOR_x bits have an
 277  *  implication of the acutal use of transparency bit,  which we handle it
 278  *  here separatedly. See PXA27x Developer's Manual, Section <<7.4.6 Pixel
 279  *  Formats>> for the valid combination of PDFOR, PAL_FOR for various BPP.
 280  *
 281  *  Transparency for palette pixel formats is not supported at the moment.
 282  */
 283 static uint32_t pxafb_var_to_lccr3(struct fb_var_screeninfo *var)
 284 {
 285         int bpp = pxafb_var_to_bpp(var);
 286         uint32_t lccr3;
 287
 288         if (bpp < 0)
 289                 return 0;
 290
 291         lccr3 = LCCR3_BPP(bpp);
 292
 293         switch (var_to_depth(var)) {
 294         case 16: lccr3 |= var->transp.length ? LCCR3_PDFOR_3 : 0; break;
 295         case 18: lccr3 |= LCCR3_PDFOR_3; break;
 296         case 24: lccr3 |= var->transp.length ? LCCR3_PDFOR_2 : LCCR3_PDFOR_3;
 297                  break;
 298         case 19:
 299         case 25: lccr3 |= LCCR3_PDFOR_0; break;
 300         }
 301         return lccr3;
 302 }
 303
 304 #define SET_PIXFMT(v, r, g, b, t)                               \
 305 ({                                                              \
 306         (v)->transp.offset = (t) ? (r) + (g) + (b) : 0;         \
 307         (v)->transp.length = (t) ? (t) : 0;                     \
 308         (v)->blue.length   = (b); (v)->blue.offset = 0;         \
 309         (v)->green.length  = (g); (v)->green.offset = (b);      \
 310         (v)->red.length    = (r); (v)->red.offset = (b) + (g);  \
 311 })
 312
 313 /* set the RGBT bitfields of fb_var_screeninf according to
 314  * var->bits_per_pixel and given depth
 315  */
 316 static void pxafb_set_pixfmt(struct fb_var_screeninfo *var, int depth)
 317 {
 318         if (depth == 0)
 319                 depth = var->bits_per_pixel;
 320
 321         if (var->bits_per_pixel < 16) {
 322                 /* indexed pixel formats */
 323                 var->red.offset    = 0; var->red.length    = 8;
 324                 var->green.offset  = 0; var->green.length  = 8;
 325                 var->blue.offset   = 0; var->blue.length   = 8;
 326                 var->transp.offset = 0; var->transp.length = 8;
 327         }
 328
 329         switch (depth) {
 330         case 16: var->transp.length ?
 331                  SET_PIXFMT(var, 5, 5, 5, 1) :          /* RGBT555 */
 332                  SET_PIXFMT(var, 5, 6, 5, 0); break;    /* RGB565 */
 333         case 18: SET_PIXFMT(var, 6, 6, 6, 0); break;    /* RGB666 */
 334         case 19: SET_PIXFMT(var, 6, 6, 6, 1); break;    /* RGBT666 */
 335         case 24: var->transp.length ?
 336                  SET_PIXFMT(var, 8, 8, 7, 1) :          /* RGBT887 */
 337                  SET_PIXFMT(var, 8, 8, 8, 0); break;    /* RGB888 */
 338         case 25: SET_PIXFMT(var, 8, 8, 8, 1); break;    /* RGBT888 */
 339         }
 340 }
 341
 342 #ifdef CONFIG_CPU_FREQ
 343 /*
 344  *  pxafb_display_dma_period()
 345  *    Calculate the minimum period (in picoseconds) between two DMA
 346  *    requests for the LCD controller.  If we hit this, it means we're
 347  *    doing nothing but LCD DMA.
 348  */
 349 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
 350 {
 351         /*
 352          * Period = pixclock * bits_per_byte * bytes_per_transfer
 353          *              / memory_bits_per_pixel;
 354          */
 355         return var->pixclock * 8 * 16 / var->bits_per_pixel;
 356 }
 357 #endif
 358
 359 /*
 360  * Select the smallest mode that allows the desired resolution to be
 361  * displayed. If desired parameters can be rounded up.
 362  */
 363 static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
 364                                              struct fb_var_screeninfo *var)
 365 {
 366         struct pxafb_mode_info *mode = NULL;
 367         struct pxafb_mode_info *modelist = mach->modes;
 368         unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
 369         unsigned int i;
 370
 371         for (i = 0; i < mach->num_modes; i++) {
 372                 if (modelist[i].xres >= var->xres &&
 373                     modelist[i].yres >= var->yres &&
 374                     modelist[i].xres < best_x &&
 375                     modelist[i].yres < best_y &&
 376                     modelist[i].bpp >= var->bits_per_pixel) {
 377                         best_x = modelist[i].xres;
 378                         best_y = modelist[i].yres;
 379                         mode = &modelist[i];
 380                 }
 381         }
 382
 383         return mode;
 384 }
 385
 386 static void pxafb_setmode(struct fb_var_screeninfo *var,
 387                           struct pxafb_mode_info *mode)
 388 {
 389         var->xres               = mode->xres;
 390         var->yres               = mode->yres;
 391         var->bits_per_pixel     = mode->bpp;
 392         var->pixclock           = mode->pixclock;
 393         var->hsync_len          = mode->hsync_len;
 394         var->left_margin        = mode->left_margin;
 395         var->right_margin       = mode->right_margin;
 396         var->vsync_len          = mode->vsync_len;
 397         var->upper_margin       = mode->upper_margin;
 398         var->lower_margin       = mode->lower_margin;
 399         var->sync               = mode->sync;
 400         var->grayscale          = mode->cmap_greyscale;
 401         var->transp.length      = mode->transparency;
 402
 403         /* set the initial RGBA bitfields */
 404         pxafb_set_pixfmt(var, mode->depth);
 405 }
 406
 407 static int pxafb_adjust_timing(struct pxafb_info *fbi,
 408                                struct fb_var_screeninfo *var)
 409 {
 410         int line_length;
 411
 412         var->xres = max_t(int, var->xres, MIN_XRES);
 413         var->yres = max_t(int, var->yres, MIN_YRES);
 414
 415         if (!(fbi->lccr0 & LCCR0_LCDT)) {
 416                 clamp_val(var->hsync_len, 1, 64);
 417                 clamp_val(var->vsync_len, 1, 64);
 418                 clamp_val(var->left_margin,  1, 255);
 419                 clamp_val(var->right_margin, 1, 255);
 420                 clamp_val(var->upper_margin, 1, 255);
 421                 clamp_val(var->lower_margin, 1, 255);
 422         }
 423
 424         /* make sure each line is aligned on word boundary */
 425         line_length = var->xres * var->bits_per_pixel / 8;
 426         line_length = ALIGN(line_length, 4);
 427         var->xres = line_length * 8 / var->bits_per_pixel;
 428
 429         /* we don't support xpan, force xres_virtual to be equal to xres */
 430         var->xres_virtual = var->xres;
 431
 432         if (var->accel_flags & FB_ACCELF_TEXT)
 433                 var->yres_virtual = fbi->fb.fix.smem_len / line_length;
 434         else
 435                 var->yres_virtual = max(var->yres_virtual, var->yres);
 436
 437         /* check for limits */
 438         if (var->xres > MAX_XRES || var->yres > MAX_YRES)
 439                 return -EINVAL;
 440
 441         if (var->yres > var->yres_virtual)
 442                 return -EINVAL;
 443
 444         return 0;
 445 }
 446
 447 /*
 448  *  pxafb_check_var():
 449  *    Get the video params out of 'var'. If a value doesn't fit, round it up,
 450  *    if it's too big, return -EINVAL.
 451  *
 452  *    Round up in the following order: bits_per_pixel, xres,
 453  *    yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
 454  *    bitfields, horizontal timing, vertical timing.
 455  */
 456 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 457 {
 458         struct pxafb_info *fbi = (struct pxafb_info *)info;
 459         struct pxafb_mach_info *inf = fbi->dev->platform_data;
 460         int err;
 461
 462         if (inf->fixed_modes) {
 463                 struct pxafb_mode_info *mode;
 464
 465                 mode = pxafb_getmode(inf, var);
 466                 if (!mode)
 467                         return -EINVAL;
 468                 pxafb_setmode(var, mode);
 469         }
 470
 471         /* do a test conversion to BPP fields to check the color formats */
 472         err = pxafb_var_to_bpp(var);
 473         if (err < 0)
 474                 return err;
 475
 476         pxafb_set_pixfmt(var, var_to_depth(var));
 477
 478         err = pxafb_adjust_timing(fbi, var);
 479         if (err)
 480                 return err;
 481
 482 #ifdef CONFIG_CPU_FREQ
 483         pr_debug("pxafb: dma period = %d ps\n",
 484                  pxafb_display_dma_period(var));
 485 #endif
 486
 487         return 0;
 488 }
 489
 490 /*
 491  * pxafb_set_par():
 492  *      Set the user defined part of the display for the specified console
 493  */
 494 static int pxafb_set_par(struct fb_info *info)
 495 {
 496         struct pxafb_info *fbi = (struct pxafb_info *)info;
 497         struct fb_var_screeninfo *var = &info->var;
 498
 499         if (var->bits_per_pixel >= 16)
 500                 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
 501         else if (!fbi->cmap_static)
 502                 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
 503         else {
 504                 /*
 505                  * Some people have weird ideas about wanting static
 506                  * pseudocolor maps.  I suspect their user space
 507                  * applications are broken.
 508                  */
 509                 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
 510         }
 511
 512         fbi->fb.fix.line_length = var->xres_virtual *
 513                                   var->bits_per_pixel / 8;
 514         if (var->bits_per_pixel >= 16)
 515                 fbi->palette_size = 0;
 516         else
 517                 fbi->palette_size = var->bits_per_pixel == 1 ?
 518                                         4 : 1 << var->bits_per_pixel;
 519
 520         fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
 521
 522         if (fbi->fb.var.bits_per_pixel >= 16)
 523                 fb_dealloc_cmap(&fbi->fb.cmap);
 524         else
 525                 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
 526
 527         pxafb_activate_var(var, fbi);
 528
 529         return 0;
 530 }
 531
 532 static int pxafb_pan_display(struct fb_var_screeninfo *var,
 533                              struct fb_info *info)
 534 {
 535         struct pxafb_info *fbi = (struct pxafb_info *)info;
 536         struct fb_var_screeninfo newvar;
 537         int dma = DMA_MAX + DMA_BASE;
 538
 539         if (fbi->state != C_ENABLE)
 540                 return 0;
 541
 542         /* Only take .xoffset, .yoffset and .vmode & FB_VMODE_YWRAP from what
 543          * was passed in and copy the rest from the old screeninfo.
 544          */
 545         memcpy(&newvar, &fbi->fb.var, sizeof(newvar));
 546         newvar.xoffset = var->xoffset;
 547         newvar.yoffset = var->yoffset;
 548         newvar.vmode &= ~FB_VMODE_YWRAP;
 549         newvar.vmode |= var->vmode & FB_VMODE_YWRAP;
 550
 551         setup_base_frame(fbi, &newvar, 1);
 552
 553         if (fbi->lccr0 & LCCR0_SDS)
 554                 lcd_writel(fbi, FBR1, fbi->fdadr[dma + 1] | 0x1);
 555
 556         lcd_writel(fbi, FBR0, fbi->fdadr[dma] | 0x1);
 557         return 0;
 558 }
 559
 560 /*
 561  * pxafb_blank():
 562  *      Blank the display by setting all palette values to zero.  Note, the
 563  *      16 bpp mode does not really use the palette, so this will not
 564  *      blank the display in all modes.
 565  */
 566 static int pxafb_blank(int blank, struct fb_info *info)
 567 {
 568         struct pxafb_info *fbi = (struct pxafb_info *)info;
 569         int i;
 570
 571         switch (blank) {
 572         case FB_BLANK_POWERDOWN:
 573         case FB_BLANK_VSYNC_SUSPEND:
 574         case FB_BLANK_HSYNC_SUSPEND:
 575         case FB_BLANK_NORMAL:
 576                 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
 577                     fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
 578                         for (i = 0; i < fbi->palette_size; i++)
 579                                 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
 580
 581                 pxafb_schedule_work(fbi, C_DISABLE);
 582                 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
 583                 break;
 584
 585         case FB_BLANK_UNBLANK:
 586                 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
 587                 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
 588                     fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
 589                         fb_set_cmap(&fbi->fb.cmap, info);
 590                 pxafb_schedule_work(fbi, C_ENABLE);
 591         }
 592         return 0;
 593 }
 594
 595 static struct fb_ops pxafb_ops = {
 596         .owner          = THIS_MODULE,
 597         .fb_check_var   = pxafb_check_var,
 598         .fb_set_par     = pxafb_set_par,
 599         .fb_pan_display = pxafb_pan_display,
 600         .fb_setcolreg   = pxafb_setcolreg,
 601         .fb_fillrect    = cfb_fillrect,
 602         .fb_copyarea    = cfb_copyarea,
 603         .fb_imageblit   = cfb_imageblit,
 604         .fb_blank       = pxafb_blank,
 605 };
 606
 607 #ifdef CONFIG_FB_PXA_OVERLAY
 608 static void overlay1fb_setup(struct pxafb_layer *ofb)
 609 {
 610         int size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
 611         unsigned long start = ofb->video_mem_phys;
 612         setup_frame_dma(ofb->fbi, DMA_OV1, PAL_NONE, start, size);
 613 }
 614
 615 /* Depending on the enable status of overlay1/2, the DMA should be
 616  * updated from FDADRx (when disabled) or FBRx (when enabled).
 617  */
 618 static void overlay1fb_enable(struct pxafb_layer *ofb)
 619 {
 620         int enabled = lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN;
 621         uint32_t fdadr1 = ofb->fbi->fdadr[DMA_OV1] | (enabled ? 0x1 : 0);
 622
 623         lcd_writel(ofb->fbi, enabled ? FBR1 : FDADR1, fdadr1);
 624         lcd_writel(ofb->fbi, OVL1C2, ofb->control[1]);
 625         lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] | OVLxC1_OEN);
 626 }
 627
 628 static void overlay1fb_disable(struct pxafb_layer *ofb)
 629 {
 630         uint32_t lccr5 = lcd_readl(ofb->fbi, LCCR5);
 631
 632         lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] & ~OVLxC1_OEN);
 633
 634         lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(1));
 635         lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(1));
 636         lcd_writel(ofb->fbi, FBR1, ofb->fbi->fdadr[DMA_OV1] | 0x3);
 637
 638         if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
 639                 pr_warning("%s: timeout disabling overlay1\n", __func__);
 640
 641         lcd_writel(ofb->fbi, LCCR5, lccr5);
 642 }
 643
 644 static void overlay2fb_setup(struct pxafb_layer *ofb)
 645 {
 646         int size, div = 1, pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
 647         unsigned long start[3] = { ofb->video_mem_phys, 0, 0 };
 648
 649         if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED) {
 650                 size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
 651                 setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
 652         } else {
 653                 size = ofb->fb.var.xres_virtual * ofb->fb.var.yres_virtual;
 654                 switch (pfor) {
 655                 case OVERLAY_FORMAT_YUV444_PLANAR: div = 1; break;
 656                 case OVERLAY_FORMAT_YUV422_PLANAR: div = 2; break;
 657                 case OVERLAY_FORMAT_YUV420_PLANAR: div = 4; break;
 658                 }
 659                 start[1] = start[0] + size;
 660                 start[2] = start[1] + size / div;
 661                 setup_frame_dma(ofb->fbi, DMA_OV2_Y,  -1, start[0], size);
 662                 setup_frame_dma(ofb->fbi, DMA_OV2_Cb, -1, start[1], size / div);
 663                 setup_frame_dma(ofb->fbi, DMA_OV2_Cr, -1, start[2], size / div);
 664         }
 665 }
 666
 667 static void overlay2fb_enable(struct pxafb_layer *ofb)
 668 {
 669         int pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
 670         int enabled = lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN;
 671         uint32_t fdadr2 = ofb->fbi->fdadr[DMA_OV2_Y]  | (enabled ? 0x1 : 0);
 672         uint32_t fdadr3 = ofb->fbi->fdadr[DMA_OV2_Cb] | (enabled ? 0x1 : 0);
 673         uint32_t fdadr4 = ofb->fbi->fdadr[DMA_OV2_Cr] | (enabled ? 0x1 : 0);
 674
 675         if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED)
 676                 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
 677         else {
 678                 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
 679                 lcd_writel(ofb->fbi, enabled ? FBR3 : FDADR3, fdadr3);
 680                 lcd_writel(ofb->fbi, enabled ? FBR4 : FDADR4, fdadr4);
 681         }
 682         lcd_writel(ofb->fbi, OVL2C2, ofb->control[1]);
 683         lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] | OVLxC1_OEN);
 684 }
 685
 686 static void overlay2fb_disable(struct pxafb_layer *ofb)
 687 {
 688         uint32_t lccr5 = lcd_readl(ofb->fbi, LCCR5);
 689
 690         lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] & ~OVLxC1_OEN);
 691
 692         lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(2));
 693         lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(2));
 694         lcd_writel(ofb->fbi, FBR2, ofb->fbi->fdadr[DMA_OV2_Y]  | 0x3);
 695         lcd_writel(ofb->fbi, FBR3, ofb->fbi->fdadr[DMA_OV2_Cb] | 0x3);
 696         lcd_writel(ofb->fbi, FBR4, ofb->fbi->fdadr[DMA_OV2_Cr] | 0x3);
 697
 698         if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
 699                 pr_warning("%s: timeout disabling overlay2\n", __func__);
 700 }
 701
 702 static struct pxafb_layer_ops ofb_ops[] = {
 703         [0] = {
 704                 .enable         = overlay1fb_enable,
 705                 .disable        = overlay1fb_disable,
 706                 .setup          = overlay1fb_setup,
 707         },
 708         [1] = {
 709                 .enable         = overlay2fb_enable,
 710                 .disable        = overlay2fb_disable,
 711                 .setup          = overlay2fb_setup,
 712         },
 713 };
 714
 715 static int overlayfb_open(struct fb_info *info, int user)
 716 {
 717         struct pxafb_layer *ofb = (struct pxafb_layer *)info;
 718
 719         /* no support for framebuffer console on overlay */
 720         if (user == 0)
 721                 return -ENODEV;
 722
 723         /* allow only one user at a time */
 724         if (atomic_inc_and_test(&ofb->usage))
 725                 return -EBUSY;
 726
 727         /* unblank the base framebuffer */
 728         fb_blank(&ofb->fbi->fb, FB_BLANK_UNBLANK);
 729         return 0;
 730 }
 731
 732 static int overlayfb_release(struct fb_info *info, int user)
 733 {
 734         struct pxafb_layer *ofb = (struct pxafb_layer*) info;
 735
 736         atomic_dec(&ofb->usage);
 737         ofb->ops->disable(ofb);
 738
 739         free_pages_exact(ofb->video_mem, ofb->video_mem_size);
 740         ofb->video_mem = NULL;
 741         ofb->video_mem_size = 0;
 742         return 0;
 743 }
 744
 745 static int overlayfb_check_var(struct fb_var_screeninfo *var,
 746                                struct fb_info *info)
 747 {
 748         struct pxafb_layer *ofb = (struct pxafb_layer *)info;
 749         struct fb_var_screeninfo *base_var = &ofb->fbi->fb.var;
 750         int xpos, ypos, pfor, bpp;
 751
 752         xpos = NONSTD_TO_XPOS(var->nonstd);
 753         ypos = NONSTD_TO_XPOS(var->nonstd);
 754         pfor = NONSTD_TO_PFOR(var->nonstd);
 755
 756         bpp = pxafb_var_to_bpp(var);
 757         if (bpp < 0)
 758                 return -EINVAL;
 759
 760         /* no support for YUV format on overlay1 */
 761         if (ofb->id == OVERLAY1 && pfor != 0)
 762                 return -EINVAL;
 763
 764         /* for YUV packed formats, bpp = 'minimum bpp of YUV components' */
 765         switch (pfor) {
 766         case OVERLAY_FORMAT_RGB:
 767                 bpp = pxafb_var_to_bpp(var);
 768                 if (bpp < 0)
 769                         return -EINVAL;
 770
 771                 pxafb_set_pixfmt(var, var_to_depth(var));
 772                 break;
 773         case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
 774         case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 8; break;
 775         case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 4; break;
 776         case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 2; break;
 777         default:
 778                 return -EINVAL;
 779         }
 780
 781         /* each line must start at a 32-bit word boundary */
 782         if ((xpos * bpp) % 32)
 783                 return -EINVAL;
 784
 785         /* xres must align on 32-bit word boundary */
 786         var->xres = roundup(var->xres * bpp, 32) / bpp;
 787
 788         if ((xpos + var->xres > base_var->xres) ||
 789             (ypos + var->yres > base_var->yres))
 790                 return -EINVAL;
 791
 792         var->xres_virtual = var->xres;
 793         var->yres_virtual = max(var->yres, var->yres_virtual);
 794         return 0;
 795 }
 796
 797 static int overlayfb_map_video_memory(struct pxafb_layer *ofb)
 798 {
 799         struct fb_var_screeninfo *var = &ofb->fb.var;
 800         int pfor = NONSTD_TO_PFOR(var->nonstd);
 801         int size, bpp = 0;
 802
 803         switch (pfor) {
 804         case OVERLAY_FORMAT_RGB: bpp = var->bits_per_pixel; break;
 805         case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
 806         case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 24; break;
 807         case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 16; break;
 808         case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 12; break;
 809         }
 810
 811         ofb->fb.fix.line_length = var->xres_virtual * bpp / 8;
 812
 813         size = PAGE_ALIGN(ofb->fb.fix.line_length * var->yres_virtual);
 814
 815         /* don't re-allocate if the original video memory is enough */
 816         if (ofb->video_mem) {
 817                 if (ofb->video_mem_size >= size)
 818                         return 0;
 819
 820                 free_pages_exact(ofb->video_mem, ofb->video_mem_size);
 821         }
 822
 823         ofb->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
 824         if (ofb->video_mem == NULL)
 825                 return -ENOMEM;
 826
 827         ofb->video_mem_phys = virt_to_phys(ofb->video_mem);
 828         ofb->video_mem_size = size;
 829
 830         mutex_lock(&ofb->fb.mm_lock);
 831         ofb->fb.fix.smem_start  = ofb->video_mem_phys;
 832         ofb->fb.fix.smem_len    = ofb->fb.fix.line_length * var->yres_virtual;
 833         mutex_unlock(&ofb->fb.mm_lock);
 834         ofb->fb.screen_base     = ofb->video_mem;
 835         return 0;
 836 }
 837
 838 static int overlayfb_set_par(struct fb_info *info)
 839 {
 840         struct pxafb_layer *ofb = (struct pxafb_layer *)info;
 841         struct fb_var_screeninfo *var = &info->var;
 842         int xpos, ypos, pfor, bpp, ret;
 843
 844         ret = overlayfb_map_video_memory(ofb);
 845         if (ret)
 846                 return ret;
 847
 848         bpp  = pxafb_var_to_bpp(var);
 849         xpos = NONSTD_TO_XPOS(var->nonstd);
 850         ypos = NONSTD_TO_XPOS(var->nonstd);
 851         pfor = NONSTD_TO_PFOR(var->nonstd);
 852
 853         ofb->control[0] = OVLxC1_PPL(var->xres) | OVLxC1_LPO(var->yres) |
 854                           OVLxC1_BPP(bpp);
 855         ofb->control[1] = OVLxC2_XPOS(xpos) | OVLxC2_YPOS(ypos);
 856
 857         if (ofb->id == OVERLAY2)
 858                 ofb->control[1] |= OVL2C2_PFOR(pfor);
 859
 860         ofb->ops->setup(ofb);
 861         ofb->ops->enable(ofb);
 862         return 0;
 863 }
 864
 865 static struct fb_ops overlay_fb_ops = {
 866         .owner                  = THIS_MODULE,
 867         .fb_open                = overlayfb_open,
 868         .fb_release             = overlayfb_release,
 869         .fb_check_var           = overlayfb_check_var,
 870         .fb_set_par             = overlayfb_set_par,
 871 };
 872
 873 static void __devinit init_pxafb_overlay(struct pxafb_info *fbi,
 874                                          struct pxafb_layer *ofb, int id)
 875 {
 876         sprintf(ofb->fb.fix.id, "overlay%d", id + 1);
 877
 878         ofb->fb.fix.type                = FB_TYPE_PACKED_PIXELS;
 879         ofb->fb.fix.xpanstep            = 0;
 880         ofb->fb.fix.ypanstep            = 1;
 881
 882         ofb->fb.var.activate            = FB_ACTIVATE_NOW;
 883         ofb->fb.var.height              = -1;
 884         ofb->fb.var.width               = -1;
 885         ofb->fb.var.vmode               = FB_VMODE_NONINTERLACED;
 886
 887         ofb->fb.fbops                   = &overlay_fb_ops;
 888         ofb->fb.flags                   = FBINFO_FLAG_DEFAULT;
 889         ofb->fb.node                    = -1;
 890         ofb->fb.pseudo_palette          = NULL;
 891
 892         ofb->id = id;
 893         ofb->ops = &ofb_ops[id];
 894         atomic_set(&ofb->usage, 0);
 895         ofb->fbi = fbi;
 896         init_completion(&ofb->branch_done);
 897 }
 898
 899 static inline int pxafb_overlay_supported(void)
 900 {
 901         if (cpu_is_pxa27x() || cpu_is_pxa3xx())
 902                 return 1;
 903
 904         return 0;
 905 }
 906
 907 static int __devinit pxafb_overlay_init(struct pxafb_info *fbi)
 908 {
 909         int i, ret;
 910
 911         if (!pxafb_overlay_supported())
 912                 return 0;
 913
 914         for (i = 0; i < 2; i++) {
 915                 init_pxafb_overlay(fbi, &fbi->overlay[i], i);
 916                 ret = register_framebuffer(&fbi->overlay[i].fb);
 917                 if (ret) {
 918                         dev_err(fbi->dev, "failed to register overlay %d\n", i);
 919                         return ret;
 920                 }
 921         }
 922
 923         /* mask all IU/BS/EOF/SOF interrupts */
 924         lcd_writel(fbi, LCCR5, ~0);
 925
 926         /* place overlay(s) on top of base */
 927         fbi->lccr0 |= LCCR0_OUC;
 928         pr_info("PXA Overlay driver loaded successfully!\n");
 929         return 0;
 930 }
 931
 932 static void __devexit pxafb_overlay_exit(struct pxafb_info *fbi)
 933 {
 934         int i;
 935
 936         if (!pxafb_overlay_supported())
 937                 return;
 938
 939         for (i = 0; i < 2; i++)
 940                 unregister_framebuffer(&fbi->overlay[i].fb);
 941 }
 942 #else
 943 static inline void pxafb_overlay_init(struct pxafb_info *fbi) {}
 944 static inline void pxafb_overlay_exit(struct pxafb_info *fbi) {}
 945 #endif /* CONFIG_FB_PXA_OVERLAY */
 946
 947 /*
 948  * Calculate the PCD value from the clock rate (in picoseconds).
 949  * We take account of the PPCR clock setting.
 950  * From PXA Developer's Manual:
 951  *
 952  *   PixelClock =      LCLK
 953  *                -------------
 954  *                2 ( PCD + 1 )
 955  *
 956  *   PCD =      LCLK
 957  *         ------------- - 1
 958  *         2(PixelClock)
 959  *
 960  * Where:
 961  *   LCLK = LCD/Memory Clock
 962  *   PCD = LCCR3[7:0]
 963  *
 964  * PixelClock here is in Hz while the pixclock argument given is the
 965  * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
 966  *
 967  * The function get_lclk_frequency_10khz returns LCLK in units of
 968  * 10khz. Calling the result of this function lclk gives us the
 969  * following
 970  *
 971  *    PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
 972  *          -------------------------------------- - 1
 973  *                          2
 974  *
 975  * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
 976  */
 977 static inline unsigned int get_pcd(struct pxafb_info *fbi,
 978                                    unsigned int pixclock)
 979 {
 980         unsigned long long pcd;
 981
 982         /* FIXME: Need to take into account Double Pixel Clock mode
 983          * (DPC) bit? or perhaps set it based on the various clock
 984          * speeds */
 985         pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
 986         pcd *= pixclock;
 987         do_div(pcd, 100000000 * 2);
 988         /* no need for this, since we should subtract 1 anyway. they cancel */
 989         /* pcd += 1; */ /* make up for integer math truncations */
 990         return (unsigned int)pcd;
 991 }
 992
 993 /*
 994  * Some touchscreens need hsync information from the video driver to
 995  * function correctly. We export it here.  Note that 'hsync_time' and
 996  * the value returned from pxafb_get_hsync_time() is the *reciprocal*
 997  * of the hsync period in seconds.
 998  */
 999 static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
1000 {
1001         unsigned long htime;
1002
1003         if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
1004                 fbi->hsync_time = 0;
1005                 return;
1006         }
1007
1008         htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
1009
1010         fbi->hsync_time = htime;
1011 }
1012
1013 unsigned long pxafb_get_hsync_time(struct device *dev)
1014 {
1015         struct pxafb_info *fbi = dev_get_drvdata(dev);
1016
1017         /* If display is blanked/suspended, hsync isn't active */
1018         if (!fbi || (fbi->state != C_ENABLE))
1019                 return 0;
1020
1021         return fbi->hsync_time;
1022 }
1023 EXPORT_SYMBOL(pxafb_get_hsync_time);
1024
1025 static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
1026                            unsigned long start, size_t size)
1027 {
1028         struct pxafb_dma_descriptor *dma_desc, *pal_desc;
1029         unsigned int dma_desc_off, pal_desc_off;
1030
1031         if (dma < 0 || dma >= DMA_MAX * 2)
1032                 return -EINVAL;
1033
1034         dma_desc = &fbi->dma_buff->dma_desc[dma];
1035         dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
1036
1037         dma_desc->fsadr = start;
1038         dma_desc->fidr  = 0;
1039         dma_desc->ldcmd = size;
1040
1041         if (pal < 0 || pal >= PAL_MAX * 2) {
1042                 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1043                 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
1044         } else {
1045                 pal_desc = &fbi->dma_buff->pal_desc[pal];
1046                 pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]);
1047
1048                 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
1049                 pal_desc->fidr  = 0;
1050
1051                 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
1052                         pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
1053                 else
1054                         pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
1055
1056                 pal_desc->ldcmd |= LDCMD_PAL;
1057
1058                 /* flip back and forth between palette and frame buffer */
1059                 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1060                 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
1061                 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
1062         }
1063
1064         return 0;
1065 }
1066
1067 static void setup_base_frame(struct pxafb_info *fbi,
1068                              struct fb_var_screeninfo *var,
1069                              int branch)
1070 {
1071         struct fb_fix_screeninfo *fix = &fbi->fb.fix;
1072         int nbytes, dma, pal, bpp = var->bits_per_pixel;
1073         unsigned long offset;
1074
1075         dma = DMA_BASE + (branch ? DMA_MAX : 0);
1076         pal = (bpp >= 16) ? PAL_NONE : PAL_BASE + (branch ? PAL_MAX : 0);
1077
1078         nbytes = fix->line_length * var->yres;
1079         offset = fix->line_length * var->yoffset + fbi->video_mem_phys;
1080
1081         if (fbi->lccr0 & LCCR0_SDS) {
1082                 nbytes = nbytes / 2;
1083                 setup_frame_dma(fbi, dma + 1, PAL_NONE, offset + nbytes, nbytes);
1084         }
1085
1086         setup_frame_dma(fbi, dma, pal, offset, nbytes);
1087 }
1088
1089 #ifdef CONFIG_FB_PXA_SMARTPANEL
1090 static int setup_smart_dma(struct pxafb_info *fbi)
1091 {
1092         struct pxafb_dma_descriptor *dma_desc;
1093         unsigned long dma_desc_off, cmd_buff_off;
1094
1095         dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
1096         dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
1097         cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
1098
1099         dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1100         dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
1101         dma_desc->fidr  = 0;
1102         dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
1103
1104         fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
1105         return 0;
1106 }
1107
1108 int pxafb_smart_flush(struct fb_info *info)
1109 {
1110         struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
1111         uint32_t prsr;
1112         int ret = 0;
1113
1114         /* disable controller until all registers are set up */
1115         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1116
1117         /* 1. make it an even number of commands to align on 32-bit boundary
1118          * 2. add the interrupt command to the end of the chain so we can
1119          *    keep track of the end of the transfer
1120          */
1121
1122         while (fbi->n_smart_cmds & 1)
1123                 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
1124
1125         fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
1126         fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
1127         setup_smart_dma(fbi);
1128
1129         /* continue to execute next command */
1130         prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
1131         lcd_writel(fbi, PRSR, prsr);
1132
1133         /* stop the processor in case it executed "wait for sync" cmd */
1134         lcd_writel(fbi, CMDCR, 0x0001);
1135
1136         /* don't send interrupts for fifo underruns on channel 6 */
1137         lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
1138
1139         lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1140         lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1141         lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1142         lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
1143         lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1144         lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
1145
1146         /* begin sending */
1147         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1148
1149         if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
1150                 pr_warning("%s: timeout waiting for command done\n",
1151                                 __func__);
1152                 ret = -ETIMEDOUT;
1153         }
1154
1155         /* quick disable */
1156         prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
1157         lcd_writel(fbi, PRSR, prsr);
1158         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1159         lcd_writel(fbi, FDADR6, 0);
1160         fbi->n_smart_cmds = 0;
1161         return ret;
1162 }
1163
1164 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
1165 {
1166         int i;
1167         struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
1168
1169         for (i = 0; i < n_cmds; i++, cmds++) {
1170                 /* if it is a software delay, flush and delay */
1171                 if ((*cmds & 0xff00) == SMART_CMD_DELAY) {
1172                         pxafb_smart_flush(info);
1173                         mdelay(*cmds & 0xff);
1174                         continue;
1175                 }
1176
1177                 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
1178                 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
1179                         pxafb_smart_flush(info);
1180
1181                 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds;
1182         }
1183
1184         return 0;
1185 }
1186
1187 static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
1188 {
1189         unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
1190         return (t == 0) ? 1 : t;
1191 }
1192
1193 static void setup_smart_timing(struct pxafb_info *fbi,
1194                                 struct fb_var_screeninfo *var)
1195 {
1196         struct pxafb_mach_info *inf = fbi->dev->platform_data;
1197         struct pxafb_mode_info *mode = &inf->modes[0];
1198         unsigned long lclk = clk_get_rate(fbi->clk);
1199         unsigned t1, t2, t3, t4;
1200
1201         t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
1202         t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
1203         t3 = mode->op_hold_time;
1204         t4 = mode->cmd_inh_time;
1205
1206         fbi->reg_lccr1 =
1207                 LCCR1_DisWdth(var->xres) |
1208                 LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
1209                 LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
1210                 LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
1211
1212         fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
1213         fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk));
1214         fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0;
1215         fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0;
1216
1217         /* FIXME: make this configurable */
1218         fbi->reg_cmdcr = 1;
1219 }
1220
1221 static int pxafb_smart_thread(void *arg)
1222 {
1223         struct pxafb_info *fbi = arg;
1224         struct pxafb_mach_info *inf = fbi->dev->platform_data;
1225
1226         if (!inf->smart_update) {
1227                 pr_err("%s: not properly initialized, thread terminated\n",
1228                                 __func__);
1229                 return -EINVAL;
1230         }
1231         inf = fbi->dev->platform_data;
1232
1233         pr_debug("%s(): task starting\n", __func__);
1234
1235         set_freezable();
1236         while (!kthread_should_stop()) {
1237
1238                 if (try_to_freeze())
1239                         continue;
1240
1241                 mutex_lock(&fbi->ctrlr_lock);
1242
1243                 if (fbi->state == C_ENABLE) {
1244                         inf->smart_update(&fbi->fb);
1245                         complete(&fbi->refresh_done);
1246                 }
1247
1248                 mutex_unlock(&fbi->ctrlr_lock);
1249
1250                 set_current_state(TASK_INTERRUPTIBLE);
1251                 schedule_timeout(30 * HZ / 1000);
1252         }
1253
1254         pr_debug("%s(): task ending\n", __func__);
1255         return 0;
1256 }
1257
1258 static int pxafb_smart_init(struct pxafb_info *fbi)
1259 {
1260         if (!(fbi->lccr0 & LCCR0_LCDT))
1261                 return 0;
1262
1263         fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
1264         fbi->n_smart_cmds = 0;
1265
1266         init_completion(&fbi->command_done);
1267         init_completion(&fbi->refresh_done);
1268
1269         fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
1270                                         "lcd_refresh");
1271         if (IS_ERR(fbi->smart_thread)) {
1272                 pr_err("%s: unable to create kernel thread\n", __func__);
1273                 return PTR_ERR(fbi->smart_thread);
1274         }
1275
1276         return 0;
1277 }
1278 #else
1279 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
1280 {
1281         return 0;
1282 }
1283
1284 int pxafb_smart_flush(struct fb_info *info)
1285 {
1286         return 0;
1287 }
1288
1289 static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; }
1290 #endif /* CONFIG_FB_PXA_SMARTPANEL */
1291
1292 static void setup_parallel_timing(struct pxafb_info *fbi,
1293                                   struct fb_var_screeninfo *var)
1294 {
1295         unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
1296
1297         fbi->reg_lccr1 =
1298                 LCCR1_DisWdth(var->xres) +
1299                 LCCR1_HorSnchWdth(var->hsync_len) +
1300                 LCCR1_BegLnDel(var->left_margin) +
1301                 LCCR1_EndLnDel(var->right_margin);
1302
1303         /*
1304          * If we have a dual scan LCD, we need to halve
1305          * the YRES parameter.
1306          */
1307         lines_per_panel = var->yres;
1308         if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1309                 lines_per_panel /= 2;
1310
1311         fbi->reg_lccr2 =
1312                 LCCR2_DisHght(lines_per_panel) +
1313                 LCCR2_VrtSnchWdth(var->vsync_len) +
1314                 LCCR2_BegFrmDel(var->upper_margin) +
1315                 LCCR2_EndFrmDel(var->lower_margin);
1316
1317         fbi->reg_lccr3 = fbi->lccr3 |
1318                 (var->sync & FB_SYNC_HOR_HIGH_ACT ?
1319                  LCCR3_HorSnchH : LCCR3_HorSnchL) |
1320                 (var->sync & FB_SYNC_VERT_HIGH_ACT ?
1321                  LCCR3_VrtSnchH : LCCR3_VrtSnchL);
1322
1323         if (pcd) {
1324                 fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
1325                 set_hsync_time(fbi, pcd);
1326         }
1327 }
1328
1329 /*
1330  * pxafb_activate_var():
1331  *      Configures LCD Controller based on entries in var parameter.
1332  *      Settings are only written to the controller if changes were made.
1333  */
1334 static int pxafb_activate_var(struct fb_var_screeninfo *var,
1335                               struct pxafb_info *fbi)
1336 {
1337         u_long flags;
1338
1339         /* Update shadow copy atomically */
1340         local_irq_save(flags);
1341
1342 #ifdef CONFIG_FB_PXA_SMARTPANEL
1343         if (fbi->lccr0 & LCCR0_LCDT)
1344                 setup_smart_timing(fbi, var);
1345         else
1346 #endif
1347                 setup_parallel_timing(fbi, var);
1348
1349         setup_base_frame(fbi, var, 0);
1350
1351         fbi->reg_lccr0 = fbi->lccr0 |
1352                 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
1353                  LCCR0_QDM | LCCR0_BM  | LCCR0_OUM);
1354
1355         fbi->reg_lccr3 |= pxafb_var_to_lccr3(var);
1356
1357         fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
1358         fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
1359         local_irq_restore(flags);
1360
1361         /*
1362          * Only update the registers if the controller is enabled
1363          * and something has changed.
1364          */
1365         if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
1366             (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
1367             (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
1368             (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
1369             (lcd_readl(fbi, LCCR4) != fbi->reg_lccr4) ||
1370             (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
1371             (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))
1372                 pxafb_schedule_work(fbi, C_REENABLE);
1373
1374         return 0;
1375 }
1376
1377 /*
1378  * NOTE!  The following functions are purely helpers for set_ctrlr_state.
1379  * Do not call them directly; set_ctrlr_state does the correct serialisation
1380  * to ensure that things happen in the right way 100% of time time.
1381  *      -- rmk
1382  */
1383 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
1384 {
1385         pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
1386
1387         if (fbi->backlight_power)
1388                 fbi->backlight_power(on);
1389 }
1390
1391 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
1392 {
1393         pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
1394
1395         if (fbi->lcd_power)
1396                 fbi->lcd_power(on, &fbi->fb.var);
1397 }
1398
1399 static void pxafb_enable_controller(struct pxafb_info *fbi)
1400 {
1401         pr_debug("pxafb: Enabling LCD controller\n");
1402         pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
1403         pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
1404         pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
1405         pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
1406         pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
1407         pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
1408
1409         /* enable LCD controller clock */
1410         clk_enable(fbi->clk);
1411
1412         if (fbi->lccr0 & LCCR0_LCDT)
1413                 return;
1414
1415         /* Sequence from 11.7.10 */
1416         lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
1417         lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1418         lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1419         lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1420         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1421
1422         lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1423         lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
1424         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1425 }
1426
1427 static void pxafb_disable_controller(struct pxafb_info *fbi)
1428 {
1429         uint32_t lccr0;
1430
1431 #ifdef CONFIG_FB_PXA_SMARTPANEL
1432         if (fbi->lccr0 & LCCR0_LCDT) {
1433                 wait_for_completion_timeout(&fbi->refresh_done,
1434                                 200 * HZ / 1000);
1435                 return;
1436         }
1437 #endif
1438
1439         /* Clear LCD Status Register */
1440         lcd_writel(fbi, LCSR, 0xffffffff);
1441
1442         lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
1443         lcd_writel(fbi, LCCR0, lccr0);
1444         lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
1445
1446         wait_for_completion_timeout(&fbi->disable_done, 200 * HZ / 1000);
1447
1448         /* disable LCD controller clock */
1449         clk_disable(fbi->clk);
1450 }
1451
1452 /*
1453  *  pxafb_handle_irq: Handle 'LCD DONE' interrupts.
1454  */
1455 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1456 {
1457         struct pxafb_info *fbi = dev_id;
1458         unsigned int lccr0, lcsr;
1459
1460         lcsr = lcd_readl(fbi, LCSR);
1461         if (lcsr & LCSR_LDD) {
1462                 lccr0 = lcd_readl(fbi, LCCR0);
1463                 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
1464                 complete(&fbi->disable_done);
1465         }
1466
1467 #ifdef CONFIG_FB_PXA_SMARTPANEL
1468         if (lcsr & LCSR_CMD_INT)
1469                 complete(&fbi->command_done);
1470 #endif
1471         lcd_writel(fbi, LCSR, lcsr);
1472
1473 #ifdef CONFIG_FB_PXA_OVERLAY
1474         {
1475                 unsigned int lcsr1 = lcd_readl(fbi, LCSR1);
1476                 if (lcsr1 & LCSR1_BS(1))
1477                         complete(&fbi->overlay[0].branch_done);
1478
1479                 if (lcsr1 & LCSR1_BS(2))
1480                         complete(&fbi->overlay[1].branch_done);
1481
1482                 lcd_writel(fbi, LCSR1, lcsr1);
1483         }
1484 #endif
1485         return IRQ_HANDLED;
1486 }
1487
1488 /*
1489  * This function must be called from task context only, since it will
1490  * sleep when disabling the LCD controller, or if we get two contending
1491  * processes trying to alter state.
1492  */
1493 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1494 {
1495         u_int old_state;
1496
1497         mutex_lock(&fbi->ctrlr_lock);
1498
1499         old_state = fbi->state;
1500
1501         /*
1502          * Hack around fbcon initialisation.
1503          */
1504         if (old_state == C_STARTUP && state == C_REENABLE)
1505                 state = C_ENABLE;
1506
1507         switch (state) {
1508         case C_DISABLE_CLKCHANGE:
1509                 /*
1510                  * Disable controller for clock change.  If the
1511                  * controller is already disabled, then do nothing.
1512                  */
1513                 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1514                         fbi->state = state;
1515                         /* TODO __pxafb_lcd_power(fbi, 0); */
1516                         pxafb_disable_controller(fbi);
1517                 }
1518                 break;
1519
1520         case C_DISABLE_PM:
1521         case C_DISABLE:
1522                 /*
1523                  * Disable controller
1524                  */
1525                 if (old_state != C_DISABLE) {
1526                         fbi->state = state;
1527                         __pxafb_backlight_power(fbi, 0);
1528                         __pxafb_lcd_power(fbi, 0);
1529                         if (old_state != C_DISABLE_CLKCHANGE)
1530                                 pxafb_disable_controller(fbi);
1531                 }
1532                 break;
1533
1534         case C_ENABLE_CLKCHANGE:
1535                 /*
1536                  * Enable the controller after clock change.  Only
1537                  * do this if we were disabled for the clock change.
1538                  */
1539                 if (old_state == C_DISABLE_CLKCHANGE) {
1540                         fbi->state = C_ENABLE;
1541                         pxafb_enable_controller(fbi);
1542                         /* TODO __pxafb_lcd_power(fbi, 1); */
1543                 }
1544                 break;
1545
1546         case C_REENABLE:
1547                 /*
1548                  * Re-enable the controller only if it was already
1549                  * enabled.  This is so we reprogram the control
1550                  * registers.
1551                  */
1552                 if (old_state == C_ENABLE) {
1553                         __pxafb_lcd_power(fbi, 0);
1554                         pxafb_disable_controller(fbi);
1555                         pxafb_enable_controller(fbi);
1556                         __pxafb_lcd_power(fbi, 1);
1557                 }
1558                 break;
1559
1560         case C_ENABLE_PM:
1561                 /*
1562                  * Re-enable the controller after PM.  This is not
1563                  * perfect - think about the case where we were doing
1564                  * a clock change, and we suspended half-way through.
1565                  */
1566                 if (old_state != C_DISABLE_PM)
1567                         break;
1568                 /* fall through */
1569
1570         case C_ENABLE:
1571                 /*
1572                  * Power up the LCD screen, enable controller, and
1573                  * turn on the backlight.
1574                  */
1575                 if (old_state != C_ENABLE) {
1576                         fbi->state = C_ENABLE;
1577                         pxafb_enable_controller(fbi);
1578                         __pxafb_lcd_power(fbi, 1);
1579                         __pxafb_backlight_power(fbi, 1);
1580                 }
1581                 break;
1582         }
1583         mutex_unlock(&fbi->ctrlr_lock);
1584 }
1585
1586 /*
1587  * Our LCD controller task (which is called when we blank or unblank)
1588  * via keventd.
1589  */
1590 static void pxafb_task(struct work_struct *work)
1591 {
1592         struct pxafb_info *fbi =
1593                 container_of(work, struct pxafb_info, task);
1594         u_int state = xchg(&fbi->task_state, -1);
1595
1596         set_ctrlr_state(fbi, state);
1597 }
1598
1599 #ifdef CONFIG_CPU_FREQ
1600 /*
1601  * CPU clock speed change handler.  We need to adjust the LCD timing
1602  * parameters when the CPU clock is adjusted by the power management
1603  * subsystem.
1604  *
1605  * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
1606  */
1607 static int
1608 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
1609 {
1610         struct pxafb_info *fbi = TO_INF(nb, freq_transition);
1611         /* TODO struct cpufreq_freqs *f = data; */
1612         u_int pcd;
1613
1614         switch (val) {
1615         case CPUFREQ_PRECHANGE:
1616                 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1617                 break;
1618
1619         case CPUFREQ_POSTCHANGE:
1620                 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
1621                 set_hsync_time(fbi, pcd);
1622                 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
1623                                   LCCR3_PixClkDiv(pcd);
1624                 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1625                 break;
1626         }
1627         return 0;
1628 }
1629
1630 static int
1631 pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
1632 {
1633         struct pxafb_info *fbi = TO_INF(nb, freq_policy);
1634         struct fb_var_screeninfo *var = &fbi->fb.var;
1635         struct cpufreq_policy *policy = data;
1636
1637         switch (val) {
1638         case CPUFREQ_ADJUST:
1639         case CPUFREQ_INCOMPATIBLE:
1640                 pr_debug("min dma period: %d ps, "
1641                         "new clock %d kHz\n", pxafb_display_dma_period(var),
1642                         policy->max);
1643                 /* TODO: fill in min/max values */
1644                 break;
1645         }
1646         return 0;
1647 }
1648 #endif
1649
1650 #ifdef CONFIG_PM
1651 /*
1652  * Power management hooks.  Note that we won't be called from IRQ context,
1653  * unlike the blank functions above, so we may sleep.
1654  */
1655 static int pxafb_suspend(struct device *dev)
1656 {
1657         struct pxafb_info *fbi = dev_get_drvdata(dev);
1658
1659         set_ctrlr_state(fbi, C_DISABLE_PM);
1660         return 0;
1661 }
1662
1663 static int pxafb_resume(struct device *dev)
1664 {
1665         struct pxafb_info *fbi = dev_get_drvdata(dev);
1666
1667         set_ctrlr_state(fbi, C_ENABLE_PM);
1668         return 0;
1669 }
1670
1671 static const struct dev_pm_ops pxafb_pm_ops = {
1672         .suspend        = pxafb_suspend,
1673         .resume         = pxafb_resume,
1674 };
1675 #endif
1676
1677 static int __devinit pxafb_init_video_memory(struct pxafb_info *fbi)
1678 {
1679         int size = PAGE_ALIGN(fbi->video_mem_size);
1680
1681         fbi->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
1682         if (fbi->video_mem == NULL)
1683                 return -ENOMEM;
1684
1685         fbi->video_mem_phys = virt_to_phys(fbi->video_mem);
1686         fbi->video_mem_size = size;
1687
1688         fbi->fb.fix.smem_start  = fbi->video_mem_phys;
1689         fbi->fb.fix.smem_len    = fbi->video_mem_size;
1690         fbi->fb.screen_base     = fbi->video_mem;
1691
1692         return fbi->video_mem ? 0 : -ENOMEM;
1693 }
1694
1695 static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1696                                    struct pxafb_mach_info *inf)
1697 {
1698         unsigned int lcd_conn = inf->lcd_conn;
1699         struct pxafb_mode_info *m;
1700         int i;
1701
1702         fbi->cmap_inverse       = inf->cmap_inverse;
1703         fbi->cmap_static        = inf->cmap_static;
1704         fbi->lccr4              = inf->lccr4;
1705
1706         switch (lcd_conn & LCD_TYPE_MASK) {
1707         case LCD_TYPE_MONO_STN:
1708                 fbi->lccr0 = LCCR0_CMS;
1709                 break;
1710         case LCD_TYPE_MONO_DSTN:
1711                 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1712                 break;
1713         case LCD_TYPE_COLOR_STN:
1714                 fbi->lccr0 = 0;
1715                 break;
1716         case LCD_TYPE_COLOR_DSTN:
1717                 fbi->lccr0 = LCCR0_SDS;
1718                 break;
1719         case LCD_TYPE_COLOR_TFT:
1720                 fbi->lccr0 = LCCR0_PAS;
1721                 break;
1722         case LCD_TYPE_SMART_PANEL:
1723                 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1724                 break;
1725         default:
1726                 /* fall back to backward compatibility way */
1727                 fbi->lccr0 = inf->lccr0;
1728                 fbi->lccr3 = inf->lccr3;
1729                 goto decode_mode;
1730         }
1731
1732         if (lcd_conn == LCD_MONO_STN_8BPP)
1733                 fbi->lccr0 |= LCCR0_DPD;
1734
1735         fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0;
1736
1737         fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1738         fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1739         fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL)  ? LCCR3_PCP : 0;
1740
1741 decode_mode:
1742         pxafb_setmode(&fbi->fb.var, &inf->modes[0]);
1743
1744         /* decide video memory size as follows:
1745          * 1. default to mode of maximum resolution
1746          * 2. allow platform to override
1747          * 3. allow module parameter to override
1748          */
1749         for (i = 0, m = &inf->modes[0]; i < inf->num_modes; i++, m++)
1750                 fbi->video_mem_size = max_t(size_t, fbi->video_mem_size,
1751                                 m->xres * m->yres * m->bpp / 8);
1752
1753         if (inf->video_mem_size > fbi->video_mem_size)
1754                 fbi->video_mem_size = inf->video_mem_size;
1755
1756         if (video_mem_size > fbi->video_mem_size)
1757                 fbi->video_mem_size = video_mem_size;
1758 }
1759
1760 static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
1761 {
1762         struct pxafb_info *fbi;
1763         void *addr;
1764         struct pxafb_mach_info *inf = dev->platform_data;
1765
1766         /* Alloc the pxafb_info and pseudo_palette in one step */
1767         fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1768         if (!fbi)
1769                 return NULL;
1770
1771         memset(fbi, 0, sizeof(struct pxafb_info));
1772         fbi->dev = dev;
1773
1774         fbi->clk = clk_get(dev, NULL);
1775         if (IS_ERR(fbi->clk)) {
1776                 kfree(fbi);
1777                 return NULL;
1778         }
1779
1780         strcpy(fbi->fb.fix.id, PXA_NAME);
1781
1782         fbi->fb.fix.type        = FB_TYPE_PACKED_PIXELS;
1783         fbi->fb.fix.type_aux    = 0;
1784         fbi->fb.fix.xpanstep    = 0;
1785         fbi->fb.fix.ypanstep    = 1;
1786         fbi->fb.fix.ywrapstep   = 0;
1787         fbi->fb.fix.accel       = FB_ACCEL_NONE;
1788
1789         fbi->fb.var.nonstd      = 0;
1790         fbi->fb.var.activate    = FB_ACTIVATE_NOW;
1791         fbi->fb.var.height      = -1;
1792         fbi->fb.var.width       = -1;
1793         fbi->fb.var.accel_flags = FB_ACCELF_TEXT;
1794         fbi->fb.var.vmode       = FB_VMODE_NONINTERLACED;
1795
1796         fbi->fb.fbops           = &pxafb_ops;
1797         fbi->fb.flags           = FBINFO_DEFAULT;
1798         fbi->fb.node            = -1;
1799
1800         addr = fbi;
1801         addr = addr + sizeof(struct pxafb_info);
1802         fbi->fb.pseudo_palette  = addr;
1803
1804         fbi->state              = C_STARTUP;
1805         fbi->task_state         = (u_char)-1;
1806
1807         pxafb_decode_mach_info(fbi, inf);
1808
1809         init_waitqueue_head(&fbi->ctrlr_wait);
1810         INIT_WORK(&fbi->task, pxafb_task);
1811         mutex_init(&fbi->ctrlr_lock);
1812         init_completion(&fbi->disable_done);
1813
1814         return fbi;
1815 }
1816
1817 #ifdef CONFIG_FB_PXA_PARAMETERS
1818 static int __devinit parse_opt_mode(struct device *dev, const char *this_opt)
1819 {
1820         struct pxafb_mach_info *inf = dev->platform_data;
1821
1822         const char *name = this_opt+5;
1823         unsigned int namelen = strlen(name);
1824         int res_specified = 0, bpp_specified = 0;
1825         unsigned int xres = 0, yres = 0, bpp = 0;
1826         int yres_specified = 0;
1827         int i;
1828         for (i = namelen-1; i >= 0; i--) {
1829                 switch (name[i]) {
1830                 case '-':
1831                         namelen = i;
1832                         if (!bpp_specified && !yres_specified) {
1833                                 bpp = simple_strtoul(&name[i+1], NULL, 0);
1834                                 bpp_specified = 1;
1835                         } else
1836                                 goto done;
1837                         break;
1838                 case 'x':
1839                         if (!yres_specified) {
1840                                 yres = simple_strtoul(&name[i+1], NULL, 0);
1841                                 yres_specified = 1;
1842                         } else
1843                                 goto done;
1844                         break;
1845                 case '0' ... '9':
1846                         break;
1847                 default:
1848                         goto done;
1849                 }
1850         }
1851         if (i < 0 && yres_specified) {
1852                 xres = simple_strtoul(name, NULL, 0);
1853                 res_specified = 1;
1854         }
1855 done:
1856         if (res_specified) {
1857                 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1858                 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1859         }
1860         if (bpp_specified)
1861                 switch (bpp) {
1862                 case 1:
1863                 case 2:
1864                 case 4:
1865                 case 8:
1866                 case 16:
1867                         inf->modes[0].bpp = bpp;
1868                         dev_info(dev, "overriding bit depth: %d\n", bpp);
1869                         break;
1870                 default:
1871                         dev_err(dev, "Depth %d is not valid\n", bpp);
1872                         return -EINVAL;
1873                 }
1874         return 0;
1875 }
1876
1877 static int __devinit parse_opt(struct device *dev, char *this_opt)
1878 {
1879         struct pxafb_mach_info *inf = dev->platform_data;
1880         struct pxafb_mode_info *mode = &inf->modes[0];
1881         char s[64];
1882
1883         s[0] = '\0';
1884
1885         if (!strncmp(this_opt, "vmem:", 5)) {
1886                 video_mem_size = memparse(this_opt + 5, NULL);
1887         } else if (!strncmp(this_opt, "mode:", 5)) {
1888                 return parse_opt_mode(dev, this_opt);
1889         } else if (!strncmp(this_opt, "pixclock:", 9)) {
1890                 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1891                 sprintf(s, "pixclock: %ld\n", mode->pixclock);
1892         } else if (!strncmp(this_opt, "left:", 5)) {
1893                 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1894                 sprintf(s, "left: %u\n", mode->left_margin);
1895         } else if (!strncmp(this_opt, "right:", 6)) {
1896                 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1897                 sprintf(s, "right: %u\n", mode->right_margin);
1898         } else if (!strncmp(this_opt, "upper:", 6)) {
1899                 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1900                 sprintf(s, "upper: %u\n", mode->upper_margin);
1901         } else if (!strncmp(this_opt, "lower:", 6)) {
1902                 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1903                 sprintf(s, "lower: %u\n", mode->lower_margin);
1904         } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1905                 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1906                 sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1907         } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1908                 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1909                 sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1910         } else if (!strncmp(this_opt, "hsync:", 6)) {
1911                 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1912                         sprintf(s, "hsync: Active Low\n");
1913                         mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1914                 } else {
1915                         sprintf(s, "hsync: Active High\n");
1916                         mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1917                 }
1918         } else if (!strncmp(this_opt, "vsync:", 6)) {
1919                 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1920                         sprintf(s, "vsync: Active Low\n");
1921                         mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1922                 } else {
1923                         sprintf(s, "vsync: Active High\n");
1924                         mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1925                 }
1926         } else if (!strncmp(this_opt, "dpc:", 4)) {
1927                 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1928                         sprintf(s, "double pixel clock: false\n");
1929                         inf->lccr3 &= ~LCCR3_DPC;
1930                 } else {
1931                         sprintf(s, "double pixel clock: true\n");
1932                         inf->lccr3 |= LCCR3_DPC;
1933                 }
1934         } else if (!strncmp(this_opt, "outputen:", 9)) {
1935                 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1936                         sprintf(s, "output enable: active low\n");
1937                         inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1938                 } else {
1939                         sprintf(s, "output enable: active high\n");
1940                         inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1941                 }
1942         } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1943                 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1944                         sprintf(s, "pixel clock polarity: falling edge\n");
1945                         inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1946                 } else {
1947                         sprintf(s, "pixel clock polarity: rising edge\n");
1948                         inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1949                 }
1950         } else if (!strncmp(this_opt, "color", 5)) {
1951                 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1952         } else if (!strncmp(this_opt, "mono", 4)) {
1953                 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1954         } else if (!strncmp(this_opt, "active", 6)) {
1955                 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1956         } else if (!strncmp(this_opt, "passive", 7)) {
1957                 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1958         } else if (!strncmp(this_opt, "single", 6)) {
1959                 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1960         } else if (!strncmp(this_opt, "dual", 4)) {
1961                 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1962         } else if (!strncmp(this_opt, "4pix", 4)) {
1963                 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1964         } else if (!strncmp(this_opt, "8pix", 4)) {
1965                 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1966         } else {
1967                 dev_err(dev, "unknown option: %s\n", this_opt);
1968                 return -EINVAL;
1969         }
1970
1971         if (s[0] != '\0')
1972                 dev_info(dev, "override %s", s);
1973
1974         return 0;
1975 }
1976
1977 static int __devinit pxafb_parse_options(struct device *dev, char *options)
1978 {
1979         char *this_opt;
1980         int ret;
1981
1982         if (!options || !*options)
1983                 return 0;
1984
1985         dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1986
1987         /* could be made table driven or similar?... */
1988         while ((this_opt = strsep(&options, ",")) != NULL) {
1989                 ret = parse_opt(dev, this_opt);
1990                 if (ret)
1991                         return ret;
1992         }
1993         return 0;
1994 }
1995
1996 static char g_options[256] __devinitdata = "";
1997
1998 #ifndef MODULE
1999 static int __init pxafb_setup_options(void)
2000 {
2001         char *options = NULL;
2002
2003         if (fb_get_options("pxafb", &options))
2004                 return -ENODEV;
2005
2006         if (options)
2007                 strlcpy(g_options, options, sizeof(g_options));
2008
2009         return 0;
2010 }
2011 #else
2012 #define pxafb_setup_options()           (0)
2013
2014 module_param_string(options, g_options, sizeof(g_options), 0);
2015 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
2016 #endif
2017
2018 #else
2019 #define pxafb_parse_options(...)        (0)
2020 #define pxafb_setup_options()           (0)
2021 #endif
2022
2023 #ifdef DEBUG_VAR
2024 /* Check for various illegal bit-combinations. Currently only
2025  * a warning is given. */
2026 static void __devinit pxafb_check_options(struct device *dev,
2027                                           struct pxafb_mach_info *inf)
2028 {
2029         if (inf->lcd_conn)
2030                 return;
2031
2032         if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
2033                 dev_warn(dev, "machine LCCR0 setting contains "
2034                                 "illegal bits: %08x\n",
2035                         inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
2036         if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
2037                 dev_warn(dev, "machine LCCR3 setting contains "
2038                                 "illegal bits: %08x\n",
2039                         inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
2040         if (inf->lccr0 & LCCR0_DPD &&
2041             ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
2042              (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
2043              (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
2044                 dev_warn(dev, "Double Pixel Data (DPD) mode is "
2045                                 "only valid in passive mono"
2046                                 " single panel mode\n");
2047         if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
2048             (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
2049                 dev_warn(dev, "Dual panel only valid in passive mode\n");
2050         if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
2051              (inf->modes->upper_margin || inf->modes->lower_margin))
2052                 dev_warn(dev, "Upper and lower margins must be 0 in "
2053                                 "passive mode\n");
2054 }
2055 #else
2056 #define pxafb_check_options(...)        do {} while (0)
2057 #endif
2058
2059 static int __devinit pxafb_probe(struct platform_device *dev)
2060 {
2061         struct pxafb_info *fbi;
2062         struct pxafb_mach_info *inf;
2063         struct resource *r;
2064         int irq, ret;
2065
2066         dev_dbg(&dev->dev, "pxafb_probe\n");
2067
2068         inf = dev->dev.platform_data;
2069         ret = -ENOMEM;
2070         fbi = NULL;
2071         if (!inf)
2072                 goto failed;
2073
2074         ret = pxafb_parse_options(&dev->dev, g_options);
2075         if (ret < 0)
2076                 goto failed;
2077
2078         pxafb_check_options(&dev->dev, inf);
2079
2080         dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
2081                         inf->modes->xres,
2082                         inf->modes->yres,
2083                         inf->modes->bpp);
2084         if (inf->modes->xres == 0 ||
2085             inf->modes->yres == 0 ||
2086             inf->modes->bpp == 0) {
2087                 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
2088                 ret = -EINVAL;
2089                 goto failed;
2090         }
2091
2092         fbi = pxafb_init_fbinfo(&dev->dev);
2093         if (!fbi) {
2094                 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
2095                 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
2096                 ret = -ENOMEM;
2097                 goto failed;
2098         }
2099
2100         if (cpu_is_pxa3xx() && inf->acceleration_enabled)
2101                 fbi->fb.fix.accel = FB_ACCEL_PXA3XX;
2102
2103         fbi->backlight_power = inf->pxafb_backlight_power;
2104         fbi->lcd_power = inf->pxafb_lcd_power;
2105
2106         r = platform_get_resource(dev, IORESOURCE_MEM, 0);
2107         if (r == NULL) {
2108                 dev_err(&dev->dev, "no I/O memory resource defined\n");
2109                 ret = -ENODEV;
2110                 goto failed_fbi;
2111         }
2112
2113         r = request_mem_region(r->start, resource_size(r), dev->name);
2114         if (r == NULL) {
2115                 dev_err(&dev->dev, "failed to request I/O memory\n");
2116                 ret = -EBUSY;
2117                 goto failed_fbi;
2118         }
2119
2120         fbi->mmio_base = ioremap(r->start, resource_size(r));
2121         if (fbi->mmio_base == NULL) {
2122                 dev_err(&dev->dev, "failed to map I/O memory\n");
2123                 ret = -EBUSY;
2124                 goto failed_free_res;
2125         }
2126
2127         fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
2128         fbi->dma_buff = dma_alloc_coherent(fbi->dev, fbi->dma_buff_size,
2129                                 &fbi->dma_buff_phys, GFP_KERNEL);
2130         if (fbi->dma_buff == NULL) {
2131                 dev_err(&dev->dev, "failed to allocate memory for DMA\n");
2132                 ret = -ENOMEM;
2133                 goto failed_free_io;
2134         }
2135
2136         ret = pxafb_init_video_memory(fbi);
2137         if (ret) {
2138                 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
2139                 ret = -ENOMEM;
2140                 goto failed_free_dma;
2141         }
2142
2143         irq = platform_get_irq(dev, 0);
2144         if (irq < 0) {
2145                 dev_err(&dev->dev, "no IRQ defined\n");
2146                 ret = -ENODEV;
2147                 goto failed_free_mem;
2148         }
2149
2150         ret = request_irq(irq, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
2151         if (ret) {
2152                 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
2153                 ret = -EBUSY;
2154                 goto failed_free_mem;
2155         }
2156
2157         ret = pxafb_smart_init(fbi);
2158         if (ret) {
2159                 dev_err(&dev->dev, "failed to initialize smartpanel\n");
2160                 goto failed_free_irq;
2161         }
2162
2163         /*
2164          * This makes sure that our colour bitfield
2165          * descriptors are correctly initialised.
2166          */
2167         ret = pxafb_check_var(&fbi->fb.var, &fbi->fb);
2168         if (ret) {
2169                 dev_err(&dev->dev, "failed to get suitable mode\n");
2170                 goto failed_free_irq;
2171         }
2172
2173         ret = pxafb_set_par(&fbi->fb);
2174         if (ret) {
2175                 dev_err(&dev->dev, "Failed to set parameters\n");
2176                 goto failed_free_irq;
2177         }
2178
2179         platform_set_drvdata(dev, fbi);
2180
2181         ret = register_framebuffer(&fbi->fb);
2182         if (ret < 0) {
2183                 dev_err(&dev->dev,
2184                         "Failed to register framebuffer device: %d\n", ret);
2185                 goto failed_free_cmap;
2186         }
2187
2188         pxafb_overlay_init(fbi);
2189
2190 #ifdef CONFIG_CPU_FREQ
2191         fbi->freq_transition.notifier_call = pxafb_freq_transition;
2192         fbi->freq_policy.notifier_call = pxafb_freq_policy;
2193         cpufreq_register_notifier(&fbi->freq_transition,
2194                                 CPUFREQ_TRANSITION_NOTIFIER);
2195         cpufreq_register_notifier(&fbi->freq_policy,
2196                                 CPUFREQ_POLICY_NOTIFIER);
2197 #endif
2198
2199         /*
2200          * Ok, now enable the LCD controller
2201          */
2202         set_ctrlr_state(fbi, C_ENABLE);
2203
2204         return 0;
2205
2206 failed_free_cmap:
2207         if (fbi->fb.cmap.len)
2208                 fb_dealloc_cmap(&fbi->fb.cmap);
2209 failed_free_irq:
2210         free_irq(irq, fbi);
2211 failed_free_mem:
2212         free_pages_exact(fbi->video_mem, fbi->video_mem_size);
2213 failed_free_dma:
2214         dma_free_coherent(&dev->dev, fbi->dma_buff_size,
2215                         fbi->dma_buff, fbi->dma_buff_phys);
2216 failed_free_io:
2217         iounmap(fbi->mmio_base);
2218 failed_free_res:
2219         release_mem_region(r->start, resource_size(r));
2220 failed_fbi:
2221         clk_put(fbi->clk);
2222         platform_set_drvdata(dev, NULL);
2223         kfree(fbi);
2224 failed:
2225         return ret;
2226 }
2227
2228 static int __devexit pxafb_remove(struct platform_device *dev)
2229 {
2230         struct pxafb_info *fbi = platform_get_drvdata(dev);
2231         struct resource *r;
2232         int irq;
2233         struct fb_info *info;
2234
2235         if (!fbi)
2236                 return 0;
2237
2238         info = &fbi->fb;
2239
2240         pxafb_overlay_exit(fbi);
2241         unregister_framebuffer(info);
2242
2243         pxafb_disable_controller(fbi);
2244
2245         if (fbi->fb.cmap.len)
2246                 fb_dealloc_cmap(&fbi->fb.cmap);
2247
2248         irq = platform_get_irq(dev, 0);
2249         free_irq(irq, fbi);
2250
2251         free_pages_exact(fbi->video_mem, fbi->video_mem_size);
2252
2253         dma_free_writecombine(&dev->dev, fbi->dma_buff_size,
2254                         fbi->dma_buff, fbi->dma_buff_phys);
2255
2256         iounmap(fbi->mmio_base);
2257
2258         r = platform_get_resource(dev, IORESOURCE_MEM, 0);
2259         release_mem_region(r->start, resource_size(r));
2260
2261         clk_put(fbi->clk);
2262         kfree(fbi);
2263
2264         return 0;
2265 }
2266
2267 static struct platform_driver pxafb_driver = {
2268         .probe          = pxafb_probe,
2269         .remove         = __devexit_p(pxafb_remove),
2270         .driver         = {
2271                 .owner  = THIS_MODULE,
2272                 .name   = "pxa2xx-fb",
2273 #ifdef CONFIG_PM
2274                 .pm     = &pxafb_pm_ops,
2275 #endif
2276         },
2277 };
2278
2279 static int __init pxafb_init(void)
2280 {
2281         if (pxafb_setup_options())
2282                 return -EINVAL;
2283
2284         return platform_driver_register(&pxafb_driver);
2285 }
2286
2287 static void __exit pxafb_exit(void)
2288 {
2289         platform_driver_unregister(&pxafb_driver);
2290 }
2291
2292 module_init(pxafb_init);
2293 module_exit(pxafb_exit);
2294
2295 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
2296 MODULE_LICENSE("GPL");