1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mb862xx/mb862xxfb.c
5 * Fujitsu Carmine/Coral-P(A)/Lime framebuffer driver
7 * (C) 2008 Anatolij Gustschin <agust@denx.de>
8 * DENX Software Engineering
14 #include <linux/delay.h>
15 #include <linux/uaccess.h>
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/pci.h>
20 #if defined(CONFIG_OF)
21 #include <linux/of_platform.h>
23 #include "mb862xxfb.h"
24 #include "mb862xx_reg.h"
26 #define NR_PALETTE 256
27 #define MB862XX_MEM_SIZE 0x1000000
28 #define CORALP_MEM_SIZE 0x2000000
29 #define CARMINE_MEM_SIZE 0x8000000
30 #define DRV_NAME "mb862xxfb"
32 #if defined(CONFIG_SOCRATES)
33 static struct mb862xx_gc_mode socrates_gc_mode = {
34 /* Mode for Prime View PM070WL4 TFT LCD Panel */
35 { "800x480", 45, 800, 480, 40000, 86, 42, 33, 10, 128, 2, 0, 0, 0 },
36 /* 16 bits/pixel, 16MB, 133MHz, SDRAM memory mode value */
37 16, 0x1000000, GC_CCF_COT_133, 0x4157ba63
42 static inline int h_total(struct fb_var_screeninfo *var)
44 return var->xres + var->left_margin +
45 var->right_margin + var->hsync_len;
48 static inline int v_total(struct fb_var_screeninfo *var)
50 return var->yres + var->upper_margin +
51 var->lower_margin + var->vsync_len;
54 static inline int hsp(struct fb_var_screeninfo *var)
56 return var->xres + var->right_margin - 1;
59 static inline int vsp(struct fb_var_screeninfo *var)
61 return var->yres + var->lower_margin - 1;
64 static inline int d_pitch(struct fb_var_screeninfo *var)
66 return var->xres * var->bits_per_pixel / 8;
69 static inline unsigned int chan_to_field(unsigned int chan,
70 struct fb_bitfield *bf)
73 chan >>= 16 - bf->length;
74 return chan << bf->offset;
77 static int mb862xxfb_setcolreg(unsigned regno,
78 unsigned red, unsigned green, unsigned blue,
79 unsigned transp, struct fb_info *info)
81 struct mb862xxfb_par *par = info->par;
84 switch (info->fix.visual) {
85 case FB_VISUAL_TRUECOLOR:
87 val = chan_to_field(red, &info->var.red);
88 val |= chan_to_field(green, &info->var.green);
89 val |= chan_to_field(blue, &info->var.blue);
90 par->pseudo_palette[regno] = val;
93 case FB_VISUAL_PSEUDOCOLOR:
95 val = (red >> 8) << 16;
96 val |= (green >> 8) << 8;
98 outreg(disp, GC_L0PAL0 + (regno * 4), val);
102 return 1; /* unsupported type */
107 static int mb862xxfb_check_var(struct fb_var_screeninfo *var,
113 dev_dbg(fbi->dev, "%s\n", __func__);
115 /* check if these values fit into the registers */
116 if (var->hsync_len > 255 || var->vsync_len > 255)
119 if ((var->xres + var->right_margin) >= 4096)
122 if ((var->yres + var->lower_margin) > 4096)
125 if (h_total(var) > 4096 || v_total(var) > 4096)
128 if (var->xres_virtual > 4096 || var->yres_virtual > 4096)
131 if (var->bits_per_pixel <= 8)
132 var->bits_per_pixel = 8;
133 else if (var->bits_per_pixel <= 16)
134 var->bits_per_pixel = 16;
135 else if (var->bits_per_pixel <= 32)
136 var->bits_per_pixel = 32;
139 * can cope with 8,16 or 24/32bpp if resulting
140 * pitch is divisible by 64 without remainder
142 if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT) {
145 var->bits_per_pixel = 0;
147 var->bits_per_pixel += 8;
148 r = d_pitch(&fbi->var) % GC_L0M_L0W_UNIT;
149 } while (r && var->bits_per_pixel <= 32);
151 if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT)
155 /* line length is going to be 128 bit aligned */
156 tmp = (var->xres * var->bits_per_pixel) / 8;
160 /* set r/g/b positions and validate bpp */
161 switch (var->bits_per_pixel) {
163 var->red.length = var->bits_per_pixel;
164 var->green.length = var->bits_per_pixel;
165 var->blue.length = var->bits_per_pixel;
167 var->green.offset = 0;
168 var->blue.offset = 0;
169 var->transp.length = 0;
173 var->green.length = 5;
174 var->blue.length = 5;
175 var->red.offset = 10;
176 var->green.offset = 5;
177 var->blue.offset = 0;
178 var->transp.length = 0;
182 var->transp.length = 8;
184 var->green.length = 8;
185 var->blue.length = 8;
186 var->transp.offset = 24;
187 var->red.offset = 16;
188 var->green.offset = 8;
189 var->blue.offset = 0;
198 * set display parameters
200 static int mb862xxfb_set_par(struct fb_info *fbi)
202 struct mb862xxfb_par *par = fbi->par;
203 unsigned long reg, sc;
205 dev_dbg(par->dev, "%s\n", __func__);
206 if (par->type == BT_CORALP)
207 mb862xxfb_init_accel(fbi, fbi->var.xres);
213 reg = inreg(disp, GC_DCM1);
214 reg &= ~GC_DCM01_DEN;
215 outreg(disp, GC_DCM1, reg);
217 /* set display reference clock div. */
218 sc = par->refclk / (1000000 / fbi->var.pixclock) - 1;
219 reg = inreg(disp, GC_DCM1);
220 reg &= ~(GC_DCM01_CKS | GC_DCM01_RESV | GC_DCM01_SC);
222 outreg(disp, GC_DCM1, reg);
223 dev_dbg(par->dev, "SC 0x%lx\n", sc);
225 /* disp dimension, format */
226 reg = pack(d_pitch(&fbi->var) / GC_L0M_L0W_UNIT,
227 (fbi->var.yres - 1));
228 if (fbi->var.bits_per_pixel == 16)
229 reg |= GC_L0M_L0C_16;
230 outreg(disp, GC_L0M, reg);
232 if (fbi->var.bits_per_pixel == 32) {
233 reg = inreg(disp, GC_L0EM);
234 outreg(disp, GC_L0EM, reg | GC_L0EM_L0EC_24);
236 outreg(disp, GC_WY_WX, 0);
237 reg = pack(fbi->var.yres - 1, fbi->var.xres);
238 outreg(disp, GC_WH_WW, reg);
239 outreg(disp, GC_L0OA0, 0);
240 outreg(disp, GC_L0DA0, 0);
241 outreg(disp, GC_L0DY_L0DX, 0);
242 outreg(disp, GC_L0WY_L0WX, 0);
243 outreg(disp, GC_L0WH_L0WW, reg);
245 /* both HW-cursors off */
246 reg = inreg(disp, GC_CPM_CUTC);
247 reg &= ~(GC_CPM_CEN0 | GC_CPM_CEN1);
248 outreg(disp, GC_CPM_CUTC, reg);
251 reg = pack(fbi->var.xres - 1, fbi->var.xres - 1);
252 outreg(disp, GC_HDB_HDP, reg);
253 reg = pack((fbi->var.yres - 1), vsp(&fbi->var));
254 outreg(disp, GC_VDP_VSP, reg);
255 reg = ((fbi->var.vsync_len - 1) << 24) |
256 pack((fbi->var.hsync_len - 1), hsp(&fbi->var));
257 outreg(disp, GC_VSW_HSW_HSP, reg);
258 outreg(disp, GC_HTP, pack(h_total(&fbi->var) - 1, 0));
259 outreg(disp, GC_VTR, pack(v_total(&fbi->var) - 1, 0));
262 reg = inreg(disp, GC_DCM1);
263 reg |= GC_DCM01_DEN | GC_DCM01_L0E;
264 reg &= ~GC_DCM01_ESY;
265 outreg(disp, GC_DCM1, reg);
269 static int mb862xxfb_pan(struct fb_var_screeninfo *var,
270 struct fb_info *info)
272 struct mb862xxfb_par *par = info->par;
275 reg = pack(var->yoffset, var->xoffset);
276 outreg(disp, GC_L0WY_L0WX, reg);
278 reg = pack(info->var.yres_virtual, info->var.xres_virtual);
279 outreg(disp, GC_L0WH_L0WW, reg);
283 static int mb862xxfb_blank(int mode, struct fb_info *fbi)
285 struct mb862xxfb_par *par = fbi->par;
288 dev_dbg(fbi->dev, "blank mode=%d\n", mode);
291 case FB_BLANK_POWERDOWN:
292 reg = inreg(disp, GC_DCM1);
293 reg &= ~GC_DCM01_DEN;
294 outreg(disp, GC_DCM1, reg);
296 case FB_BLANK_UNBLANK:
297 reg = inreg(disp, GC_DCM1);
299 outreg(disp, GC_DCM1, reg);
301 case FB_BLANK_NORMAL:
302 case FB_BLANK_VSYNC_SUSPEND:
303 case FB_BLANK_HSYNC_SUSPEND:
310 static int mb862xxfb_ioctl(struct fb_info *fbi, unsigned int cmd,
313 struct mb862xxfb_par *par = fbi->par;
314 struct mb862xx_l1_cfg *l1_cfg = &par->l1_cfg;
315 void __user *argp = (void __user *)arg;
320 case MB862XX_L1_GET_CFG:
321 if (copy_to_user(argp, l1_cfg, sizeof(*l1_cfg)))
324 case MB862XX_L1_SET_CFG:
325 if (copy_from_user(l1_cfg, argp, sizeof(*l1_cfg)))
327 if (l1_cfg->dh == 0 || l1_cfg->dw == 0)
329 if ((l1_cfg->sw >= l1_cfg->dw) && (l1_cfg->sh >= l1_cfg->dh)) {
331 outreg(cap, GC_CAP_CSC,
332 pack((l1_cfg->sh << 11) / l1_cfg->dh,
333 (l1_cfg->sw << 11) / l1_cfg->dw));
334 l1em = inreg(disp, GC_L1EM);
336 } else if ((l1_cfg->sw <= l1_cfg->dw) &&
337 (l1_cfg->sh <= l1_cfg->dh)) {
339 outreg(cap, GC_CAP_CSC,
340 pack((l1_cfg->sh << 11) / l1_cfg->dh,
341 (l1_cfg->sw << 11) / l1_cfg->dw));
342 outreg(cap, GC_CAP_CMSS,
343 pack(l1_cfg->sw >> 1, l1_cfg->sh));
344 outreg(cap, GC_CAP_CMDS,
345 pack(l1_cfg->dw >> 1, l1_cfg->dh));
346 l1em = inreg(disp, GC_L1EM);
350 if (l1_cfg->mirror) {
351 outreg(cap, GC_CAP_CBM,
352 inreg(cap, GC_CAP_CBM) | GC_CBM_HRV);
353 l1em |= l1_cfg->dw * 2 - 8;
355 outreg(cap, GC_CAP_CBM,
356 inreg(cap, GC_CAP_CBM) & ~GC_CBM_HRV);
359 outreg(disp, GC_L1EM, l1em);
361 case MB862XX_L1_ENABLE:
364 outreg(disp, GC_L1DA, par->cap_buf);
365 outreg(cap, GC_CAP_IMG_START,
366 pack(l1_cfg->sy >> 1, l1_cfg->sx));
367 outreg(cap, GC_CAP_IMG_END,
368 pack(l1_cfg->sh, l1_cfg->sw));
369 outreg(disp, GC_L1M, GC_L1M_16 | GC_L1M_YC | GC_L1M_CS |
370 (par->l1_stride << 16));
371 outreg(disp, GC_L1WY_L1WX,
372 pack(l1_cfg->dy, l1_cfg->dx));
373 outreg(disp, GC_L1WH_L1WW,
374 pack(l1_cfg->dh - 1, l1_cfg->dw));
375 outreg(disp, GC_DLS, 1);
376 outreg(cap, GC_CAP_VCM,
377 GC_VCM_VIE | GC_VCM_CM | GC_VCM_VS_PAL);
378 outreg(disp, GC_DCM1, inreg(disp, GC_DCM1) |
379 GC_DCM1_DEN | GC_DCM1_L1E);
381 outreg(cap, GC_CAP_VCM,
382 inreg(cap, GC_CAP_VCM) & ~GC_VCM_VIE);
383 outreg(disp, GC_DCM1,
384 inreg(disp, GC_DCM1) & ~GC_DCM1_L1E);
387 case MB862XX_L1_CAP_CTL:
390 outreg(cap, GC_CAP_VCM,
391 inreg(cap, GC_CAP_VCM) | GC_VCM_VIE);
393 outreg(cap, GC_CAP_VCM,
394 inreg(cap, GC_CAP_VCM) & ~GC_VCM_VIE);
403 /* framebuffer ops */
404 static struct fb_ops mb862xxfb_ops = {
405 .owner = THIS_MODULE,
406 .fb_check_var = mb862xxfb_check_var,
407 .fb_set_par = mb862xxfb_set_par,
408 .fb_setcolreg = mb862xxfb_setcolreg,
409 .fb_blank = mb862xxfb_blank,
410 .fb_pan_display = mb862xxfb_pan,
411 .fb_fillrect = cfb_fillrect,
412 .fb_copyarea = cfb_copyarea,
413 .fb_imageblit = cfb_imageblit,
414 .fb_ioctl = mb862xxfb_ioctl,
417 /* initialize fb_info data */
418 static int mb862xxfb_init_fbinfo(struct fb_info *fbi)
420 struct mb862xxfb_par *par = fbi->par;
421 struct mb862xx_gc_mode *mode = par->gc_mode;
425 fbi->fbops = &mb862xxfb_ops;
426 fbi->pseudo_palette = par->pseudo_palette;
427 fbi->screen_base = par->fb_base;
428 fbi->screen_size = par->mapped_vram;
430 strcpy(fbi->fix.id, DRV_NAME);
431 fbi->fix.smem_start = (unsigned long)par->fb_base_phys;
432 fbi->fix.mmio_start = (unsigned long)par->mmio_base_phys;
433 fbi->fix.mmio_len = par->mmio_len;
434 fbi->fix.accel = FB_ACCEL_NONE;
435 fbi->fix.type = FB_TYPE_PACKED_PIXELS;
436 fbi->fix.type_aux = 0;
437 fbi->fix.xpanstep = 1;
438 fbi->fix.ypanstep = 1;
439 fbi->fix.ywrapstep = 0;
441 reg = inreg(disp, GC_DCM1);
442 if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E) {
443 /* get the disp mode from active display cfg */
444 unsigned long sc = ((reg & GC_DCM01_SC) >> 8) + 1;
445 unsigned long hsp, vsp, ht, vt;
447 dev_dbg(par->dev, "using bootloader's disp. mode\n");
448 fbi->var.pixclock = (sc * 1000000) / par->refclk;
449 fbi->var.xres = (inreg(disp, GC_HDB_HDP) & 0x0fff) + 1;
450 reg = inreg(disp, GC_VDP_VSP);
451 fbi->var.yres = ((reg >> 16) & 0x0fff) + 1;
452 vsp = (reg & 0x0fff) + 1;
453 fbi->var.xres_virtual = fbi->var.xres;
454 fbi->var.yres_virtual = fbi->var.yres;
455 reg = inreg(disp, GC_L0EM);
456 if (reg & GC_L0EM_L0EC_24) {
457 fbi->var.bits_per_pixel = 32;
459 reg = inreg(disp, GC_L0M);
460 if (reg & GC_L0M_L0C_16)
461 fbi->var.bits_per_pixel = 16;
463 fbi->var.bits_per_pixel = 8;
465 reg = inreg(disp, GC_VSW_HSW_HSP);
466 fbi->var.hsync_len = ((reg & 0xff0000) >> 16) + 1;
467 fbi->var.vsync_len = ((reg & 0x3f000000) >> 24) + 1;
468 hsp = (reg & 0xffff) + 1;
469 ht = ((inreg(disp, GC_HTP) & 0xfff0000) >> 16) + 1;
470 fbi->var.right_margin = hsp - fbi->var.xres;
471 fbi->var.left_margin = ht - hsp - fbi->var.hsync_len;
472 vt = ((inreg(disp, GC_VTR) & 0xfff0000) >> 16) + 1;
473 fbi->var.lower_margin = vsp - fbi->var.yres;
474 fbi->var.upper_margin = vt - vsp - fbi->var.vsync_len;
476 dev_dbg(par->dev, "using supplied mode\n");
477 fb_videomode_to_var(&fbi->var, (struct fb_videomode *)mode);
478 fbi->var.bits_per_pixel = mode->def_bpp ? mode->def_bpp : 8;
482 ret = fb_find_mode(&fbi->var, fbi, "640x480-16@60",
484 if (ret == 0 || ret == 4) {
486 "failed to get initial mode\n");
491 fbi->var.xoffset = 0;
492 fbi->var.yoffset = 0;
493 fbi->var.grayscale = 0;
495 fbi->var.height = -1;
497 fbi->var.accel_flags = 0;
498 fbi->var.vmode = FB_VMODE_NONINTERLACED;
499 fbi->var.activate = FB_ACTIVATE_NOW;
500 fbi->flags = FBINFO_DEFAULT |
502 FBINFO_FOREIGN_ENDIAN |
504 FBINFO_HWACCEL_XPAN |
507 /* check and possibly fix bpp */
508 if ((fbi->fbops->fb_check_var)(&fbi->var, fbi))
509 dev_err(par->dev, "check_var() failed on initial setup?\n");
511 fbi->fix.visual = fbi->var.bits_per_pixel == 8 ?
512 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
513 fbi->fix.line_length = (fbi->var.xres_virtual *
514 fbi->var.bits_per_pixel) / 8;
515 fbi->fix.smem_len = fbi->fix.line_length * fbi->var.yres_virtual;
518 * reserve space for capture buffers and two cursors
519 * at the end of vram: 720x576 * 2 * 2.2 + 64x64 * 16.
521 par->cap_buf = par->mapped_vram - 0x1bd800 - 0x10000;
522 par->cap_len = 0x1bd800;
525 par->l1_cfg.sw = 720;
526 par->l1_cfg.sh = 576;
529 par->l1_cfg.dw = 720;
530 par->l1_cfg.dh = 576;
531 stride = par->l1_cfg.sw * (fbi->var.bits_per_pixel / 8);
532 par->l1_stride = stride / 64 + ((stride % 64) ? 1 : 0);
533 outreg(cap, GC_CAP_CBM, GC_CBM_OO | GC_CBM_CBST |
534 (par->l1_stride << 16));
535 outreg(cap, GC_CAP_CBOA, par->cap_buf);
536 outreg(cap, GC_CAP_CBLA, par->cap_buf + par->cap_len);
541 * show some display controller and cursor registers
543 static ssize_t mb862xxfb_show_dispregs(struct device *dev,
544 struct device_attribute *attr, char *buf)
546 struct fb_info *fbi = dev_get_drvdata(dev);
547 struct mb862xxfb_par *par = fbi->par;
551 for (reg = GC_DCM0; reg <= GC_L0DY_L0DX; reg += 4)
552 ptr += sprintf(ptr, "%08x = %08x\n",
553 reg, inreg(disp, reg));
555 for (reg = GC_CPM_CUTC; reg <= GC_CUY1_CUX1; reg += 4)
556 ptr += sprintf(ptr, "%08x = %08x\n",
557 reg, inreg(disp, reg));
559 for (reg = GC_DCM1; reg <= GC_L0WH_L0WW; reg += 4)
560 ptr += sprintf(ptr, "%08x = %08x\n",
561 reg, inreg(disp, reg));
563 for (reg = 0x400; reg <= 0x410; reg += 4)
564 ptr += sprintf(ptr, "geo %08x = %08x\n",
565 reg, inreg(geo, reg));
567 for (reg = 0x400; reg <= 0x410; reg += 4)
568 ptr += sprintf(ptr, "draw %08x = %08x\n",
569 reg, inreg(draw, reg));
571 for (reg = 0x440; reg <= 0x450; reg += 4)
572 ptr += sprintf(ptr, "draw %08x = %08x\n",
573 reg, inreg(draw, reg));
578 static DEVICE_ATTR(dispregs, 0444, mb862xxfb_show_dispregs, NULL);
580 static irqreturn_t mb862xx_intr(int irq, void *dev_id)
582 struct mb862xxfb_par *par = (struct mb862xxfb_par *) dev_id;
583 unsigned long reg_ist, mask;
588 if (par->type == BT_CARMINE) {
589 /* Get Interrupt Status */
590 reg_ist = inreg(ctrl, GC_CTRL_STATUS);
591 mask = inreg(ctrl, GC_CTRL_INT_MASK);
599 /* Clear interrupt status */
600 outreg(ctrl, 0x0, reg_ist);
603 reg_ist = inreg(host, GC_IST);
604 mask = inreg(host, GC_IMASK);
611 outreg(host, GC_IST, ~reg_ist);
616 #if defined(CONFIG_FB_MB862XX_LIME)
618 * GDC (Lime, Coral(B/Q), Mint, ...) on host bus
620 static int mb862xx_gdc_init(struct mb862xxfb_par *par)
622 unsigned long ccf, mmr;
623 unsigned long ver, rev;
628 #if defined(CONFIG_FB_PRE_INIT_FB)
631 par->host = par->mmio_base;
632 par->i2c = par->mmio_base + MB862XX_I2C_BASE;
633 par->disp = par->mmio_base + MB862XX_DISP_BASE;
634 par->cap = par->mmio_base + MB862XX_CAP_BASE;
635 par->draw = par->mmio_base + MB862XX_DRAW_BASE;
636 par->geo = par->mmio_base + MB862XX_GEO_BASE;
637 par->pio = par->mmio_base + MB862XX_PIO_BASE;
639 par->refclk = GC_DISP_REFCLK_400;
641 ver = inreg(host, GC_CID);
642 rev = inreg(pio, GC_REVISION);
643 if ((ver == 0x303) && (rev & 0xffffff00) == 0x20050100) {
644 dev_info(par->dev, "Fujitsu Lime v1.%d found\n",
647 ccf = par->gc_mode ? par->gc_mode->ccf : GC_CCF_COT_100;
648 mmr = par->gc_mode ? par->gc_mode->mmr : 0x414fb7f2;
650 dev_info(par->dev, "? GDC, CID/Rev.: 0x%lx/0x%lx \n", ver, rev);
654 if (!par->pre_init) {
655 outreg(host, GC_CCF, ccf);
657 outreg(host, GC_MMR, mmr);
661 /* interrupt status */
662 outreg(host, GC_IST, 0);
663 outreg(host, GC_IMASK, GC_INT_EN);
667 static int of_platform_mb862xx_probe(struct platform_device *ofdev)
669 struct device_node *np = ofdev->dev.of_node;
670 struct device *dev = &ofdev->dev;
671 struct mb862xxfb_par *par;
672 struct fb_info *info;
674 resource_size_t res_size;
675 unsigned long ret = -ENODEV;
677 if (of_address_to_resource(np, 0, &res)) {
678 dev_err(dev, "Invalid address\n");
682 info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
684 dev_err(dev, "cannot allocate framebuffer\n");
692 par->irq = irq_of_parse_and_map(np, 0);
693 if (par->irq == NO_IRQ) {
694 dev_err(dev, "failed to map irq\n");
699 res_size = resource_size(&res);
700 par->res = request_mem_region(res.start, res_size, DRV_NAME);
701 if (par->res == NULL) {
702 dev_err(dev, "Cannot claim framebuffer/mmio\n");
707 #if defined(CONFIG_SOCRATES)
708 par->gc_mode = &socrates_gc_mode;
711 par->fb_base_phys = res.start;
712 par->mmio_base_phys = res.start + MB862XX_MMIO_BASE;
713 par->mmio_len = MB862XX_MMIO_SIZE;
715 par->mapped_vram = par->gc_mode->max_vram;
717 par->mapped_vram = MB862XX_MEM_SIZE;
719 par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
720 if (par->fb_base == NULL) {
721 dev_err(dev, "Cannot map framebuffer\n");
725 par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
726 if (par->mmio_base == NULL) {
727 dev_err(dev, "Cannot map registers\n");
731 dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
732 (u64)par->fb_base_phys, (ulong)par->mapped_vram);
733 dev_dbg(dev, "mmio phys 0x%llx 0x%lx, (irq = %d)\n",
734 (u64)par->mmio_base_phys, (ulong)par->mmio_len, par->irq);
736 if (mb862xx_gdc_init(par))
739 if (request_irq(par->irq, mb862xx_intr, 0,
740 DRV_NAME, (void *)par)) {
741 dev_err(dev, "Cannot request irq\n");
745 mb862xxfb_init_fbinfo(info);
747 if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
748 dev_err(dev, "Could not allocate cmap for fb_info.\n");
752 if ((info->fbops->fb_set_par)(info))
753 dev_err(dev, "set_var() failed on initial setup?\n");
755 if (register_framebuffer(info)) {
756 dev_err(dev, "failed to register framebuffer\n");
760 dev_set_drvdata(dev, info);
762 if (device_create_file(dev, &dev_attr_dispregs))
763 dev_err(dev, "Can't create sysfs regdump file\n");
767 fb_dealloc_cmap(&info->cmap);
769 outreg(host, GC_IMASK, 0);
770 free_irq(par->irq, (void *)par);
772 iounmap(par->mmio_base);
774 iounmap(par->fb_base);
776 release_mem_region(res.start, res_size);
778 irq_dispose_mapping(par->irq);
780 framebuffer_release(info);
784 static int of_platform_mb862xx_remove(struct platform_device *ofdev)
786 struct fb_info *fbi = dev_get_drvdata(&ofdev->dev);
787 struct mb862xxfb_par *par = fbi->par;
788 resource_size_t res_size = resource_size(par->res);
791 dev_dbg(fbi->dev, "%s release\n", fbi->fix.id);
794 reg = inreg(disp, GC_DCM1);
795 reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
796 outreg(disp, GC_DCM1, reg);
798 /* disable interrupts */
799 outreg(host, GC_IMASK, 0);
801 free_irq(par->irq, (void *)par);
802 irq_dispose_mapping(par->irq);
804 device_remove_file(&ofdev->dev, &dev_attr_dispregs);
806 unregister_framebuffer(fbi);
807 fb_dealloc_cmap(&fbi->cmap);
809 iounmap(par->mmio_base);
810 iounmap(par->fb_base);
812 release_mem_region(par->res->start, res_size);
813 framebuffer_release(fbi);
820 static struct of_device_id of_platform_mb862xx_tbl[] = {
821 { .compatible = "fujitsu,MB86276", },
822 { .compatible = "fujitsu,lime", },
823 { .compatible = "fujitsu,MB86277", },
824 { .compatible = "fujitsu,mint", },
825 { .compatible = "fujitsu,MB86293", },
826 { .compatible = "fujitsu,MB86294", },
827 { .compatible = "fujitsu,coral", },
830 MODULE_DEVICE_TABLE(of, of_platform_mb862xx_tbl);
832 static struct platform_driver of_platform_mb862xxfb_driver = {
835 .of_match_table = of_platform_mb862xx_tbl,
837 .probe = of_platform_mb862xx_probe,
838 .remove = of_platform_mb862xx_remove,
842 #if defined(CONFIG_FB_MB862XX_PCI_GDC)
843 static int coralp_init(struct mb862xxfb_par *par)
847 par->host = par->mmio_base;
848 par->i2c = par->mmio_base + MB862XX_I2C_BASE;
849 par->disp = par->mmio_base + MB862XX_DISP_BASE;
850 par->cap = par->mmio_base + MB862XX_CAP_BASE;
851 par->draw = par->mmio_base + MB862XX_DRAW_BASE;
852 par->geo = par->mmio_base + MB862XX_GEO_BASE;
853 par->pio = par->mmio_base + MB862XX_PIO_BASE;
855 par->refclk = GC_DISP_REFCLK_400;
857 if (par->mapped_vram >= 0x2000000) {
858 /* relocate gdc registers space */
859 writel(1, par->fb_base + MB862XX_MMIO_BASE + GC_RSW);
860 udelay(1); /* wait at least 20 bus cycles */
863 ver = inreg(host, GC_CID);
864 cn = (ver & GC_CID_CNAME_MSK) >> 8;
865 ver = ver & GC_CID_VERSION_MSK;
869 dev_info(par->dev, "Fujitsu Coral-%s GDC Rev.%d found\n",\
870 (ver == 6) ? "P" : (ver == 8) ? "PA" : "?",
871 par->pdev->revision);
872 reg = inreg(disp, GC_DCM1);
873 if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E)
876 if (!par->pre_init) {
877 outreg(host, GC_CCF, GC_CCF_CGE_166 | GC_CCF_COT_133);
879 outreg(host, GC_MMR, GC_MMR_CORALP_EVB_VAL);
882 /* Clear interrupt status */
883 outreg(host, GC_IST, 0);
888 mb862xx_i2c_init(par);
892 static int init_dram_ctrl(struct mb862xxfb_par *par)
897 * Set io mode first! Spec. says IC may be destroyed
898 * if not set to SSTL2/LVCMOS before init.
900 outreg(dram_ctrl, GC_DCTL_IOCONT1_IOCONT0, GC_EVB_DCTL_IOCONT1_IOCONT0);
903 outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD);
904 outreg(dram_ctrl, GC_DCTL_SETTIME1_EMODE, GC_EVB_DCTL_SETTIME1_EMODE);
905 outreg(dram_ctrl, GC_DCTL_REFRESH_SETTIME2,
906 GC_EVB_DCTL_REFRESH_SETTIME2);
907 outreg(dram_ctrl, GC_DCTL_RSV2_RSV1, GC_EVB_DCTL_RSV2_RSV1);
908 outreg(dram_ctrl, GC_DCTL_DDRIF2_DDRIF1, GC_EVB_DCTL_DDRIF2_DDRIF1);
909 outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES);
911 /* DLL reset done? */
912 while ((inreg(dram_ctrl, GC_DCTL_RSV0_STATES) & GC_DCTL_STATES_MSK)) {
913 udelay(GC_DCTL_INIT_WAIT_INTERVAL);
914 if (i++ > GC_DCTL_INIT_WAIT_CNT) {
915 dev_err(par->dev, "VRAM init failed.\n");
919 outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD_AFT_RST);
920 outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES_AFT_RST);
924 static int carmine_init(struct mb862xxfb_par *par)
928 par->ctrl = par->mmio_base + MB86297_CTRL_BASE;
929 par->i2c = par->mmio_base + MB86297_I2C_BASE;
930 par->disp = par->mmio_base + MB86297_DISP0_BASE;
931 par->disp1 = par->mmio_base + MB86297_DISP1_BASE;
932 par->cap = par->mmio_base + MB86297_CAP0_BASE;
933 par->cap1 = par->mmio_base + MB86297_CAP1_BASE;
934 par->draw = par->mmio_base + MB86297_DRAW_BASE;
935 par->dram_ctrl = par->mmio_base + MB86297_DRAMCTRL_BASE;
936 par->wrback = par->mmio_base + MB86297_WRBACK_BASE;
938 par->refclk = GC_DISP_REFCLK_533;
941 reg = GC_CTRL_CLK_EN_DRAM | GC_CTRL_CLK_EN_2D3D | GC_CTRL_CLK_EN_DISP0;
942 outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
944 /* check for engine module revision */
945 if (inreg(draw, GC_2D3D_REV) == GC_RE_REVISION)
946 dev_info(par->dev, "Fujitsu Carmine GDC Rev.%d found\n",
947 par->pdev->revision);
951 reg &= ~GC_CTRL_CLK_EN_2D3D;
952 outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
955 if (init_dram_ctrl(par) < 0)
958 outreg(ctrl, GC_CTRL_INT_MASK, 0);
962 outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
966 static inline int mb862xx_pci_gdc_init(struct mb862xxfb_par *par)
970 return coralp_init(par);
972 return carmine_init(par);
978 #define CHIP_ID(id) \
979 { PCI_DEVICE(PCI_VENDOR_ID_FUJITSU_LIMITED, id) }
981 static const struct pci_device_id mb862xx_pci_tbl[] = {
982 /* MB86295/MB86296 */
983 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALP),
984 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALPA),
986 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CARMINE),
990 MODULE_DEVICE_TABLE(pci, mb862xx_pci_tbl);
992 static int mb862xx_pci_probe(struct pci_dev *pdev,
993 const struct pci_device_id *ent)
995 struct mb862xxfb_par *par;
996 struct fb_info *info;
997 struct device *dev = &pdev->dev;
1000 ret = pci_enable_device(pdev);
1002 dev_err(dev, "Cannot enable PCI device\n");
1006 info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
1008 dev_err(dev, "framebuffer alloc failed\n");
1017 par->irq = pdev->irq;
1019 ret = pci_request_regions(pdev, DRV_NAME);
1021 dev_err(dev, "Cannot reserve region(s) for PCI device\n");
1025 switch (pdev->device) {
1026 case PCI_DEVICE_ID_FUJITSU_CORALP:
1027 case PCI_DEVICE_ID_FUJITSU_CORALPA:
1028 par->fb_base_phys = pci_resource_start(par->pdev, 0);
1029 par->mapped_vram = CORALP_MEM_SIZE;
1030 if (par->mapped_vram >= 0x2000000) {
1031 par->mmio_base_phys = par->fb_base_phys +
1032 MB862XX_MMIO_HIGH_BASE;
1034 par->mmio_base_phys = par->fb_base_phys +
1037 par->mmio_len = MB862XX_MMIO_SIZE;
1038 par->type = BT_CORALP;
1040 case PCI_DEVICE_ID_FUJITSU_CARMINE:
1041 par->fb_base_phys = pci_resource_start(par->pdev, 2);
1042 par->mmio_base_phys = pci_resource_start(par->pdev, 3);
1043 par->mmio_len = pci_resource_len(par->pdev, 3);
1044 par->mapped_vram = CARMINE_MEM_SIZE;
1045 par->type = BT_CARMINE;
1048 /* should never occur */
1053 par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
1054 if (par->fb_base == NULL) {
1055 dev_err(dev, "Cannot map framebuffer\n");
1060 par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
1061 if (par->mmio_base == NULL) {
1062 dev_err(dev, "Cannot map registers\n");
1067 dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
1068 (unsigned long long)par->fb_base_phys, (ulong)par->mapped_vram);
1069 dev_dbg(dev, "mmio phys 0x%llx 0x%lx\n",
1070 (unsigned long long)par->mmio_base_phys, (ulong)par->mmio_len);
1072 ret = mb862xx_pci_gdc_init(par);
1076 ret = request_irq(par->irq, mb862xx_intr, IRQF_SHARED,
1077 DRV_NAME, (void *)par);
1079 dev_err(dev, "Cannot request irq\n");
1083 mb862xxfb_init_fbinfo(info);
1085 if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
1086 dev_err(dev, "Could not allocate cmap for fb_info.\n");
1091 if ((info->fbops->fb_set_par)(info))
1092 dev_err(dev, "set_var() failed on initial setup?\n");
1094 ret = register_framebuffer(info);
1096 dev_err(dev, "failed to register framebuffer\n");
1100 pci_set_drvdata(pdev, info);
1102 if (device_create_file(dev, &dev_attr_dispregs))
1103 dev_err(dev, "Can't create sysfs regdump file\n");
1105 if (par->type == BT_CARMINE)
1106 outreg(ctrl, GC_CTRL_INT_MASK, GC_CARMINE_INT_EN);
1108 outreg(host, GC_IMASK, GC_INT_EN);
1113 fb_dealloc_cmap(&info->cmap);
1115 free_irq(par->irq, (void *)par);
1117 iounmap(par->mmio_base);
1119 iounmap(par->fb_base);
1121 pci_release_regions(pdev);
1123 framebuffer_release(info);
1125 pci_disable_device(pdev);
1130 static void mb862xx_pci_remove(struct pci_dev *pdev)
1132 struct fb_info *fbi = pci_get_drvdata(pdev);
1133 struct mb862xxfb_par *par = fbi->par;
1136 dev_dbg(fbi->dev, "%s release\n", fbi->fix.id);
1139 reg = inreg(disp, GC_DCM1);
1140 reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
1141 outreg(disp, GC_DCM1, reg);
1143 if (par->type == BT_CARMINE) {
1144 outreg(ctrl, GC_CTRL_INT_MASK, 0);
1145 outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
1147 outreg(host, GC_IMASK, 0);
1150 mb862xx_i2c_exit(par);
1152 device_remove_file(&pdev->dev, &dev_attr_dispregs);
1154 unregister_framebuffer(fbi);
1155 fb_dealloc_cmap(&fbi->cmap);
1157 free_irq(par->irq, (void *)par);
1158 iounmap(par->mmio_base);
1159 iounmap(par->fb_base);
1161 pci_release_regions(pdev);
1162 framebuffer_release(fbi);
1163 pci_disable_device(pdev);
1166 static struct pci_driver mb862xxfb_pci_driver = {
1168 .id_table = mb862xx_pci_tbl,
1169 .probe = mb862xx_pci_probe,
1170 .remove = mb862xx_pci_remove,
1174 static int mb862xxfb_init(void)
1178 #if defined(CONFIG_FB_MB862XX_LIME)
1179 ret = platform_driver_register(&of_platform_mb862xxfb_driver);
1181 #if defined(CONFIG_FB_MB862XX_PCI_GDC)
1182 ret = pci_register_driver(&mb862xxfb_pci_driver);
1187 static void __exit mb862xxfb_exit(void)
1189 #if defined(CONFIG_FB_MB862XX_LIME)
1190 platform_driver_unregister(&of_platform_mb862xxfb_driver);
1192 #if defined(CONFIG_FB_MB862XX_PCI_GDC)
1193 pci_unregister_driver(&mb862xxfb_pci_driver);
1197 module_init(mb862xxfb_init);
1198 module_exit(mb862xxfb_exit);
1200 MODULE_DESCRIPTION("Fujitsu MB862xx Framebuffer driver");
1201 MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
1202 MODULE_LICENSE("GPL v2");