drivers/usb/dwc3/gadget.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/delay.h>
  13 #include <linux/slab.h>
  14 #include <linux/spinlock.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/list.h>
  20 #include <linux/dma-mapping.h>
  21
  22 #include <linux/usb/ch9.h>
  23 #include <linux/usb/gadget.h>
  24
  25 #include "debug.h"
  26 #include "core.h"
  27 #include "gadget.h"
  28 #include "io.h"
  29
  30 #define DWC3_ALIGN_FRAME(d)     (((d)->frame_number + (d)->interval) \
  31                                         & ~((d)->interval - 1))
  32
  33 /**
  34  * dwc3_gadget_set_test_mode - enables usb2 test modes
  35  * @dwc: pointer to our context structure
  36  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  37  *
  38  * Caller should take care of locking. This function will return 0 on
  39  * success or -EINVAL if wrong Test Selector is passed.
  40  */
  41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  42 {
  43         u32             reg;
  44
  45         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  46         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  47
  48         switch (mode) {
  49         case TEST_J:
  50         case TEST_K:
  51         case TEST_SE0_NAK:
  52         case TEST_PACKET:
  53         case TEST_FORCE_EN:
  54                 reg |= mode << 1;
  55                 break;
  56         default:
  57                 return -EINVAL;
  58         }
  59
  60         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  61
  62         return 0;
  63 }
  64
  65 /**
  66  * dwc3_gadget_get_link_state - gets current state of usb link
  67  * @dwc: pointer to our context structure
  68  *
  69  * Caller should take care of locking. This function will
  70  * return the link state on success (>= 0) or -ETIMEDOUT.
  71  */
  72 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  73 {
  74         u32             reg;
  75
  76         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  77
  78         return DWC3_DSTS_USBLNKST(reg);
  79 }
  80
  81 /**
  82  * dwc3_gadget_set_link_state - sets usb link to a particular state
  83  * @dwc: pointer to our context structure
  84  * @state: the state to put link into
  85  *
  86  * Caller should take care of locking. This function will
  87  * return 0 on success or -ETIMEDOUT.
  88  */
  89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  90 {
  91         int             retries = 10000;
  92         u32             reg;
  93
  94         /*
  95          * Wait until device controller is ready. Only applies to 1.94a and
  96          * later RTL.
  97          */
  98         if (dwc->revision >= DWC3_REVISION_194A) {
  99                 while (--retries) {
 100                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 101                         if (reg & DWC3_DSTS_DCNRD)
 102                                 udelay(5);
 103                         else
 104                                 break;
 105                 }
 106
 107                 if (retries <= 0)
 108                         return -ETIMEDOUT;
 109         }
 110
 111         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 112         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 113
 114         /* set requested state */
 115         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 116         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 117
 118         /*
 119          * The following code is racy when called from dwc3_gadget_wakeup,
 120          * and is not needed, at least on newer versions
 121          */
 122         if (dwc->revision >= DWC3_REVISION_194A)
 123                 return 0;
 124
 125         /* wait for a change in DSTS */
 126         retries = 10000;
 127         while (--retries) {
 128                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 129
 130                 if (DWC3_DSTS_USBLNKST(reg) == state)
 131                         return 0;
 132
 133                 udelay(5);
 134         }
 135
 136         return -ETIMEDOUT;
 137 }
 138
 139 /**
 140  * dwc3_ep_inc_trb - increment a trb index.
 141  * @index: Pointer to the TRB index to increment.
 142  *
 143  * The index should never point to the link TRB. After incrementing,
 144  * if it is point to the link TRB, wrap around to the beginning. The
 145  * link TRB is always at the last TRB entry.
 146  */
 147 static void dwc3_ep_inc_trb(u8 *index)
 148 {
 149         (*index)++;
 150         if (*index == (DWC3_TRB_NUM - 1))
 151                 *index = 0;
 152 }
 153
 154 /**
 155  * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
 156  * @dep: The endpoint whose enqueue pointer we're incrementing
 157  */
 158 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
 159 {
 160         dwc3_ep_inc_trb(&dep->trb_enqueue);
 161 }
 162
 163 /**
 164  * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
 165  * @dep: The endpoint whose enqueue pointer we're incrementing
 166  */
 167 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
 168 {
 169         dwc3_ep_inc_trb(&dep->trb_dequeue);
 170 }
 171
 172 static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
 173                 struct dwc3_request *req, int status)
 174 {
 175         struct dwc3                     *dwc = dep->dwc;
 176
 177         req->started = false;
 178         list_del(&req->list);
 179         req->remaining = 0;
 180
 181         if (req->request.status == -EINPROGRESS)
 182                 req->request.status = status;
 183
 184         if (req->trb)
 185                 usb_gadget_unmap_request_by_dev(dwc->sysdev,
 186                                 &req->request, req->direction);
 187
 188         req->trb = NULL;
 189         trace_dwc3_gadget_giveback(req);
 190
 191         if (dep->number > 1)
 192                 pm_runtime_put(dwc->dev);
 193 }
 194
 195 /**
 196  * dwc3_gadget_giveback - call struct usb_request's ->complete callback
 197  * @dep: The endpoint to whom the request belongs to
 198  * @req: The request we're giving back
 199  * @status: completion code for the request
 200  *
 201  * Must be called with controller's lock held and interrupts disabled. This
 202  * function will unmap @req and call its ->complete() callback to notify upper
 203  * layers that it has completed.
 204  */
 205 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 206                 int status)
 207 {
 208         struct dwc3                     *dwc = dep->dwc;
 209
 210         dwc3_gadget_del_and_unmap_request(dep, req, status);
 211
 212         spin_unlock(&dwc->lock);
 213         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 214         spin_lock(&dwc->lock);
 215 }
 216
 217 /**
 218  * dwc3_send_gadget_generic_command - issue a generic command for the controller
 219  * @dwc: pointer to the controller context
 220  * @cmd: the command to be issued
 221  * @param: command parameter
 222  *
 223  * Caller should take care of locking. Issue @cmd with a given @param to @dwc
 224  * and wait for its completion.
 225  */
 226 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 227 {
 228         u32             timeout = 500;
 229         int             status = 0;
 230         int             ret = 0;
 231         u32             reg;
 232
 233         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 234         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 235
 236         do {
 237                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 238                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 239                         status = DWC3_DGCMD_STATUS(reg);
 240                         if (status)
 241                                 ret = -EINVAL;
 242                         break;
 243                 }
 244         } while (--timeout);
 245
 246         if (!timeout) {
 247                 ret = -ETIMEDOUT;
 248                 status = -ETIMEDOUT;
 249         }
 250
 251         trace_dwc3_gadget_generic_cmd(cmd, param, status);
 252
 253         return ret;
 254 }
 255
 256 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
 257
 258 /**
 259  * dwc3_send_gadget_ep_cmd - issue an endpoint command
 260  * @dep: the endpoint to which the command is going to be issued
 261  * @cmd: the command to be issued
 262  * @params: parameters to the command
 263  *
 264  * Caller should handle locking. This function will issue @cmd with given
 265  * @params to @dep and wait for its completion.
 266  */
 267 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
 268                 struct dwc3_gadget_ep_cmd_params *params)
 269 {
 270         const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
 271         struct dwc3             *dwc = dep->dwc;
 272         u32                     timeout = 1000;
 273         u32                     saved_config = 0;
 274         u32                     reg;
 275
 276         int                     cmd_status = 0;
 277         int                     ret = -EINVAL;
 278
 279         /*
 280          * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
 281          * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
 282          * endpoint command.
 283          *
 284          * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
 285          * settings. Restore them after the command is completed.
 286          *
 287          * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
 288          */
 289         if (dwc->gadget.speed <= USB_SPEED_HIGH) {
 290                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 291                 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
 292                         saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
 293                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 294                 }
 295
 296                 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
 297                         saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
 298                         reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 299                 }
 300
 301                 if (saved_config)
 302                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 303         }
 304
 305         if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
 306                 int             needs_wakeup;
 307
 308                 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
 309                                 dwc->link_state == DWC3_LINK_STATE_U2 ||
 310                                 dwc->link_state == DWC3_LINK_STATE_U3);
 311
 312                 if (unlikely(needs_wakeup)) {
 313                         ret = __dwc3_gadget_wakeup(dwc);
 314                         dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
 315                                         ret);
 316                 }
 317         }
 318
 319         dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
 320         dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
 321         dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
 322
 323         /*
 324          * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
 325          * not relying on XferNotReady, we can make use of a special "No
 326          * Response Update Transfer" command where we should clear both CmdAct
 327          * and CmdIOC bits.
 328          *
 329          * With this, we don't need to wait for command completion and can
 330          * straight away issue further commands to the endpoint.
 331          *
 332          * NOTICE: We're making an assumption that control endpoints will never
 333          * make use of Update Transfer command. This is a safe assumption
 334          * because we can never have more than one request at a time with
 335          * Control Endpoints. If anybody changes that assumption, this chunk
 336          * needs to be updated accordingly.
 337          */
 338         if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
 339                         !usb_endpoint_xfer_isoc(desc))
 340                 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
 341         else
 342                 cmd |= DWC3_DEPCMD_CMDACT;
 343
 344         dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
 345         do {
 346                 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
 347                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 348                         cmd_status = DWC3_DEPCMD_STATUS(reg);
 349
 350                         switch (cmd_status) {
 351                         case 0:
 352                                 ret = 0;
 353                                 break;
 354                         case DEPEVT_TRANSFER_NO_RESOURCE:
 355                                 ret = -EINVAL;
 356                                 break;
 357                         case DEPEVT_TRANSFER_BUS_EXPIRY:
 358                                 /*
 359                                  * SW issues START TRANSFER command to
 360                                  * isochronous ep with future frame interval. If
 361                                  * future interval time has already passed when
 362                                  * core receives the command, it will respond
 363                                  * with an error status of 'Bus Expiry'.
 364                                  *
 365                                  * Instead of always returning -EINVAL, let's
 366                                  * give a hint to the gadget driver that this is
 367                                  * the case by returning -EAGAIN.
 368                                  */
 369                                 ret = -EAGAIN;
 370                                 break;
 371                         default:
 372                                 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
 373                         }
 374
 375                         break;
 376                 }
 377         } while (--timeout);
 378
 379         if (timeout == 0) {
 380                 ret = -ETIMEDOUT;
 381                 cmd_status = -ETIMEDOUT;
 382         }
 383
 384         trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
 385
 386         if (ret == 0) {
 387                 switch (DWC3_DEPCMD_CMD(cmd)) {
 388                 case DWC3_DEPCMD_STARTTRANSFER:
 389                         dep->flags |= DWC3_EP_TRANSFER_STARTED;
 390                         dwc3_gadget_ep_get_transfer_index(dep);
 391                         break;
 392                 case DWC3_DEPCMD_ENDTRANSFER:
 393                         dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
 394                         break;
 395                 default:
 396                         /* nothing */
 397                         break;
 398                 }
 399         }
 400
 401         if (saved_config) {
 402                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 403                 reg |= saved_config;
 404                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 405         }
 406
 407         return ret;
 408 }
 409
 410 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
 411 {
 412         struct dwc3 *dwc = dep->dwc;
 413         struct dwc3_gadget_ep_cmd_params params;
 414         u32 cmd = DWC3_DEPCMD_CLEARSTALL;
 415
 416         /*
 417          * As of core revision 2.60a the recommended programming model
 418          * is to set the ClearPendIN bit when issuing a Clear Stall EP
 419          * command for IN endpoints. This is to prevent an issue where
 420          * some (non-compliant) hosts may not send ACK TPs for pending
 421          * IN transfers due to a mishandled error condition. Synopsys
 422          * STAR 9000614252.
 423          */
 424         if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
 425             (dwc->gadget.speed >= USB_SPEED_SUPER))
 426                 cmd |= DWC3_DEPCMD_CLEARPENDIN;
 427
 428         memset(&params, 0, sizeof(params));
 429
 430         return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 431 }
 432
 433 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 434                 struct dwc3_trb *trb)
 435 {
 436         u32             offset = (char *) trb - (char *) dep->trb_pool;
 437
 438         return dep->trb_pool_dma + offset;
 439 }
 440
 441 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 442 {
 443         struct dwc3             *dwc = dep->dwc;
 444
 445         if (dep->trb_pool)
 446                 return 0;
 447
 448         dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
 449                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 450                         &dep->trb_pool_dma, GFP_KERNEL);
 451         if (!dep->trb_pool) {
 452                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 453                                 dep->name);
 454                 return -ENOMEM;
 455         }
 456
 457         return 0;
 458 }
 459
 460 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 461 {
 462         struct dwc3             *dwc = dep->dwc;
 463
 464         dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 465                         dep->trb_pool, dep->trb_pool_dma);
 466
 467         dep->trb_pool = NULL;
 468         dep->trb_pool_dma = 0;
 469 }
 470
 471 static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
 472 {
 473         struct dwc3_gadget_ep_cmd_params params;
 474
 475         memset(&params, 0x00, sizeof(params));
 476
 477         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 478
 479         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
 480                         &params);
 481 }
 482
 483 /**
 484  * dwc3_gadget_start_config - configure ep resources
 485  * @dep: endpoint that is being enabled
 486  *
 487  * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
 488  * completion, it will set Transfer Resource for all available endpoints.
 489  *
 490  * The assignment of transfer resources cannot perfectly follow the data book
 491  * due to the fact that the controller driver does not have all knowledge of the
 492  * configuration in advance. It is given this information piecemeal by the
 493  * composite gadget framework after every SET_CONFIGURATION and
 494  * SET_INTERFACE. Trying to follow the databook programming model in this
 495  * scenario can cause errors. For two reasons:
 496  *
 497  * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
 498  * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
 499  * incorrect in the scenario of multiple interfaces.
 500  *
 501  * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
 502  * endpoint on alt setting (8.1.6).
 503  *
 504  * The following simplified method is used instead:
 505  *
 506  * All hardware endpoints can be assigned a transfer resource and this setting
 507  * will stay persistent until either a core reset or hibernation. So whenever we
 508  * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
 509  * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
 510  * guaranteed that there are as many transfer resources as endpoints.
 511  *
 512  * This function is called for each endpoint when it is being enabled but is
 513  * triggered only when called for EP0-out, which always happens first, and which
 514  * should only happen in one of the above conditions.
 515  */
 516 static int dwc3_gadget_start_config(struct dwc3_ep *dep)
 517 {
 518         struct dwc3_gadget_ep_cmd_params params;
 519         struct dwc3             *dwc;
 520         u32                     cmd;
 521         int                     i;
 522         int                     ret;
 523
 524         if (dep->number)
 525                 return 0;
 526
 527         memset(&params, 0x00, sizeof(params));
 528         cmd = DWC3_DEPCMD_DEPSTARTCFG;
 529         dwc = dep->dwc;
 530
 531         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 532         if (ret)
 533                 return ret;
 534
 535         for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
 536                 struct dwc3_ep *dep = dwc->eps[i];
 537
 538                 if (!dep)
 539                         continue;
 540
 541                 ret = dwc3_gadget_set_xfer_resource(dep);
 542                 if (ret)
 543                         return ret;
 544         }
 545
 546         return 0;
 547 }
 548
 549 static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
 550 {
 551         const struct usb_ss_ep_comp_descriptor *comp_desc;
 552         const struct usb_endpoint_descriptor *desc;
 553         struct dwc3_gadget_ep_cmd_params params;
 554         struct dwc3 *dwc = dep->dwc;
 555
 556         comp_desc = dep->endpoint.comp_desc;
 557         desc = dep->endpoint.desc;
 558
 559         memset(&params, 0x00, sizeof(params));
 560
 561         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 562                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 563
 564         /* Burst size is only needed in SuperSpeed mode */
 565         if (dwc->gadget.speed >= USB_SPEED_SUPER) {
 566                 u32 burst = dep->endpoint.maxburst;
 567                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
 568         }
 569
 570         params.param0 |= action;
 571         if (action == DWC3_DEPCFG_ACTION_RESTORE)
 572                 params.param2 |= dep->saved_state;
 573
 574         if (usb_endpoint_xfer_control(desc))
 575                 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
 576
 577         if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
 578                 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
 579
 580         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 581                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 582                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 583                 dep->stream_capable = true;
 584         }
 585
 586         if (!usb_endpoint_xfer_control(desc))
 587                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 588
 589         /*
 590          * We are doing 1:1 mapping for endpoints, meaning
 591          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 592          * so on. We consider the direction bit as part of the physical
 593          * endpoint number. So USB endpoint 0x81 is 0x03.
 594          */
 595         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 596
 597         /*
 598          * We must use the lower 16 TX FIFOs even though
 599          * HW might have more
 600          */
 601         if (dep->direction)
 602                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 603
 604         if (desc->bInterval) {
 605                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 606                 dep->interval = 1 << (desc->bInterval - 1);
 607         }
 608
 609         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
 610 }
 611
 612 /**
 613  * __dwc3_gadget_ep_enable - initializes a hw endpoint
 614  * @dep: endpoint to be initialized
 615  * @action: one of INIT, MODIFY or RESTORE
 616  *
 617  * Caller should take care of locking. Execute all necessary commands to
 618  * initialize a HW endpoint so it can be used by a gadget driver.
 619  */
 620 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
 621 {
 622         const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
 623         struct dwc3             *dwc = dep->dwc;
 624
 625         u32                     reg;
 626         int                     ret;
 627
 628         if (!(dep->flags & DWC3_EP_ENABLED)) {
 629                 ret = dwc3_gadget_start_config(dep);
 630                 if (ret)
 631                         return ret;
 632         }
 633
 634         ret = dwc3_gadget_set_ep_config(dep, action);
 635         if (ret)
 636                 return ret;
 637
 638         if (!(dep->flags & DWC3_EP_ENABLED)) {
 639                 struct dwc3_trb *trb_st_hw;
 640                 struct dwc3_trb *trb_link;
 641
 642                 dep->type = usb_endpoint_type(desc);
 643                 dep->flags |= DWC3_EP_ENABLED;
 644                 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
 645
 646                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 647                 reg |= DWC3_DALEPENA_EP(dep->number);
 648                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 649
 650                 init_waitqueue_head(&dep->wait_end_transfer);
 651
 652                 if (usb_endpoint_xfer_control(desc))
 653                         goto out;
 654
 655                 /* Initialize the TRB ring */
 656                 dep->trb_dequeue = 0;
 657                 dep->trb_enqueue = 0;
 658                 memset(dep->trb_pool, 0,
 659                        sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
 660
 661                 /* Link TRB. The HWO bit is never reset */
 662                 trb_st_hw = &dep->trb_pool[0];
 663
 664                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 665                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 666                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 667                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 668                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 669         }
 670
 671         /*
 672          * Issue StartTransfer here with no-op TRB so we can always rely on No
 673          * Response Update Transfer command.
 674          */
 675         if (usb_endpoint_xfer_bulk(desc) ||
 676                         usb_endpoint_xfer_int(desc)) {
 677                 struct dwc3_gadget_ep_cmd_params params;
 678                 struct dwc3_trb *trb;
 679                 dma_addr_t trb_dma;
 680                 u32 cmd;
 681
 682                 memset(&params, 0, sizeof(params));
 683                 trb = &dep->trb_pool[0];
 684                 trb_dma = dwc3_trb_dma_offset(dep, trb);
 685
 686                 params.param0 = upper_32_bits(trb_dma);
 687                 params.param1 = lower_32_bits(trb_dma);
 688
 689                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 690
 691                 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 692                 if (ret < 0)
 693                         return ret;
 694         }
 695
 696 out:
 697         trace_dwc3_gadget_ep_enable(dep);
 698
 699         return 0;
 700 }
 701
 702 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force);
 703 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 704 {
 705         struct dwc3_request             *req;
 706
 707         dwc3_stop_active_transfer(dep, true);
 708
 709         /* - giveback all requests to gadget driver */
 710         while (!list_empty(&dep->started_list)) {
 711                 req = next_request(&dep->started_list);
 712
 713                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 714         }
 715
 716         while (!list_empty(&dep->pending_list)) {
 717                 req = next_request(&dep->pending_list);
 718
 719                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 720         }
 721 }
 722
 723 /**
 724  * __dwc3_gadget_ep_disable - disables a hw endpoint
 725  * @dep: the endpoint to disable
 726  *
 727  * This function undoes what __dwc3_gadget_ep_enable did and also removes
 728  * requests which are currently being processed by the hardware and those which
 729  * are not yet scheduled.
 730  *
 731  * Caller should take care of locking.
 732  */
 733 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 734 {
 735         struct dwc3             *dwc = dep->dwc;
 736         u32                     reg;
 737
 738         trace_dwc3_gadget_ep_disable(dep);
 739
 740         dwc3_remove_requests(dwc, dep);
 741
 742         /* make sure HW endpoint isn't stalled */
 743         if (dep->flags & DWC3_EP_STALL)
 744                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 745
 746         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 747         reg &= ~DWC3_DALEPENA_EP(dep->number);
 748         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 749
 750         dep->stream_capable = false;
 751         dep->type = 0;
 752         dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
 753
 754         /* Clear out the ep descriptors for non-ep0 */
 755         if (dep->number > 1) {
 756                 dep->endpoint.comp_desc = NULL;
 757                 dep->endpoint.desc = NULL;
 758         }
 759
 760         return 0;
 761 }
 762
 763 /* -------------------------------------------------------------------------- */
 764
 765 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 766                 const struct usb_endpoint_descriptor *desc)
 767 {
 768         return -EINVAL;
 769 }
 770
 771 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 772 {
 773         return -EINVAL;
 774 }
 775
 776 /* -------------------------------------------------------------------------- */
 777
 778 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 779                 const struct usb_endpoint_descriptor *desc)
 780 {
 781         struct dwc3_ep                  *dep;
 782         struct dwc3                     *dwc;
 783         unsigned long                   flags;
 784         int                             ret;
 785
 786         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 787                 pr_debug("dwc3: invalid parameters\n");
 788                 return -EINVAL;
 789         }
 790
 791         if (!desc->wMaxPacketSize) {
 792                 pr_debug("dwc3: missing wMaxPacketSize\n");
 793                 return -EINVAL;
 794         }
 795
 796         dep = to_dwc3_ep(ep);
 797         dwc = dep->dwc;
 798
 799         if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
 800                                         "%s is already enabled\n",
 801                                         dep->name))
 802                 return 0;
 803
 804         spin_lock_irqsave(&dwc->lock, flags);
 805         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
 806         spin_unlock_irqrestore(&dwc->lock, flags);
 807
 808         return ret;
 809 }
 810
 811 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 812 {
 813         struct dwc3_ep                  *dep;
 814         struct dwc3                     *dwc;
 815         unsigned long                   flags;
 816         int                             ret;
 817
 818         if (!ep) {
 819                 pr_debug("dwc3: invalid parameters\n");
 820                 return -EINVAL;
 821         }
 822
 823         dep = to_dwc3_ep(ep);
 824         dwc = dep->dwc;
 825
 826         if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
 827                                         "%s is already disabled\n",
 828                                         dep->name))
 829                 return 0;
 830
 831         spin_lock_irqsave(&dwc->lock, flags);
 832         ret = __dwc3_gadget_ep_disable(dep);
 833         spin_unlock_irqrestore(&dwc->lock, flags);
 834
 835         return ret;
 836 }
 837
 838 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 839                 gfp_t gfp_flags)
 840 {
 841         struct dwc3_request             *req;
 842         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 843
 844         req = kzalloc(sizeof(*req), gfp_flags);
 845         if (!req)
 846                 return NULL;
 847
 848         req->direction  = dep->direction;
 849         req->epnum      = dep->number;
 850         req->dep        = dep;
 851
 852         trace_dwc3_alloc_request(req);
 853
 854         return &req->request;
 855 }
 856
 857 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 858                 struct usb_request *request)
 859 {
 860         struct dwc3_request             *req = to_dwc3_request(request);
 861
 862         trace_dwc3_free_request(req);
 863         kfree(req);
 864 }
 865
 866 /**
 867  * dwc3_ep_prev_trb - returns the previous TRB in the ring
 868  * @dep: The endpoint with the TRB ring
 869  * @index: The index of the current TRB in the ring
 870  *
 871  * Returns the TRB prior to the one pointed to by the index. If the
 872  * index is 0, we will wrap backwards, skip the link TRB, and return
 873  * the one just before that.
 874  */
 875 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
 876 {
 877         u8 tmp = index;
 878
 879         if (!tmp)
 880                 tmp = DWC3_TRB_NUM - 1;
 881
 882         return &dep->trb_pool[tmp - 1];
 883 }
 884
 885 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
 886 {
 887         struct dwc3_trb         *tmp;
 888         u8                      trbs_left;
 889
 890         /*
 891          * If enqueue & dequeue are equal than it is either full or empty.
 892          *
 893          * One way to know for sure is if the TRB right before us has HWO bit
 894          * set or not. If it has, then we're definitely full and can't fit any
 895          * more transfers in our ring.
 896          */
 897         if (dep->trb_enqueue == dep->trb_dequeue) {
 898                 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
 899                 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
 900                         return 0;
 901
 902                 return DWC3_TRB_NUM - 1;
 903         }
 904
 905         trbs_left = dep->trb_dequeue - dep->trb_enqueue;
 906         trbs_left &= (DWC3_TRB_NUM - 1);
 907
 908         if (dep->trb_dequeue < dep->trb_enqueue)
 909                 trbs_left--;
 910
 911         return trbs_left;
 912 }
 913
 914 static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
 915                 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
 916                 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
 917 {
 918         struct dwc3             *dwc = dep->dwc;
 919         struct usb_gadget       *gadget = &dwc->gadget;
 920         enum usb_device_speed   speed = gadget->speed;
 921
 922         dwc3_ep_inc_enq(dep);
 923
 924         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 925         trb->bpl = lower_32_bits(dma);
 926         trb->bph = upper_32_bits(dma);
 927
 928         switch (usb_endpoint_type(dep->endpoint.desc)) {
 929         case USB_ENDPOINT_XFER_CONTROL:
 930                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 931                 break;
 932
 933         case USB_ENDPOINT_XFER_ISOC:
 934                 if (!node) {
 935                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 936
 937                         /*
 938                          * USB Specification 2.0 Section 5.9.2 states that: "If
 939                          * there is only a single transaction in the microframe,
 940                          * only a DATA0 data packet PID is used.  If there are
 941                          * two transactions per microframe, DATA1 is used for
 942                          * the first transaction data packet and DATA0 is used
 943                          * for the second transaction data packet.  If there are
 944                          * three transactions per microframe, DATA2 is used for
 945                          * the first transaction data packet, DATA1 is used for
 946                          * the second, and DATA0 is used for the third."
 947                          *
 948                          * IOW, we should satisfy the following cases:
 949                          *
 950                          * 1) length <= maxpacket
 951                          *      - DATA0
 952                          *
 953                          * 2) maxpacket < length <= (2 * maxpacket)
 954                          *      - DATA1, DATA0
 955                          *
 956                          * 3) (2 * maxpacket) < length <= (3 * maxpacket)
 957                          *      - DATA2, DATA1, DATA0
 958                          */
 959                         if (speed == USB_SPEED_HIGH) {
 960                                 struct usb_ep *ep = &dep->endpoint;
 961                                 unsigned int mult = 2;
 962                                 unsigned int maxp = usb_endpoint_maxp(ep->desc);
 963
 964                                 if (length <= (2 * maxp))
 965                                         mult--;
 966
 967                                 if (length <= maxp)
 968                                         mult--;
 969
 970                                 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
 971                         }
 972                 } else {
 973                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 974                 }
 975
 976                 /* always enable Interrupt on Missed ISOC */
 977                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 978                 break;
 979
 980         case USB_ENDPOINT_XFER_BULK:
 981         case USB_ENDPOINT_XFER_INT:
 982                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 983                 break;
 984         default:
 985                 /*
 986                  * This is only possible with faulty memory because we
 987                  * checked it already :)
 988                  */
 989                 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
 990                                 usb_endpoint_type(dep->endpoint.desc));
 991         }
 992
 993         /* always enable Continue on Short Packet */
 994         if (usb_endpoint_dir_out(dep->endpoint.desc)) {
 995                 trb->ctrl |= DWC3_TRB_CTRL_CSP;
 996
 997                 if (short_not_ok)
 998                         trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 999         }
1000
1001         if ((!no_interrupt && !chain) ||
1002                         (dwc3_calc_trbs_left(dep) == 0))
1003                 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1004
1005         if (chain)
1006                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1007
1008         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1009                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1010
1011         trb->ctrl |= DWC3_TRB_CTRL_HWO;
1012
1013         trace_dwc3_prepare_trb(dep, trb);
1014 }
1015
1016 /**
1017  * dwc3_prepare_one_trb - setup one TRB from one request
1018  * @dep: endpoint for which this request is prepared
1019  * @req: dwc3_request pointer
1020  * @chain: should this TRB be chained to the next?
1021  * @node: only for isochronous endpoints. First TRB needs different type.
1022  */
1023 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1024                 struct dwc3_request *req, unsigned chain, unsigned node)
1025 {
1026         struct dwc3_trb         *trb;
1027         unsigned int            length;
1028         dma_addr_t              dma;
1029         unsigned                stream_id = req->request.stream_id;
1030         unsigned                short_not_ok = req->request.short_not_ok;
1031         unsigned                no_interrupt = req->request.no_interrupt;
1032
1033         if (req->request.num_sgs > 0) {
1034                 length = sg_dma_len(req->start_sg);
1035                 dma = sg_dma_address(req->start_sg);
1036         } else {
1037                 length = req->request.length;
1038                 dma = req->request.dma;
1039         }
1040
1041         trb = &dep->trb_pool[dep->trb_enqueue];
1042
1043         if (!req->trb) {
1044                 dwc3_gadget_move_started_request(req);
1045                 req->trb = trb;
1046                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1047         }
1048
1049         __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
1050                         stream_id, short_not_ok, no_interrupt);
1051 }
1052
1053 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
1054                 struct dwc3_request *req)
1055 {
1056         struct scatterlist *sg = req->start_sg;
1057         struct scatterlist *s;
1058         int             i;
1059
1060         unsigned int remaining = req->request.num_mapped_sgs
1061                 - req->num_queued_sgs;
1062
1063         for_each_sg(sg, s, remaining, i) {
1064                 unsigned int length = req->request.length;
1065                 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1066                 unsigned int rem = length % maxp;
1067                 unsigned chain = true;
1068
1069                 if (sg_is_last(s))
1070                         chain = false;
1071
1072                 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1073                         struct dwc3     *dwc = dep->dwc;
1074                         struct dwc3_trb *trb;
1075
1076                         req->unaligned = true;
1077
1078                         /* prepare normal TRB */
1079                         dwc3_prepare_one_trb(dep, req, true, i);
1080
1081                         /* Now prepare one extra TRB to align transfer size */
1082                         trb = &dep->trb_pool[dep->trb_enqueue];
1083                         __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1084                                         maxp - rem, false, 0,
1085                                         req->request.stream_id,
1086                                         req->request.short_not_ok,
1087                                         req->request.no_interrupt);
1088                 } else {
1089                         dwc3_prepare_one_trb(dep, req, chain, i);
1090                 }
1091
1092                 /*
1093                  * There can be a situation where all sgs in sglist are not
1094                  * queued because of insufficient trb number. To handle this
1095                  * case, update start_sg to next sg to be queued, so that
1096                  * we have free trbs we can continue queuing from where we
1097                  * previously stopped
1098                  */
1099                 if (chain)
1100                         req->start_sg = sg_next(s);
1101
1102                 req->num_queued_sgs++;
1103
1104                 if (!dwc3_calc_trbs_left(dep))
1105                         break;
1106         }
1107 }
1108
1109 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
1110                 struct dwc3_request *req)
1111 {
1112         unsigned int length = req->request.length;
1113         unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1114         unsigned int rem = length % maxp;
1115
1116         if (rem && usb_endpoint_dir_out(dep->endpoint.desc)) {
1117                 struct dwc3     *dwc = dep->dwc;
1118                 struct dwc3_trb *trb;
1119
1120                 req->unaligned = true;
1121
1122                 /* prepare normal TRB */
1123                 dwc3_prepare_one_trb(dep, req, true, 0);
1124
1125                 /* Now prepare one extra TRB to align transfer size */
1126                 trb = &dep->trb_pool[dep->trb_enqueue];
1127                 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1128                                 false, 0, req->request.stream_id,
1129                                 req->request.short_not_ok,
1130                                 req->request.no_interrupt);
1131         } else if (req->request.zero && req->request.length &&
1132                    (IS_ALIGNED(req->request.length, maxp))) {
1133                 struct dwc3     *dwc = dep->dwc;
1134                 struct dwc3_trb *trb;
1135
1136                 req->zero = true;
1137
1138                 /* prepare normal TRB */
1139                 dwc3_prepare_one_trb(dep, req, true, 0);
1140
1141                 /* Now prepare one extra TRB to handle ZLP */
1142                 trb = &dep->trb_pool[dep->trb_enqueue];
1143                 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1144                                 false, 0, req->request.stream_id,
1145                                 req->request.short_not_ok,
1146                                 req->request.no_interrupt);
1147         } else {
1148                 dwc3_prepare_one_trb(dep, req, false, 0);
1149         }
1150 }
1151
1152 /*
1153  * dwc3_prepare_trbs - setup TRBs from requests
1154  * @dep: endpoint for which requests are being prepared
1155  *
1156  * The function goes through the requests list and sets up TRBs for the
1157  * transfers. The function returns once there are no more TRBs available or
1158  * it runs out of requests.
1159  */
1160 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1161 {
1162         struct dwc3_request     *req, *n;
1163
1164         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1165
1166         /*
1167          * We can get in a situation where there's a request in the started list
1168          * but there weren't enough TRBs to fully kick it in the first time
1169          * around, so it has been waiting for more TRBs to be freed up.
1170          *
1171          * In that case, we should check if we have a request with pending_sgs
1172          * in the started list and prepare TRBs for that request first,
1173          * otherwise we will prepare TRBs completely out of order and that will
1174          * break things.
1175          */
1176         list_for_each_entry(req, &dep->started_list, list) {
1177                 if (req->num_pending_sgs > 0)
1178                         dwc3_prepare_one_trb_sg(dep, req);
1179
1180                 if (!dwc3_calc_trbs_left(dep))
1181                         return;
1182         }
1183
1184         list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1185                 struct dwc3     *dwc = dep->dwc;
1186                 int             ret;
1187
1188                 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1189                                                     dep->direction);
1190                 if (ret)
1191                         return;
1192
1193                 req->sg                 = req->request.sg;
1194                 req->start_sg           = req->sg;
1195                 req->num_queued_sgs     = 0;
1196                 req->num_pending_sgs    = req->request.num_mapped_sgs;
1197
1198                 if (req->num_pending_sgs > 0)
1199                         dwc3_prepare_one_trb_sg(dep, req);
1200                 else
1201                         dwc3_prepare_one_trb_linear(dep, req);
1202
1203                 if (!dwc3_calc_trbs_left(dep))
1204                         return;
1205         }
1206 }
1207
1208 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1209 {
1210         struct dwc3_gadget_ep_cmd_params params;
1211         struct dwc3_request             *req;
1212         int                             starting;
1213         int                             ret;
1214         u32                             cmd;
1215
1216         if (!dwc3_calc_trbs_left(dep))
1217                 return 0;
1218
1219         starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1220
1221         dwc3_prepare_trbs(dep);
1222         req = next_request(&dep->started_list);
1223         if (!req) {
1224                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1225                 return 0;
1226         }
1227
1228         memset(&params, 0, sizeof(params));
1229
1230         if (starting) {
1231                 params.param0 = upper_32_bits(req->trb_dma);
1232                 params.param1 = lower_32_bits(req->trb_dma);
1233                 cmd = DWC3_DEPCMD_STARTTRANSFER;
1234
1235                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1236                         cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1237         } else {
1238                 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1239                         DWC3_DEPCMD_PARAM(dep->resource_index);
1240         }
1241
1242         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1243         if (ret < 0) {
1244                 /*
1245                  * FIXME we need to iterate over the list of requests
1246                  * here and stop, unmap, free and del each of the linked
1247                  * requests instead of what we do now.
1248                  */
1249                 if (req->trb)
1250                         memset(req->trb, 0, sizeof(struct dwc3_trb));
1251                 dwc3_gadget_del_and_unmap_request(dep, req, ret);
1252                 return ret;
1253         }
1254
1255         return 0;
1256 }
1257
1258 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1259 {
1260         u32                     reg;
1261
1262         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1263         return DWC3_DSTS_SOFFN(reg);
1264 }
1265
1266 static void __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1267 {
1268         if (list_empty(&dep->pending_list)) {
1269                 dev_info(dep->dwc->dev, "%s: ran out of requests\n",
1270                                 dep->name);
1271                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1272                 return;
1273         }
1274
1275         dep->frame_number = DWC3_ALIGN_FRAME(dep);
1276         __dwc3_gadget_kick_transfer(dep);
1277 }
1278
1279 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1280 {
1281         struct dwc3             *dwc = dep->dwc;
1282
1283         if (!dep->endpoint.desc) {
1284                 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1285                                 dep->name);
1286                 return -ESHUTDOWN;
1287         }
1288
1289         if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1290                                 &req->request, req->dep->name))
1291                 return -EINVAL;
1292
1293         pm_runtime_get(dwc->dev);
1294
1295         req->request.actual     = 0;
1296         req->request.status     = -EINPROGRESS;
1297
1298         trace_dwc3_ep_queue(req);
1299
1300         list_add_tail(&req->list, &dep->pending_list);
1301
1302         /*
1303          * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1304          * wait for a XferNotReady event so we will know what's the current
1305          * (micro-)frame number.
1306          *
1307          * Without this trick, we are very, very likely gonna get Bus Expiry
1308          * errors which will force us issue EndTransfer command.
1309          */
1310         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1311                 if (!(dep->flags & DWC3_EP_PENDING_REQUEST) &&
1312                                 !(dep->flags & DWC3_EP_TRANSFER_STARTED))
1313                         return 0;
1314
1315                 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1316                         if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) {
1317                                 __dwc3_gadget_start_isoc(dep);
1318                                 return 0;
1319                         }
1320                 }
1321         }
1322
1323         return __dwc3_gadget_kick_transfer(dep);
1324 }
1325
1326 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1327         gfp_t gfp_flags)
1328 {
1329         struct dwc3_request             *req = to_dwc3_request(request);
1330         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1331         struct dwc3                     *dwc = dep->dwc;
1332
1333         unsigned long                   flags;
1334
1335         int                             ret;
1336
1337         spin_lock_irqsave(&dwc->lock, flags);
1338         ret = __dwc3_gadget_ep_queue(dep, req);
1339         spin_unlock_irqrestore(&dwc->lock, flags);
1340
1341         return ret;
1342 }
1343
1344 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1345                 struct usb_request *request)
1346 {
1347         struct dwc3_request             *req = to_dwc3_request(request);
1348         struct dwc3_request             *r = NULL;
1349
1350         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1351         struct dwc3                     *dwc = dep->dwc;
1352
1353         unsigned long                   flags;
1354         int                             ret = 0;
1355
1356         trace_dwc3_ep_dequeue(req);
1357
1358         spin_lock_irqsave(&dwc->lock, flags);
1359
1360         list_for_each_entry(r, &dep->pending_list, list) {
1361                 if (r == req)
1362                         break;
1363         }
1364
1365         if (r != req) {
1366                 list_for_each_entry(r, &dep->started_list, list) {
1367                         if (r == req)
1368                                 break;
1369                 }
1370                 if (r == req) {
1371                         /* wait until it is processed */
1372                         dwc3_stop_active_transfer(dep, true);
1373
1374                         /*
1375                          * If request was already started, this means we had to
1376                          * stop the transfer. With that we also need to ignore
1377                          * all TRBs used by the request, however TRBs can only
1378                          * be modified after completion of END_TRANSFER
1379                          * command. So what we do here is that we wait for
1380                          * END_TRANSFER completion and only after that, we jump
1381                          * over TRBs by clearing HWO and incrementing dequeue
1382                          * pointer.
1383                          *
1384                          * Note that we have 2 possible types of transfers here:
1385                          *
1386                          * i) Linear buffer request
1387                          * ii) SG-list based request
1388                          *
1389                          * SG-list based requests will have r->num_pending_sgs
1390                          * set to a valid number (> 0). Linear requests,
1391                          * normally use a single TRB.
1392                          *
1393                          * For each of these two cases, if r->unaligned flag is
1394                          * set, one extra TRB has been used to align transfer
1395                          * size to wMaxPacketSize.
1396                          *
1397                          * All of these cases need to be taken into
1398                          * consideration so we don't mess up our TRB ring
1399                          * pointers.
1400                          */
1401                         wait_event_lock_irq(dep->wait_end_transfer,
1402                                         !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1403                                         dwc->lock);
1404
1405                         if (!r->trb)
1406                                 goto out0;
1407
1408                         if (r->num_pending_sgs) {
1409                                 struct dwc3_trb *trb;
1410                                 int i = 0;
1411
1412                                 for (i = 0; i < r->num_pending_sgs; i++) {
1413                                         trb = r->trb + i;
1414                                         trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1415                                         dwc3_ep_inc_deq(dep);
1416                                 }
1417
1418                                 if (r->unaligned || r->zero) {
1419                                         trb = r->trb + r->num_pending_sgs + 1;
1420                                         trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1421                                         dwc3_ep_inc_deq(dep);
1422                                 }
1423                         } else {
1424                                 struct dwc3_trb *trb = r->trb;
1425
1426                                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1427                                 dwc3_ep_inc_deq(dep);
1428
1429                                 if (r->unaligned || r->zero) {
1430                                         trb = r->trb + 1;
1431                                         trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1432                                         dwc3_ep_inc_deq(dep);
1433                                 }
1434                         }
1435                         goto out1;
1436                 }
1437                 dev_err(dwc->dev, "request %pK was not queued to %s\n",
1438                                 request, ep->name);
1439                 ret = -EINVAL;
1440                 goto out0;
1441         }
1442
1443 out1:
1444         /* giveback the request */
1445
1446         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1447
1448 out0:
1449         spin_unlock_irqrestore(&dwc->lock, flags);
1450
1451         return ret;
1452 }
1453
1454 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1455 {
1456         struct dwc3_gadget_ep_cmd_params        params;
1457         struct dwc3                             *dwc = dep->dwc;
1458         int                                     ret;
1459
1460         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1461                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1462                 return -EINVAL;
1463         }
1464
1465         memset(&params, 0x00, sizeof(params));
1466
1467         if (value) {
1468                 struct dwc3_trb *trb;
1469
1470                 unsigned transfer_in_flight;
1471                 unsigned started;
1472
1473                 if (dep->flags & DWC3_EP_STALL)
1474                         return 0;
1475
1476                 if (dep->number > 1)
1477                         trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1478                 else
1479                         trb = &dwc->ep0_trb[dep->trb_enqueue];
1480
1481                 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1482                 started = !list_empty(&dep->started_list);
1483
1484                 if (!protocol && ((dep->direction && transfer_in_flight) ||
1485                                 (!dep->direction && started))) {
1486                         return -EAGAIN;
1487                 }
1488
1489                 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1490                                 &params);
1491                 if (ret)
1492                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1493                                         dep->name);
1494                 else
1495                         dep->flags |= DWC3_EP_STALL;
1496         } else {
1497                 if (!(dep->flags & DWC3_EP_STALL))
1498                         return 0;
1499
1500                 ret = dwc3_send_clear_stall_ep_cmd(dep);
1501                 if (ret)
1502                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1503                                         dep->name);
1504                 else
1505                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1506         }
1507
1508         return ret;
1509 }
1510
1511 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1512 {
1513         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1514         struct dwc3                     *dwc = dep->dwc;
1515
1516         unsigned long                   flags;
1517
1518         int                             ret;
1519
1520         spin_lock_irqsave(&dwc->lock, flags);
1521         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1522         spin_unlock_irqrestore(&dwc->lock, flags);
1523
1524         return ret;
1525 }
1526
1527 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1528 {
1529         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1530         struct dwc3                     *dwc = dep->dwc;
1531         unsigned long                   flags;
1532         int                             ret;
1533
1534         spin_lock_irqsave(&dwc->lock, flags);
1535         dep->flags |= DWC3_EP_WEDGE;
1536
1537         if (dep->number == 0 || dep->number == 1)
1538                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1539         else
1540                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1541         spin_unlock_irqrestore(&dwc->lock, flags);
1542
1543         return ret;
1544 }
1545
1546 /* -------------------------------------------------------------------------- */
1547
1548 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1549         .bLength        = USB_DT_ENDPOINT_SIZE,
1550         .bDescriptorType = USB_DT_ENDPOINT,
1551         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1552 };
1553
1554 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1555         .enable         = dwc3_gadget_ep0_enable,
1556         .disable        = dwc3_gadget_ep0_disable,
1557         .alloc_request  = dwc3_gadget_ep_alloc_request,
1558         .free_request   = dwc3_gadget_ep_free_request,
1559         .queue          = dwc3_gadget_ep0_queue,
1560         .dequeue        = dwc3_gadget_ep_dequeue,
1561         .set_halt       = dwc3_gadget_ep0_set_halt,
1562         .set_wedge      = dwc3_gadget_ep_set_wedge,
1563 };
1564
1565 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1566         .enable         = dwc3_gadget_ep_enable,
1567         .disable        = dwc3_gadget_ep_disable,
1568         .alloc_request  = dwc3_gadget_ep_alloc_request,
1569         .free_request   = dwc3_gadget_ep_free_request,
1570         .queue          = dwc3_gadget_ep_queue,
1571         .dequeue        = dwc3_gadget_ep_dequeue,
1572         .set_halt       = dwc3_gadget_ep_set_halt,
1573         .set_wedge      = dwc3_gadget_ep_set_wedge,
1574 };
1575
1576 /* -------------------------------------------------------------------------- */
1577
1578 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1579 {
1580         struct dwc3             *dwc = gadget_to_dwc(g);
1581
1582         return __dwc3_gadget_get_frame(dwc);
1583 }
1584
1585 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1586 {
1587         int                     retries;
1588
1589         int                     ret;
1590         u32                     reg;
1591
1592         u8                      link_state;
1593         u8                      speed;
1594
1595         /*
1596          * According to the Databook Remote wakeup request should
1597          * be issued only when the device is in early suspend state.
1598          *
1599          * We can check that via USB Link State bits in DSTS register.
1600          */
1601         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1602
1603         speed = reg & DWC3_DSTS_CONNECTSPD;
1604         if ((speed == DWC3_DSTS_SUPERSPEED) ||
1605             (speed == DWC3_DSTS_SUPERSPEED_PLUS))
1606                 return 0;
1607
1608         link_state = DWC3_DSTS_USBLNKST(reg);
1609
1610         switch (link_state) {
1611         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1612         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1613                 break;
1614         default:
1615                 return -EINVAL;
1616         }
1617
1618         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1619         if (ret < 0) {
1620                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1621                 return ret;
1622         }
1623
1624         /* Recent versions do this automatically */
1625         if (dwc->revision < DWC3_REVISION_194A) {
1626                 /* write zeroes to Link Change Request */
1627                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1628                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1629                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1630         }
1631
1632         /* poll until Link State changes to ON */
1633         retries = 20000;
1634
1635         while (retries--) {
1636                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1637
1638                 /* in HS, means ON */
1639                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1640                         break;
1641         }
1642
1643         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1644                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1645                 return -EINVAL;
1646         }
1647
1648         return 0;
1649 }
1650
1651 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1652 {
1653         struct dwc3             *dwc = gadget_to_dwc(g);
1654         unsigned long           flags;
1655         int                     ret;
1656
1657         spin_lock_irqsave(&dwc->lock, flags);
1658         ret = __dwc3_gadget_wakeup(dwc);
1659         spin_unlock_irqrestore(&dwc->lock, flags);
1660
1661         return ret;
1662 }
1663
1664 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1665                 int is_selfpowered)
1666 {
1667         struct dwc3             *dwc = gadget_to_dwc(g);
1668         unsigned long           flags;
1669
1670         spin_lock_irqsave(&dwc->lock, flags);
1671         g->is_selfpowered = !!is_selfpowered;
1672         spin_unlock_irqrestore(&dwc->lock, flags);
1673
1674         return 0;
1675 }
1676
1677 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1678 {
1679         u32                     reg;
1680         u32                     timeout = 500;
1681
1682         if (pm_runtime_suspended(dwc->dev))
1683                 return 0;
1684
1685         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1686         if (is_on) {
1687                 if (dwc->revision <= DWC3_REVISION_187A) {
1688                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1689                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1690                 }
1691
1692                 if (dwc->revision >= DWC3_REVISION_194A)
1693                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1694                 reg |= DWC3_DCTL_RUN_STOP;
1695
1696                 if (dwc->has_hibernation)
1697                         reg |= DWC3_DCTL_KEEP_CONNECT;
1698
1699                 dwc->pullups_connected = true;
1700         } else {
1701                 reg &= ~DWC3_DCTL_RUN_STOP;
1702
1703                 if (dwc->has_hibernation && !suspend)
1704                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1705
1706                 dwc->pullups_connected = false;
1707         }
1708
1709         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1710
1711         do {
1712                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1713                 reg &= DWC3_DSTS_DEVCTRLHLT;
1714         } while (--timeout && !(!is_on ^ !reg));
1715
1716         if (!timeout)
1717                 return -ETIMEDOUT;
1718
1719         return 0;
1720 }
1721
1722 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1723 {
1724         struct dwc3             *dwc = gadget_to_dwc(g);
1725         unsigned long           flags;
1726         int                     ret;
1727
1728         is_on = !!is_on;
1729
1730         /*
1731          * Per databook, when we want to stop the gadget, if a control transfer
1732          * is still in process, complete it and get the core into setup phase.
1733          */
1734         if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1735                 reinit_completion(&dwc->ep0_in_setup);
1736
1737                 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1738                                 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1739                 if (ret == 0) {
1740                         dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1741                         return -ETIMEDOUT;
1742                 }
1743         }
1744
1745         spin_lock_irqsave(&dwc->lock, flags);
1746         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1747         spin_unlock_irqrestore(&dwc->lock, flags);
1748
1749         return ret;
1750 }
1751
1752 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1753 {
1754         u32                     reg;
1755
1756         /* Enable all but Start and End of Frame IRQs */
1757         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1758                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1759                         DWC3_DEVTEN_CMDCMPLTEN |
1760                         DWC3_DEVTEN_ERRTICERREN |
1761                         DWC3_DEVTEN_WKUPEVTEN |
1762                         DWC3_DEVTEN_CONNECTDONEEN |
1763                         DWC3_DEVTEN_USBRSTEN |
1764                         DWC3_DEVTEN_DISCONNEVTEN);
1765
1766         if (dwc->revision < DWC3_REVISION_250A)
1767                 reg |= DWC3_DEVTEN_ULSTCNGEN;
1768
1769         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1770 }
1771
1772 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1773 {
1774         /* mask all interrupts */
1775         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1776 }
1777
1778 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1779 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1780
1781 /**
1782  * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
1783  * @dwc: pointer to our context structure
1784  *
1785  * The following looks like complex but it's actually very simple. In order to
1786  * calculate the number of packets we can burst at once on OUT transfers, we're
1787  * gonna use RxFIFO size.
1788  *
1789  * To calculate RxFIFO size we need two numbers:
1790  * MDWIDTH = size, in bits, of the internal memory bus
1791  * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1792  *
1793  * Given these two numbers, the formula is simple:
1794  *
1795  * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1796  *
1797  * 24 bytes is for 3x SETUP packets
1798  * 16 bytes is a clock domain crossing tolerance
1799  *
1800  * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1801  */
1802 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1803 {
1804         u32 ram2_depth;
1805         u32 mdwidth;
1806         u32 nump;
1807         u32 reg;
1808
1809         ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1810         mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1811
1812         nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1813         nump = min_t(u32, nump, 16);
1814
1815         /* update NumP */
1816         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1817         reg &= ~DWC3_DCFG_NUMP_MASK;
1818         reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1819         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1820 }
1821
1822 static int __dwc3_gadget_start(struct dwc3 *dwc)
1823 {
1824         struct dwc3_ep          *dep;
1825         int                     ret = 0;
1826         u32                     reg;
1827
1828         /*
1829          * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1830          * the core supports IMOD, disable it.
1831          */
1832         if (dwc->imod_interval) {
1833                 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1834                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1835         } else if (dwc3_has_imod(dwc)) {
1836                 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1837         }
1838
1839         /*
1840          * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1841          * field instead of letting dwc3 itself calculate that automatically.
1842          *
1843          * This way, we maximize the chances that we'll be able to get several
1844          * bursts of data without going through any sort of endpoint throttling.
1845          */
1846         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1847         if (dwc3_is_usb31(dwc))
1848                 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
1849         else
1850                 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1851
1852         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1853
1854         dwc3_gadget_setup_nump(dwc);
1855
1856         /* Start with SuperSpeed Default */
1857         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1858
1859         dep = dwc->eps[0];
1860         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1861         if (ret) {
1862                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1863                 goto err0;
1864         }
1865
1866         dep = dwc->eps[1];
1867         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1868         if (ret) {
1869                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1870                 goto err1;
1871         }
1872
1873         /* begin to receive SETUP packets */
1874         dwc->ep0state = EP0_SETUP_PHASE;
1875         dwc3_ep0_out_start(dwc);
1876
1877         dwc3_gadget_enable_irq(dwc);
1878
1879         return 0;
1880
1881 err1:
1882         __dwc3_gadget_ep_disable(dwc->eps[0]);
1883
1884 err0:
1885         return ret;
1886 }
1887
1888 static int dwc3_gadget_start(struct usb_gadget *g,
1889                 struct usb_gadget_driver *driver)
1890 {
1891         struct dwc3             *dwc = gadget_to_dwc(g);
1892         unsigned long           flags;
1893         int                     ret = 0;
1894         int                     irq;
1895
1896         irq = dwc->irq_gadget;
1897         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1898                         IRQF_SHARED, "dwc3", dwc->ev_buf);
1899         if (ret) {
1900                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1901                                 irq, ret);
1902                 goto err0;
1903         }
1904
1905         spin_lock_irqsave(&dwc->lock, flags);
1906         if (dwc->gadget_driver) {
1907                 dev_err(dwc->dev, "%s is already bound to %s\n",
1908                                 dwc->gadget.name,
1909                                 dwc->gadget_driver->driver.name);
1910                 ret = -EBUSY;
1911                 goto err1;
1912         }
1913
1914         dwc->gadget_driver      = driver;
1915
1916         if (pm_runtime_active(dwc->dev))
1917                 __dwc3_gadget_start(dwc);
1918
1919         spin_unlock_irqrestore(&dwc->lock, flags);
1920
1921         return 0;
1922
1923 err1:
1924         spin_unlock_irqrestore(&dwc->lock, flags);
1925         free_irq(irq, dwc);
1926
1927 err0:
1928         return ret;
1929 }
1930
1931 static void __dwc3_gadget_stop(struct dwc3 *dwc)
1932 {
1933         dwc3_gadget_disable_irq(dwc);
1934         __dwc3_gadget_ep_disable(dwc->eps[0]);
1935         __dwc3_gadget_ep_disable(dwc->eps[1]);
1936 }
1937
1938 static int dwc3_gadget_stop(struct usb_gadget *g)
1939 {
1940         struct dwc3             *dwc = gadget_to_dwc(g);
1941         unsigned long           flags;
1942         int                     epnum;
1943         u32                     tmo_eps = 0;
1944
1945         spin_lock_irqsave(&dwc->lock, flags);
1946
1947         if (pm_runtime_suspended(dwc->dev))
1948                 goto out;
1949
1950         __dwc3_gadget_stop(dwc);
1951
1952         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1953                 struct dwc3_ep  *dep = dwc->eps[epnum];
1954                 int ret;
1955
1956                 if (!dep)
1957                         continue;
1958
1959                 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1960                         continue;
1961
1962                 ret = wait_event_interruptible_lock_irq_timeout(dep->wait_end_transfer,
1963                             !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1964                             dwc->lock, msecs_to_jiffies(5));
1965
1966                 if (ret <= 0) {
1967                         /* Timed out or interrupted! There's nothing much
1968                          * we can do so we just log here and print which
1969                          * endpoints timed out at the end.
1970                          */
1971                         tmo_eps |= 1 << epnum;
1972                         dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
1973                 }
1974         }
1975
1976         if (tmo_eps) {
1977                 dev_err(dwc->dev,
1978                         "end transfer timed out on endpoints 0x%x [bitmap]\n",
1979                         tmo_eps);
1980         }
1981
1982 out:
1983         dwc->gadget_driver      = NULL;
1984         spin_unlock_irqrestore(&dwc->lock, flags);
1985
1986         free_irq(dwc->irq_gadget, dwc->ev_buf);
1987
1988         return 0;
1989 }
1990
1991 static void dwc3_gadget_set_speed(struct usb_gadget *g,
1992                                   enum usb_device_speed speed)
1993 {
1994         struct dwc3             *dwc = gadget_to_dwc(g);
1995         unsigned long           flags;
1996         u32                     reg;
1997
1998         spin_lock_irqsave(&dwc->lock, flags);
1999         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2000         reg &= ~(DWC3_DCFG_SPEED_MASK);
2001
2002         /*
2003          * WORKAROUND: DWC3 revision < 2.20a have an issue
2004          * which would cause metastability state on Run/Stop
2005          * bit if we try to force the IP to USB2-only mode.
2006          *
2007          * Because of that, we cannot configure the IP to any
2008          * speed other than the SuperSpeed
2009          *
2010          * Refers to:
2011          *
2012          * STAR#9000525659: Clock Domain Crossing on DCTL in
2013          * USB 2.0 Mode
2014          */
2015         if (dwc->revision < DWC3_REVISION_220A &&
2016             !dwc->dis_metastability_quirk) {
2017                 reg |= DWC3_DCFG_SUPERSPEED;
2018         } else {
2019                 switch (speed) {
2020                 case USB_SPEED_LOW:
2021                         reg |= DWC3_DCFG_LOWSPEED;
2022                         break;
2023                 case USB_SPEED_FULL:
2024                         reg |= DWC3_DCFG_FULLSPEED;
2025                         break;
2026                 case USB_SPEED_HIGH:
2027                         reg |= DWC3_DCFG_HIGHSPEED;
2028                         break;
2029                 case USB_SPEED_SUPER:
2030                         reg |= DWC3_DCFG_SUPERSPEED;
2031                         break;
2032                 case USB_SPEED_SUPER_PLUS:
2033                         if (dwc3_is_usb31(dwc))
2034                                 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2035                         else
2036                                 reg |= DWC3_DCFG_SUPERSPEED;
2037                         break;
2038                 default:
2039                         dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2040
2041                         if (dwc->revision & DWC3_REVISION_IS_DWC31)
2042                                 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2043                         else
2044                                 reg |= DWC3_DCFG_SUPERSPEED;
2045                 }
2046         }
2047         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2048
2049         spin_unlock_irqrestore(&dwc->lock, flags);
2050 }
2051
2052 static const struct usb_gadget_ops dwc3_gadget_ops = {
2053         .get_frame              = dwc3_gadget_get_frame,
2054         .wakeup                 = dwc3_gadget_wakeup,
2055         .set_selfpowered        = dwc3_gadget_set_selfpowered,
2056         .pullup                 = dwc3_gadget_pullup,
2057         .udc_start              = dwc3_gadget_start,
2058         .udc_stop               = dwc3_gadget_stop,
2059         .udc_set_speed          = dwc3_gadget_set_speed,
2060 };
2061
2062 /* -------------------------------------------------------------------------- */
2063
2064 static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
2065 {
2066         struct dwc3 *dwc = dep->dwc;
2067
2068         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2069         dep->endpoint.maxburst = 1;
2070         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2071         if (!dep->direction)
2072                 dwc->gadget.ep0 = &dep->endpoint;
2073
2074         dep->endpoint.caps.type_control = true;
2075
2076         return 0;
2077 }
2078
2079 static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
2080 {
2081         struct dwc3 *dwc = dep->dwc;
2082         int mdwidth;
2083         int kbytes;
2084         int size;
2085
2086         mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2087         /* MDWIDTH is represented in bits, we need it in bytes */
2088         mdwidth /= 8;
2089
2090         size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
2091         if (dwc3_is_usb31(dwc))
2092                 size = DWC31_GTXFIFOSIZ_TXFDEF(size);
2093         else
2094                 size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2095
2096         /* FIFO Depth is in MDWDITH bytes. Multiply */
2097         size *= mdwidth;
2098
2099         kbytes = size / 1024;
2100         if (kbytes == 0)
2101                 kbytes = 1;
2102
2103         /*
2104          * FIFO sizes account an extra MDWIDTH * (kbytes + 1) bytes for
2105          * internal overhead. We don't really know how these are used,
2106          * but documentation say it exists.
2107          */
2108         size -= mdwidth * (kbytes + 1);
2109         size /= kbytes;
2110
2111         usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2112
2113         dep->endpoint.max_streams = 15;
2114         dep->endpoint.ops = &dwc3_gadget_ep_ops;
2115         list_add_tail(&dep->endpoint.ep_list,
2116                         &dwc->gadget.ep_list);
2117         dep->endpoint.caps.type_iso = true;
2118         dep->endpoint.caps.type_bulk = true;
2119         dep->endpoint.caps.type_int = true;
2120
2121         return dwc3_alloc_trb_pool(dep);
2122 }
2123
2124 static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
2125 {
2126         struct dwc3 *dwc = dep->dwc;
2127
2128         usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
2129         dep->endpoint.max_streams = 15;
2130         dep->endpoint.ops = &dwc3_gadget_ep_ops;
2131         list_add_tail(&dep->endpoint.ep_list,
2132                         &dwc->gadget.ep_list);
2133         dep->endpoint.caps.type_iso = true;
2134         dep->endpoint.caps.type_bulk = true;
2135         dep->endpoint.caps.type_int = true;
2136
2137         return dwc3_alloc_trb_pool(dep);
2138 }
2139
2140 static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
2141 {
2142         struct dwc3_ep                  *dep;
2143         bool                            direction = epnum & 1;
2144         int                             ret;
2145         u8                              num = epnum >> 1;
2146
2147         dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2148         if (!dep)
2149                 return -ENOMEM;
2150
2151         dep->dwc = dwc;
2152         dep->number = epnum;
2153         dep->direction = direction;
2154         dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2155         dwc->eps[epnum] = dep;
2156
2157         snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2158                         direction ? "in" : "out");
2159
2160         dep->endpoint.name = dep->name;
2161
2162         if (!(dep->number > 1)) {
2163                 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2164                 dep->endpoint.comp_desc = NULL;
2165         }
2166
2167         spin_lock_init(&dep->lock);
2168
2169         if (num == 0)
2170                 ret = dwc3_gadget_init_control_endpoint(dep);
2171         else if (direction)
2172                 ret = dwc3_gadget_init_in_endpoint(dep);
2173         else
2174                 ret = dwc3_gadget_init_out_endpoint(dep);
2175
2176         if (ret)
2177                 return ret;
2178
2179         dep->endpoint.caps.dir_in = direction;
2180         dep->endpoint.caps.dir_out = !direction;
2181
2182         INIT_LIST_HEAD(&dep->pending_list);
2183         INIT_LIST_HEAD(&dep->started_list);
2184
2185         return 0;
2186 }
2187
2188 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
2189 {
2190         u8                              epnum;
2191
2192         INIT_LIST_HEAD(&dwc->gadget.ep_list);
2193
2194         for (epnum = 0; epnum < total; epnum++) {
2195                 int                     ret;
2196
2197                 ret = dwc3_gadget_init_endpoint(dwc, epnum);
2198                 if (ret)
2199                         return ret;
2200         }
2201
2202         return 0;
2203 }
2204
2205 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2206 {
2207         struct dwc3_ep                  *dep;
2208         u8                              epnum;
2209
2210         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2211                 dep = dwc->eps[epnum];
2212                 if (!dep)
2213                         continue;
2214                 /*
2215                  * Physical endpoints 0 and 1 are special; they form the
2216                  * bi-directional USB endpoint 0.
2217                  *
2218                  * For those two physical endpoints, we don't allocate a TRB
2219                  * pool nor do we add them the endpoints list. Due to that, we
2220                  * shouldn't do these two operations otherwise we would end up
2221                  * with all sorts of bugs when removing dwc3.ko.
2222                  */
2223                 if (epnum != 0 && epnum != 1) {
2224                         dwc3_free_trb_pool(dep);
2225                         list_del(&dep->endpoint.ep_list);
2226                 }
2227
2228                 kfree(dep);
2229         }
2230 }
2231
2232 /* -------------------------------------------------------------------------- */
2233
2234 static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
2235                 struct dwc3_request *req, struct dwc3_trb *trb,
2236                 const struct dwc3_event_depevt *event, int status, int chain)
2237 {
2238         unsigned int            count;
2239
2240         dwc3_ep_inc_deq(dep);
2241
2242         trace_dwc3_complete_trb(dep, trb);
2243
2244         /*
2245          * If we're in the middle of series of chained TRBs and we
2246          * receive a short transfer along the way, DWC3 will skip
2247          * through all TRBs including the last TRB in the chain (the
2248          * where CHN bit is zero. DWC3 will also avoid clearing HWO
2249          * bit and SW has to do it manually.
2250          *
2251          * We're going to do that here to avoid problems of HW trying
2252          * to use bogus TRBs for transfers.
2253          */
2254         if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2255                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2256
2257         /*
2258          * If we're dealing with unaligned size OUT transfer, we will be left
2259          * with one TRB pending in the ring. We need to manually clear HWO bit
2260          * from that TRB.
2261          */
2262         if ((req->zero || req->unaligned) && (trb->ctrl & DWC3_TRB_CTRL_HWO)) {
2263                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2264                 return 1;
2265         }
2266
2267         count = trb->size & DWC3_TRB_SIZE_MASK;
2268         req->remaining += count;
2269
2270         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2271                 return 1;
2272
2273         if (event->status & DEPEVT_STATUS_SHORT && !chain)
2274                 return 1;
2275
2276         if (event->status & DEPEVT_STATUS_IOC)
2277                 return 1;
2278
2279         return 0;
2280 }
2281
2282 static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
2283                 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2284                 int status)
2285 {
2286         struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2287         struct scatterlist *sg = req->sg;
2288         struct scatterlist *s;
2289         unsigned int pending = req->num_pending_sgs;
2290         unsigned int i;
2291         int ret = 0;
2292
2293         for_each_sg(sg, s, pending, i) {
2294                 trb = &dep->trb_pool[dep->trb_dequeue];
2295
2296                 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2297                         break;
2298
2299                 req->sg = sg_next(s);
2300                 req->num_pending_sgs--;
2301
2302                 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
2303                                 trb, event, status, true);
2304                 if (ret)
2305                         break;
2306         }
2307
2308         return ret;
2309 }
2310
2311 static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
2312                 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2313                 int status)
2314 {
2315         struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2316
2317         return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
2318                         event, status, false);
2319 }
2320
2321 static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
2322 {
2323         return req->request.actual == req->request.length;
2324 }
2325
2326 static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
2327                 const struct dwc3_event_depevt *event,
2328                 struct dwc3_request *req, int status)
2329 {
2330         int ret;
2331
2332         if (req->num_pending_sgs)
2333                 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
2334                                 status);
2335         else
2336                 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2337                                 status);
2338
2339         if (req->unaligned || req->zero) {
2340                 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2341                                 status);
2342                 req->unaligned = false;
2343                 req->zero = false;
2344         }
2345
2346         req->request.actual = req->request.length - req->remaining;
2347
2348         if (!dwc3_gadget_ep_request_completed(req) &&
2349                         req->num_pending_sgs) {
2350                 __dwc3_gadget_kick_transfer(dep);
2351                 goto out;
2352         }
2353
2354         dwc3_gadget_giveback(dep, req, status);
2355
2356 out:
2357         return ret;
2358 }
2359
2360 static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
2361                 const struct dwc3_event_depevt *event, int status)
2362 {
2363         struct dwc3_request     *req;
2364         struct dwc3_request     *tmp;
2365
2366         list_for_each_entry_safe(req, tmp, &dep->started_list, list) {
2367                 int ret;
2368
2369                 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
2370                                 req, status);
2371                 if (ret)
2372                         break;
2373         }
2374 }
2375
2376 static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
2377                 const struct dwc3_event_depevt *event)
2378 {
2379         dep->frame_number = event->parameters;
2380 }
2381
2382 static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
2383                 const struct dwc3_event_depevt *event)
2384 {
2385         struct dwc3             *dwc = dep->dwc;
2386         unsigned                status = 0;
2387         bool                    stop = false;
2388
2389         dwc3_gadget_endpoint_frame_from_event(dep, event);
2390
2391         if (event->status & DEPEVT_STATUS_BUSERR)
2392                 status = -ECONNRESET;
2393
2394         if (event->status & DEPEVT_STATUS_MISSED_ISOC) {
2395                 status = -EXDEV;
2396
2397                 if (list_empty(&dep->started_list))
2398                         stop = true;
2399         }
2400
2401         dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
2402
2403         if (stop) {
2404                 dwc3_stop_active_transfer(dep, true);
2405                 dep->flags = DWC3_EP_ENABLED;
2406         }
2407
2408         /*
2409          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2410          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2411          */
2412         if (dwc->revision < DWC3_REVISION_183A) {
2413                 u32             reg;
2414                 int             i;
2415
2416                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2417                         dep = dwc->eps[i];
2418
2419                         if (!(dep->flags & DWC3_EP_ENABLED))
2420                                 continue;
2421
2422                         if (!list_empty(&dep->started_list))
2423                                 return;
2424                 }
2425
2426                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2427                 reg |= dwc->u1u2;
2428                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2429
2430                 dwc->u1u2 = 0;
2431         }
2432 }
2433
2434 static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
2435                 const struct dwc3_event_depevt *event)
2436 {
2437         dwc3_gadget_endpoint_frame_from_event(dep, event);
2438         __dwc3_gadget_start_isoc(dep);
2439 }
2440
2441 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2442                 const struct dwc3_event_depevt *event)
2443 {
2444         struct dwc3_ep          *dep;
2445         u8                      epnum = event->endpoint_number;
2446         u8                      cmd;
2447
2448         dep = dwc->eps[epnum];
2449
2450         if (!(dep->flags & DWC3_EP_ENABLED)) {
2451                 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2452                         return;
2453
2454                 /* Handle only EPCMDCMPLT when EP disabled */
2455                 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2456                         return;
2457         }
2458
2459         if (epnum == 0 || epnum == 1) {
2460                 dwc3_ep0_interrupt(dwc, event);
2461                 return;
2462         }
2463
2464         switch (event->endpoint_event) {
2465         case DWC3_DEPEVT_XFERINPROGRESS:
2466                 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
2467                 break;
2468         case DWC3_DEPEVT_XFERNOTREADY:
2469                 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
2470                 break;
2471         case DWC3_DEPEVT_EPCMDCMPLT:
2472                 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2473
2474                 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2475                         dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2476                         wake_up(&dep->wait_end_transfer);
2477                 }
2478                 break;
2479         case DWC3_DEPEVT_STREAMEVT:
2480         case DWC3_DEPEVT_XFERCOMPLETE:
2481         case DWC3_DEPEVT_RXTXFIFOEVT:
2482                 break;
2483         }
2484 }
2485
2486 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2487 {
2488         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2489                 spin_unlock(&dwc->lock);
2490                 dwc->gadget_driver->disconnect(&dwc->gadget);
2491                 spin_lock(&dwc->lock);
2492         }
2493 }
2494
2495 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2496 {
2497         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2498                 spin_unlock(&dwc->lock);
2499                 dwc->gadget_driver->suspend(&dwc->gadget);
2500                 spin_lock(&dwc->lock);
2501         }
2502 }
2503
2504 static void dwc3_resume_gadget(struct dwc3 *dwc)
2505 {
2506         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2507                 spin_unlock(&dwc->lock);
2508                 dwc->gadget_driver->resume(&dwc->gadget);
2509                 spin_lock(&dwc->lock);
2510         }
2511 }
2512
2513 static void dwc3_reset_gadget(struct dwc3 *dwc)
2514 {
2515         if (!dwc->gadget_driver)
2516                 return;
2517
2518         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2519                 spin_unlock(&dwc->lock);
2520                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2521                 spin_lock(&dwc->lock);
2522         }
2523 }
2524
2525 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force)
2526 {
2527         struct dwc3 *dwc = dep->dwc;
2528         struct dwc3_gadget_ep_cmd_params params;
2529         u32 cmd;
2530         int ret;
2531
2532         if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2533             !dep->resource_index)
2534                 return;
2535
2536         /*
2537          * NOTICE: We are violating what the Databook says about the
2538          * EndTransfer command. Ideally we would _always_ wait for the
2539          * EndTransfer Command Completion IRQ, but that's causing too
2540          * much trouble synchronizing between us and gadget driver.
2541          *
2542          * We have discussed this with the IP Provider and it was
2543          * suggested to giveback all requests here, but give HW some
2544          * extra time to synchronize with the interconnect. We're using
2545          * an arbitrary 100us delay for that.
2546          *
2547          * Note also that a similar handling was tested by Synopsys
2548          * (thanks a lot Paul) and nothing bad has come out of it.
2549          * In short, what we're doing is:
2550          *
2551          * - Issue EndTransfer WITH CMDIOC bit set
2552          * - Wait 100us
2553          *
2554          * As of IP version 3.10a of the DWC_usb3 IP, the controller
2555          * supports a mode to work around the above limitation. The
2556          * software can poll the CMDACT bit in the DEPCMD register
2557          * after issuing a EndTransfer command. This mode is enabled
2558          * by writing GUCTL2[14]. This polling is already done in the
2559          * dwc3_send_gadget_ep_cmd() function so if the mode is
2560          * enabled, the EndTransfer command will have completed upon
2561          * returning from this function and we don't need to delay for
2562          * 100us.
2563          *
2564          * This mode is NOT available on the DWC_usb31 IP.
2565          */
2566
2567         cmd = DWC3_DEPCMD_ENDTRANSFER;
2568         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2569         cmd |= DWC3_DEPCMD_CMDIOC;
2570         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2571         memset(&params, 0, sizeof(params));
2572         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
2573         WARN_ON_ONCE(ret);
2574         dep->resource_index = 0;
2575
2576         if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2577                 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
2578                 udelay(100);
2579         }
2580 }
2581
2582 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2583 {
2584         u32 epnum;
2585
2586         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2587                 struct dwc3_ep *dep;
2588                 int ret;
2589
2590                 dep = dwc->eps[epnum];
2591                 if (!dep)
2592                         continue;
2593
2594                 if (!(dep->flags & DWC3_EP_STALL))
2595                         continue;
2596
2597                 dep->flags &= ~DWC3_EP_STALL;
2598
2599                 ret = dwc3_send_clear_stall_ep_cmd(dep);
2600                 WARN_ON_ONCE(ret);
2601         }
2602 }
2603
2604 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2605 {
2606         int                     reg;
2607
2608         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2609         reg &= ~DWC3_DCTL_INITU1ENA;
2610         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2611
2612         reg &= ~DWC3_DCTL_INITU2ENA;
2613         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2614
2615         dwc3_disconnect_gadget(dwc);
2616
2617         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2618         dwc->setup_packet_pending = false;
2619         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2620
2621         dwc->connected = false;
2622 }
2623
2624 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2625 {
2626         u32                     reg;
2627
2628         dwc->connected = true;
2629
2630         /*
2631          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2632          * would cause a missing Disconnect Event if there's a
2633          * pending Setup Packet in the FIFO.
2634          *
2635          * There's no suggested workaround on the official Bug
2636          * report, which states that "unless the driver/application
2637          * is doing any special handling of a disconnect event,
2638          * there is no functional issue".
2639          *
2640          * Unfortunately, it turns out that we _do_ some special
2641          * handling of a disconnect event, namely complete all
2642          * pending transfers, notify gadget driver of the
2643          * disconnection, and so on.
2644          *
2645          * Our suggested workaround is to follow the Disconnect
2646          * Event steps here, instead, based on a setup_packet_pending
2647          * flag. Such flag gets set whenever we have a SETUP_PENDING
2648          * status for EP0 TRBs and gets cleared on XferComplete for the
2649          * same endpoint.
2650          *
2651          * Refers to:
2652          *
2653          * STAR#9000466709: RTL: Device : Disconnect event not
2654          * generated if setup packet pending in FIFO
2655          */
2656         if (dwc->revision < DWC3_REVISION_188A) {
2657                 if (dwc->setup_packet_pending)
2658                         dwc3_gadget_disconnect_interrupt(dwc);
2659         }
2660
2661         dwc3_reset_gadget(dwc);
2662
2663         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2664         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2665         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2666         dwc->test_mode = false;
2667         dwc3_clear_stall_all_ep(dwc);
2668
2669         /* Reset device address to zero */
2670         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2671         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2672         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2673 }
2674
2675 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2676 {
2677         struct dwc3_ep          *dep;
2678         int                     ret;
2679         u32                     reg;
2680         u8                      speed;
2681
2682         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2683         speed = reg & DWC3_DSTS_CONNECTSPD;
2684         dwc->speed = speed;
2685
2686         /*
2687          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2688          * each time on Connect Done.
2689          *
2690          * Currently we always use the reset value. If any platform
2691          * wants to set this to a different value, we need to add a
2692          * setting and update GCTL.RAMCLKSEL here.
2693          */
2694
2695         switch (speed) {
2696         case DWC3_DSTS_SUPERSPEED_PLUS:
2697                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2698                 dwc->gadget.ep0->maxpacket = 512;
2699                 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2700                 break;
2701         case DWC3_DSTS_SUPERSPEED:
2702                 /*
2703                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2704                  * would cause a missing USB3 Reset event.
2705                  *
2706                  * In such situations, we should force a USB3 Reset
2707                  * event by calling our dwc3_gadget_reset_interrupt()
2708                  * routine.
2709                  *
2710                  * Refers to:
2711                  *
2712                  * STAR#9000483510: RTL: SS : USB3 reset event may
2713                  * not be generated always when the link enters poll
2714                  */
2715                 if (dwc->revision < DWC3_REVISION_190A)
2716                         dwc3_gadget_reset_interrupt(dwc);
2717
2718                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2719                 dwc->gadget.ep0->maxpacket = 512;
2720                 dwc->gadget.speed = USB_SPEED_SUPER;
2721                 break;
2722         case DWC3_DSTS_HIGHSPEED:
2723                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2724                 dwc->gadget.ep0->maxpacket = 64;
2725                 dwc->gadget.speed = USB_SPEED_HIGH;
2726                 break;
2727         case DWC3_DSTS_FULLSPEED:
2728                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2729                 dwc->gadget.ep0->maxpacket = 64;
2730                 dwc->gadget.speed = USB_SPEED_FULL;
2731                 break;
2732         case DWC3_DSTS_LOWSPEED:
2733                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2734                 dwc->gadget.ep0->maxpacket = 8;
2735                 dwc->gadget.speed = USB_SPEED_LOW;
2736                 break;
2737         }
2738
2739         dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket;
2740
2741         /* Enable USB2 LPM Capability */
2742
2743         if ((dwc->revision > DWC3_REVISION_194A) &&
2744             (speed != DWC3_DSTS_SUPERSPEED) &&
2745             (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2746                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2747                 reg |= DWC3_DCFG_LPM_CAP;
2748                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2749
2750                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2751                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2752
2753                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2754
2755                 /*
2756                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2757                  * DCFG.LPMCap is set, core responses with an ACK and the
2758                  * BESL value in the LPM token is less than or equal to LPM
2759                  * NYET threshold.
2760                  */
2761                 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2762                                 && dwc->has_lpm_erratum,
2763                                 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
2764
2765                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2766                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2767
2768                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2769         } else {
2770                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2771                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2772                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2773         }
2774
2775         dep = dwc->eps[0];
2776         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2777         if (ret) {
2778                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2779                 return;
2780         }
2781
2782         dep = dwc->eps[1];
2783         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2784         if (ret) {
2785                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2786                 return;
2787         }
2788
2789         /*
2790          * Configure PHY via GUSB3PIPECTLn if required.
2791          *
2792          * Update GTXFIFOSIZn
2793          *
2794          * In both cases reset values should be sufficient.
2795          */
2796 }
2797
2798 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2799 {
2800         /*
2801          * TODO take core out of low power mode when that's
2802          * implemented.
2803          */
2804
2805         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2806                 spin_unlock(&dwc->lock);
2807                 dwc->gadget_driver->resume(&dwc->gadget);
2808                 spin_lock(&dwc->lock);
2809         }
2810 }
2811
2812 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2813                 unsigned int evtinfo)
2814 {
2815         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2816         unsigned int            pwropt;
2817
2818         /*
2819          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2820          * Hibernation mode enabled which would show up when device detects
2821          * host-initiated U3 exit.
2822          *
2823          * In that case, device will generate a Link State Change Interrupt
2824          * from U3 to RESUME which is only necessary if Hibernation is
2825          * configured in.
2826          *
2827          * There are no functional changes due to such spurious event and we
2828          * just need to ignore it.
2829          *
2830          * Refers to:
2831          *
2832          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2833          * operational mode
2834          */
2835         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2836         if ((dwc->revision < DWC3_REVISION_250A) &&
2837                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2838                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2839                                 (next == DWC3_LINK_STATE_RESUME)) {
2840                         return;
2841                 }
2842         }
2843
2844         /*
2845          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2846          * on the link partner, the USB session might do multiple entry/exit
2847          * of low power states before a transfer takes place.
2848          *
2849          * Due to this problem, we might experience lower throughput. The
2850          * suggested workaround is to disable DCTL[12:9] bits if we're
2851          * transitioning from U1/U2 to U0 and enable those bits again
2852          * after a transfer completes and there are no pending transfers
2853          * on any of the enabled endpoints.
2854          *
2855          * This is the first half of that workaround.
2856          *
2857          * Refers to:
2858          *
2859          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2860          * core send LGO_Ux entering U0
2861          */
2862         if (dwc->revision < DWC3_REVISION_183A) {
2863                 if (next == DWC3_LINK_STATE_U0) {
2864                         u32     u1u2;
2865                         u32     reg;
2866
2867                         switch (dwc->link_state) {
2868                         case DWC3_LINK_STATE_U1:
2869                         case DWC3_LINK_STATE_U2:
2870                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2871                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2872                                                 | DWC3_DCTL_ACCEPTU2ENA
2873                                                 | DWC3_DCTL_INITU1ENA
2874                                                 | DWC3_DCTL_ACCEPTU1ENA);
2875
2876                                 if (!dwc->u1u2)
2877                                         dwc->u1u2 = reg & u1u2;
2878
2879                                 reg &= ~u1u2;
2880
2881                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2882                                 break;
2883                         default:
2884                                 /* do nothing */
2885                                 break;
2886                         }
2887                 }
2888         }
2889
2890         switch (next) {
2891         case DWC3_LINK_STATE_U1:
2892                 if (dwc->speed == USB_SPEED_SUPER)
2893                         dwc3_suspend_gadget(dwc);
2894                 break;
2895         case DWC3_LINK_STATE_U2:
2896         case DWC3_LINK_STATE_U3:
2897                 dwc3_suspend_gadget(dwc);
2898                 break;
2899         case DWC3_LINK_STATE_RESUME:
2900                 dwc3_resume_gadget(dwc);
2901                 break;
2902         default:
2903                 /* do nothing */
2904                 break;
2905         }
2906
2907         dwc->link_state = next;
2908 }
2909
2910 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
2911                                           unsigned int evtinfo)
2912 {
2913         enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2914
2915         if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
2916                 dwc3_suspend_gadget(dwc);
2917
2918         dwc->link_state = next;
2919 }
2920
2921 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2922                 unsigned int evtinfo)
2923 {
2924         unsigned int is_ss = evtinfo & BIT(4);
2925
2926         /*
2927          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2928          * have a known issue which can cause USB CV TD.9.23 to fail
2929          * randomly.
2930          *
2931          * Because of this issue, core could generate bogus hibernation
2932          * events which SW needs to ignore.
2933          *
2934          * Refers to:
2935          *
2936          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2937          * Device Fallback from SuperSpeed
2938          */
2939         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2940                 return;
2941
2942         /* enter hibernation here */
2943 }
2944
2945 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2946                 const struct dwc3_event_devt *event)
2947 {
2948         switch (event->type) {
2949         case DWC3_DEVICE_EVENT_DISCONNECT:
2950                 dwc3_gadget_disconnect_interrupt(dwc);
2951                 break;
2952         case DWC3_DEVICE_EVENT_RESET:
2953                 dwc3_gadget_reset_interrupt(dwc);
2954                 break;
2955         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2956                 dwc3_gadget_conndone_interrupt(dwc);
2957                 break;
2958         case DWC3_DEVICE_EVENT_WAKEUP:
2959                 dwc3_gadget_wakeup_interrupt(dwc);
2960                 break;
2961         case DWC3_DEVICE_EVENT_HIBER_REQ:
2962                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2963                                         "unexpected hibernation event\n"))
2964                         break;
2965
2966                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2967                 break;
2968         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2969                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2970                 break;
2971         case DWC3_DEVICE_EVENT_EOPF:
2972                 /* It changed to be suspend event for version 2.30a and above */
2973                 if (dwc->revision >= DWC3_REVISION_230A) {
2974                         /*
2975                          * Ignore suspend event until the gadget enters into
2976                          * USB_STATE_CONFIGURED state.
2977                          */
2978                         if (dwc->gadget.state >= USB_STATE_CONFIGURED)
2979                                 dwc3_gadget_suspend_interrupt(dwc,
2980                                                 event->event_info);
2981                 }
2982                 break;
2983         case DWC3_DEVICE_EVENT_SOF:
2984         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2985         case DWC3_DEVICE_EVENT_CMD_CMPL:
2986         case DWC3_DEVICE_EVENT_OVERFLOW:
2987                 break;
2988         default:
2989                 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2990         }
2991 }
2992
2993 static void dwc3_process_event_entry(struct dwc3 *dwc,
2994                 const union dwc3_event *event)
2995 {
2996         trace_dwc3_event(event->raw, dwc);
2997
2998         if (!event->type.is_devspec)
2999                 dwc3_endpoint_interrupt(dwc, &event->depevt);
3000         else if (event->type.type == DWC3_EVENT_TYPE_DEV)
3001                 dwc3_gadget_interrupt(dwc, &event->devt);
3002         else
3003                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
3004 }
3005
3006 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3007 {
3008         struct dwc3 *dwc = evt->dwc;
3009         irqreturn_t ret = IRQ_NONE;
3010         int left;
3011         u32 reg;
3012
3013         left = evt->count;
3014
3015         if (!(evt->flags & DWC3_EVENT_PENDING))
3016                 return IRQ_NONE;
3017
3018         while (left > 0) {
3019                 union dwc3_event event;
3020
3021                 event.raw = *(u32 *) (evt->cache + evt->lpos);
3022
3023                 dwc3_process_event_entry(dwc, &event);
3024
3025                 /*
3026                  * FIXME we wrap around correctly to the next entry as
3027                  * almost all entries are 4 bytes in size. There is one
3028                  * entry which has 12 bytes which is a regular entry
3029                  * followed by 8 bytes data. ATM I don't know how
3030                  * things are organized if we get next to the a
3031                  * boundary so I worry about that once we try to handle
3032                  * that.
3033                  */
3034                 evt->lpos = (evt->lpos + 4) % evt->length;
3035                 left -= 4;
3036         }
3037
3038         evt->count = 0;
3039         evt->flags &= ~DWC3_EVENT_PENDING;
3040         ret = IRQ_HANDLED;
3041
3042         /* Unmask interrupt */
3043         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3044         reg &= ~DWC3_GEVNTSIZ_INTMASK;
3045         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3046
3047         if (dwc->imod_interval) {
3048                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3049                 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3050         }
3051
3052         return ret;
3053 }
3054
3055 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3056 {
3057         struct dwc3_event_buffer *evt = _evt;
3058         struct dwc3 *dwc = evt->dwc;
3059         unsigned long flags;
3060         irqreturn_t ret = IRQ_NONE;
3061
3062         spin_lock_irqsave(&dwc->lock, flags);
3063         ret = dwc3_process_event_buf(evt);
3064         spin_unlock_irqrestore(&dwc->lock, flags);
3065
3066         return ret;
3067 }
3068
3069 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3070 {
3071         struct dwc3 *dwc = evt->dwc;
3072         u32 amount;
3073         u32 count;
3074         u32 reg;
3075
3076         if (pm_runtime_suspended(dwc->dev)) {
3077                 pm_runtime_get(dwc->dev);
3078                 disable_irq_nosync(dwc->irq_gadget);
3079                 dwc->pending_events = true;
3080                 return IRQ_HANDLED;
3081         }
3082
3083         /*
3084          * With PCIe legacy interrupt, test shows that top-half irq handler can
3085          * be called again after HW interrupt deassertion. Check if bottom-half
3086          * irq event handler completes before caching new event to prevent
3087          * losing events.
3088          */
3089         if (evt->flags & DWC3_EVENT_PENDING)
3090                 return IRQ_HANDLED;
3091
3092         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3093         count &= DWC3_GEVNTCOUNT_MASK;
3094         if (!count)
3095                 return IRQ_NONE;
3096
3097         evt->count = count;
3098         evt->flags |= DWC3_EVENT_PENDING;
3099
3100         /* Mask interrupt */
3101         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3102         reg |= DWC3_GEVNTSIZ_INTMASK;
3103         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3104
3105         amount = min(count, evt->length - evt->lpos);
3106         memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3107
3108         if (amount < count)
3109                 memcpy(evt->cache, evt->buf, count - amount);
3110
3111         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3112
3113         return IRQ_WAKE_THREAD;
3114 }
3115
3116 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3117 {
3118         struct dwc3_event_buffer        *evt = _evt;
3119
3120         return dwc3_check_event_buf(evt);
3121 }
3122
3123 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3124 {
3125         struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3126         int irq;
3127
3128         irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
3129         if (irq > 0)
3130                 goto out;
3131
3132         if (irq == -EPROBE_DEFER)
3133                 goto out;
3134
3135         irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
3136         if (irq > 0)
3137                 goto out;
3138
3139         if (irq == -EPROBE_DEFER)
3140                 goto out;
3141
3142         irq = platform_get_irq(dwc3_pdev, 0);
3143         if (irq > 0)
3144                 goto out;
3145
3146         if (irq != -EPROBE_DEFER)
3147                 dev_err(dwc->dev, "missing peripheral IRQ\n");
3148
3149         if (!irq)
3150                 irq = -EINVAL;
3151
3152 out:
3153         return irq;
3154 }
3155
3156 /**
3157  * dwc3_gadget_init - initializes gadget related registers
3158  * @dwc: pointer to our controller context structure
3159  *
3160  * Returns 0 on success otherwise negative errno.
3161  */
3162 int dwc3_gadget_init(struct dwc3 *dwc)
3163 {
3164         int ret;
3165         int irq;
3166
3167         irq = dwc3_gadget_get_irq(dwc);
3168         if (irq < 0) {
3169                 ret = irq;
3170                 goto err0;
3171         }
3172
3173         dwc->irq_gadget = irq;
3174
3175         dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3176                                           sizeof(*dwc->ep0_trb) * 2,
3177                                           &dwc->ep0_trb_addr, GFP_KERNEL);
3178         if (!dwc->ep0_trb) {
3179                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3180                 ret = -ENOMEM;
3181                 goto err0;
3182         }
3183
3184         dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3185         if (!dwc->setup_buf) {
3186                 ret = -ENOMEM;
3187                 goto err1;
3188         }
3189
3190         dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3191                         &dwc->bounce_addr, GFP_KERNEL);
3192         if (!dwc->bounce) {
3193                 ret = -ENOMEM;
3194                 goto err2;
3195         }
3196
3197         init_completion(&dwc->ep0_in_setup);
3198
3199         dwc->gadget.ops                 = &dwc3_gadget_ops;
3200         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
3201         dwc->gadget.sg_supported        = true;
3202         dwc->gadget.name                = "dwc3-gadget";
3203         dwc->gadget.is_otg              = dwc->dr_mode == USB_DR_MODE_OTG;
3204
3205         /*
3206          * FIXME We might be setting max_speed to <SUPER, however versions
3207          * <2.20a of dwc3 have an issue with metastability (documented
3208          * elsewhere in this driver) which tells us we can't set max speed to
3209          * anything lower than SUPER.
3210          *
3211          * Because gadget.max_speed is only used by composite.c and function
3212          * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3213          * to happen so we avoid sending SuperSpeed Capability descriptor
3214          * together with our BOS descriptor as that could confuse host into
3215          * thinking we can handle super speed.
3216          *
3217          * Note that, in fact, we won't even support GetBOS requests when speed
3218          * is less than super speed because we don't have means, yet, to tell
3219          * composite.c that we are USB 2.0 + LPM ECN.
3220          */
3221         if (dwc->revision < DWC3_REVISION_220A &&
3222             !dwc->dis_metastability_quirk)
3223                 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
3224                                 dwc->revision);
3225
3226         dwc->gadget.max_speed           = dwc->maximum_speed;
3227
3228         /*
3229          * REVISIT: Here we should clear all pending IRQs to be
3230          * sure we're starting from a well known location.
3231          */
3232
3233         ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
3234         if (ret)
3235                 goto err3;
3236
3237         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3238         if (ret) {
3239                 dev_err(dwc->dev, "failed to register udc\n");
3240                 goto err4;
3241         }
3242
3243         return 0;
3244
3245 err4:
3246         dwc3_gadget_free_endpoints(dwc);
3247
3248 err3:
3249         dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3250                         dwc->bounce_addr);
3251
3252 err2:
3253         kfree(dwc->setup_buf);
3254
3255 err1:
3256         dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3257                         dwc->ep0_trb, dwc->ep0_trb_addr);
3258
3259 err0:
3260         return ret;
3261 }
3262
3263 /* -------------------------------------------------------------------------- */
3264
3265 void dwc3_gadget_exit(struct dwc3 *dwc)
3266 {
3267         usb_del_gadget_udc(&dwc->gadget);
3268         dwc3_gadget_free_endpoints(dwc);
3269         dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3270                           dwc->bounce_addr);
3271         kfree(dwc->setup_buf);
3272         dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3273                           dwc->ep0_trb, dwc->ep0_trb_addr);
3274 }
3275
3276 int dwc3_gadget_suspend(struct dwc3 *dwc)
3277 {
3278         if (!dwc->gadget_driver)
3279                 return 0;
3280
3281         dwc3_gadget_run_stop(dwc, false, false);
3282         dwc3_disconnect_gadget(dwc);
3283         __dwc3_gadget_stop(dwc);
3284
3285         return 0;
3286 }
3287
3288 int dwc3_gadget_resume(struct dwc3 *dwc)
3289 {
3290         int                     ret;
3291
3292         if (!dwc->gadget_driver)
3293                 return 0;
3294
3295         ret = __dwc3_gadget_start(dwc);
3296         if (ret < 0)
3297                 goto err0;
3298
3299         ret = dwc3_gadget_run_stop(dwc, true, false);
3300         if (ret < 0)
3301                 goto err1;
3302
3303         return 0;
3304
3305 err1:
3306         __dwc3_gadget_stop(dwc);
3307
3308 err0:
3309         return ret;
3310 }
3311
3312 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3313 {
3314         if (dwc->pending_events) {
3315                 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3316                 dwc->pending_events = false;
3317                 enable_irq(dwc->irq_gadget);
3318         }
3319 }