1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 * Inspired by dwc3-of-simple.c
7 #include <linux/acpi.h>
10 #include <linux/clk.h>
11 #include <linux/irq.h>
12 #include <linux/of_clk.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/extcon.h>
16 #include <linux/interconnect.h>
17 #include <linux/of_platform.h>
18 #include <linux/platform_device.h>
19 #include <linux/phy/phy.h>
20 #include <linux/usb/of.h>
21 #include <linux/reset.h>
22 #include <linux/iopoll.h>
26 /* USB QSCRATCH Hardware registers */
27 #define QSCRATCH_HS_PHY_CTRL 0x10
28 #define UTMI_OTG_VBUS_VALID BIT(20)
29 #define SW_SESSVLD_SEL BIT(28)
31 #define QSCRATCH_SS_PHY_CTRL 0x30
32 #define LANE0_PWR_PRESENT BIT(24)
34 #define QSCRATCH_GENERAL_CFG 0x08
35 #define PIPE_UTMI_CLK_SEL BIT(0)
36 #define PIPE3_PHYSTATUS_SW BIT(3)
37 #define PIPE_UTMI_CLK_DIS BIT(8)
39 #define PWR_EVNT_IRQ_STAT_REG 0x58
40 #define PWR_EVNT_LPM_IN_L2_MASK BIT(4)
41 #define PWR_EVNT_LPM_OUT_L2_MASK BIT(5)
43 #define SDM845_QSCRATCH_BASE_OFFSET 0xf8800
44 #define SDM845_QSCRATCH_SIZE 0x400
45 #define SDM845_DWC3_CORE_SIZE 0xcd00
47 /* Interconnect path bandwidths in MBps */
48 #define USB_MEMORY_AVG_HS_BW MBps_to_icc(240)
49 #define USB_MEMORY_PEAK_HS_BW MBps_to_icc(700)
50 #define USB_MEMORY_AVG_SS_BW MBps_to_icc(1000)
51 #define USB_MEMORY_PEAK_SS_BW MBps_to_icc(2500)
52 #define APPS_USB_AVG_BW 0
53 #define APPS_USB_PEAK_BW MBps_to_icc(40)
55 struct dwc3_acpi_pdata {
56 u32 qscratch_base_offset;
57 u32 qscratch_base_size;
58 u32 dwc3_core_base_size;
60 int dp_hs_phy_irq_index;
61 int dm_hs_phy_irq_index;
68 void __iomem *qscratch_base;
69 struct platform_device *dwc3;
70 struct platform_device *urs_usb;
73 struct reset_control *resets;
80 struct extcon_dev *edev;
81 struct extcon_dev *host_edev;
82 struct notifier_block vbus_nb;
83 struct notifier_block host_nb;
85 const struct dwc3_acpi_pdata *acpi_pdata;
87 enum usb_dr_mode mode;
90 struct icc_path *icc_path_ddr;
91 struct icc_path *icc_path_apps;
94 static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
98 reg = readl(base + offset);
100 writel(reg, base + offset);
102 /* ensure that above write is through */
103 readl(base + offset);
106 static inline void dwc3_qcom_clrbits(void __iomem *base, u32 offset, u32 val)
110 reg = readl(base + offset);
112 writel(reg, base + offset);
114 /* ensure that above write is through */
115 readl(base + offset);
118 static void dwc3_qcom_vbus_overrride_enable(struct dwc3_qcom *qcom, bool enable)
121 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
123 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
124 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
126 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
128 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
129 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
133 static int dwc3_qcom_vbus_notifier(struct notifier_block *nb,
134 unsigned long event, void *ptr)
136 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, vbus_nb);
138 /* enable vbus override for device mode */
139 dwc3_qcom_vbus_overrride_enable(qcom, event);
140 qcom->mode = event ? USB_DR_MODE_PERIPHERAL : USB_DR_MODE_HOST;
145 static int dwc3_qcom_host_notifier(struct notifier_block *nb,
146 unsigned long event, void *ptr)
148 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, host_nb);
150 /* disable vbus override in host mode */
151 dwc3_qcom_vbus_overrride_enable(qcom, !event);
152 qcom->mode = event ? USB_DR_MODE_HOST : USB_DR_MODE_PERIPHERAL;
157 static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom)
159 struct device *dev = qcom->dev;
160 struct extcon_dev *host_edev;
163 if (!of_property_read_bool(dev->of_node, "extcon"))
166 qcom->edev = extcon_get_edev_by_phandle(dev, 0);
167 if (IS_ERR(qcom->edev))
168 return PTR_ERR(qcom->edev);
170 qcom->vbus_nb.notifier_call = dwc3_qcom_vbus_notifier;
172 qcom->host_edev = extcon_get_edev_by_phandle(dev, 1);
173 if (IS_ERR(qcom->host_edev))
174 qcom->host_edev = NULL;
176 ret = devm_extcon_register_notifier(dev, qcom->edev, EXTCON_USB,
179 dev_err(dev, "VBUS notifier register failed\n");
184 host_edev = qcom->host_edev;
186 host_edev = qcom->edev;
188 qcom->host_nb.notifier_call = dwc3_qcom_host_notifier;
189 ret = devm_extcon_register_notifier(dev, host_edev, EXTCON_USB_HOST,
192 dev_err(dev, "Host notifier register failed\n");
196 /* Update initial VBUS override based on extcon state */
197 if (extcon_get_state(qcom->edev, EXTCON_USB) ||
198 !extcon_get_state(host_edev, EXTCON_USB_HOST))
199 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, true, qcom->edev);
201 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, false, qcom->edev);
206 static int dwc3_qcom_interconnect_enable(struct dwc3_qcom *qcom)
210 ret = icc_enable(qcom->icc_path_ddr);
214 ret = icc_enable(qcom->icc_path_apps);
216 icc_disable(qcom->icc_path_ddr);
221 static int dwc3_qcom_interconnect_disable(struct dwc3_qcom *qcom)
225 ret = icc_disable(qcom->icc_path_ddr);
229 ret = icc_disable(qcom->icc_path_apps);
231 icc_enable(qcom->icc_path_ddr);
237 * dwc3_qcom_interconnect_init() - Get interconnect path handles
238 * and set bandwidhth.
239 * @qcom: Pointer to the concerned usb core.
242 static int dwc3_qcom_interconnect_init(struct dwc3_qcom *qcom)
244 struct device *dev = qcom->dev;
247 qcom->icc_path_ddr = of_icc_get(dev, "usb-ddr");
248 if (IS_ERR(qcom->icc_path_ddr)) {
249 dev_err(dev, "failed to get usb-ddr path: %ld\n",
250 PTR_ERR(qcom->icc_path_ddr));
251 return PTR_ERR(qcom->icc_path_ddr);
254 qcom->icc_path_apps = of_icc_get(dev, "apps-usb");
255 if (IS_ERR(qcom->icc_path_apps)) {
256 dev_err(dev, "failed to get apps-usb path: %ld\n",
257 PTR_ERR(qcom->icc_path_apps));
258 return PTR_ERR(qcom->icc_path_apps);
261 if (usb_get_maximum_speed(&qcom->dwc3->dev) >= USB_SPEED_SUPER ||
262 usb_get_maximum_speed(&qcom->dwc3->dev) == USB_SPEED_UNKNOWN)
263 ret = icc_set_bw(qcom->icc_path_ddr,
264 USB_MEMORY_AVG_SS_BW, USB_MEMORY_PEAK_SS_BW);
266 ret = icc_set_bw(qcom->icc_path_ddr,
267 USB_MEMORY_AVG_HS_BW, USB_MEMORY_PEAK_HS_BW);
270 dev_err(dev, "failed to set bandwidth for usb-ddr path: %d\n", ret);
274 ret = icc_set_bw(qcom->icc_path_apps,
275 APPS_USB_AVG_BW, APPS_USB_PEAK_BW);
277 dev_err(dev, "failed to set bandwidth for apps-usb path: %d\n", ret);
285 * dwc3_qcom_interconnect_exit() - Release interconnect path handles
286 * @qcom: Pointer to the concerned usb core.
288 * This function is used to release interconnect path handle.
290 static void dwc3_qcom_interconnect_exit(struct dwc3_qcom *qcom)
292 icc_put(qcom->icc_path_ddr);
293 icc_put(qcom->icc_path_apps);
296 static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom)
298 if (qcom->hs_phy_irq) {
299 disable_irq_wake(qcom->hs_phy_irq);
300 disable_irq_nosync(qcom->hs_phy_irq);
303 if (qcom->dp_hs_phy_irq) {
304 disable_irq_wake(qcom->dp_hs_phy_irq);
305 disable_irq_nosync(qcom->dp_hs_phy_irq);
308 if (qcom->dm_hs_phy_irq) {
309 disable_irq_wake(qcom->dm_hs_phy_irq);
310 disable_irq_nosync(qcom->dm_hs_phy_irq);
313 if (qcom->ss_phy_irq) {
314 disable_irq_wake(qcom->ss_phy_irq);
315 disable_irq_nosync(qcom->ss_phy_irq);
319 static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
321 if (qcom->hs_phy_irq) {
322 enable_irq(qcom->hs_phy_irq);
323 enable_irq_wake(qcom->hs_phy_irq);
326 if (qcom->dp_hs_phy_irq) {
327 enable_irq(qcom->dp_hs_phy_irq);
328 enable_irq_wake(qcom->dp_hs_phy_irq);
331 if (qcom->dm_hs_phy_irq) {
332 enable_irq(qcom->dm_hs_phy_irq);
333 enable_irq_wake(qcom->dm_hs_phy_irq);
336 if (qcom->ss_phy_irq) {
337 enable_irq(qcom->ss_phy_irq);
338 enable_irq_wake(qcom->ss_phy_irq);
342 static int dwc3_qcom_suspend(struct dwc3_qcom *qcom)
347 if (qcom->is_suspended)
350 val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG);
351 if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
352 dev_err(qcom->dev, "HS-PHY not in L2\n");
354 for (i = qcom->num_clocks - 1; i >= 0; i--)
355 clk_disable_unprepare(qcom->clks[i]);
357 ret = dwc3_qcom_interconnect_disable(qcom);
359 dev_warn(qcom->dev, "failed to disable interconnect: %d\n", ret);
361 qcom->is_suspended = true;
362 dwc3_qcom_enable_interrupts(qcom);
367 static int dwc3_qcom_resume(struct dwc3_qcom *qcom)
372 if (!qcom->is_suspended)
375 dwc3_qcom_disable_interrupts(qcom);
377 for (i = 0; i < qcom->num_clocks; i++) {
378 ret = clk_prepare_enable(qcom->clks[i]);
381 clk_disable_unprepare(qcom->clks[i]);
386 ret = dwc3_qcom_interconnect_enable(qcom);
388 dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret);
390 /* Clear existing events from PHY related to L2 in/out */
391 dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG,
392 PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);
394 qcom->is_suspended = false;
399 static irqreturn_t qcom_dwc3_resume_irq(int irq, void *data)
401 struct dwc3_qcom *qcom = data;
402 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
404 /* If pm_suspended then let pm_resume take care of resuming h/w */
405 if (qcom->pm_suspended)
409 pm_runtime_resume(&dwc->xhci->dev);
414 static void dwc3_qcom_select_utmi_clk(struct dwc3_qcom *qcom)
416 /* Configure dwc3 to use UTMI clock as PIPE clock not present */
417 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
420 usleep_range(100, 1000);
422 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
423 PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);
425 usleep_range(100, 1000);
427 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
431 static int dwc3_qcom_get_irq(struct platform_device *pdev,
432 const char *name, int num)
434 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
435 struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb : pdev;
436 struct device_node *np = pdev->dev.of_node;
440 ret = platform_get_irq_byname(pdev_irq, name);
442 ret = platform_get_irq(pdev_irq, num);
447 static int dwc3_qcom_setup_irq(struct platform_device *pdev)
449 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
450 const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
454 irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq",
455 pdata ? pdata->hs_phy_irq_index : -1);
457 /* Keep wakeup interrupts disabled until suspend */
458 irq_set_status_flags(irq, IRQ_NOAUTOEN);
459 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
460 qcom_dwc3_resume_irq,
461 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
462 "qcom_dwc3 HS", qcom);
464 dev_err(qcom->dev, "hs_phy_irq failed: %d\n", ret);
467 qcom->hs_phy_irq = irq;
470 irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq",
471 pdata ? pdata->dp_hs_phy_irq_index : -1);
473 irq_set_status_flags(irq, IRQ_NOAUTOEN);
474 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
475 qcom_dwc3_resume_irq,
476 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
477 "qcom_dwc3 DP_HS", qcom);
479 dev_err(qcom->dev, "dp_hs_phy_irq failed: %d\n", ret);
482 qcom->dp_hs_phy_irq = irq;
485 irq = dwc3_qcom_get_irq(pdev, "dm_hs_phy_irq",
486 pdata ? pdata->dm_hs_phy_irq_index : -1);
488 irq_set_status_flags(irq, IRQ_NOAUTOEN);
489 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
490 qcom_dwc3_resume_irq,
491 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
492 "qcom_dwc3 DM_HS", qcom);
494 dev_err(qcom->dev, "dm_hs_phy_irq failed: %d\n", ret);
497 qcom->dm_hs_phy_irq = irq;
500 irq = dwc3_qcom_get_irq(pdev, "ss_phy_irq",
501 pdata ? pdata->ss_phy_irq_index : -1);
503 irq_set_status_flags(irq, IRQ_NOAUTOEN);
504 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
505 qcom_dwc3_resume_irq,
506 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
507 "qcom_dwc3 SS", qcom);
509 dev_err(qcom->dev, "ss_phy_irq failed: %d\n", ret);
512 qcom->ss_phy_irq = irq;
518 static int dwc3_qcom_clk_init(struct dwc3_qcom *qcom, int count)
520 struct device *dev = qcom->dev;
521 struct device_node *np = dev->of_node;
530 qcom->num_clocks = count;
532 qcom->clks = devm_kcalloc(dev, qcom->num_clocks,
533 sizeof(struct clk *), GFP_KERNEL);
537 for (i = 0; i < qcom->num_clocks; i++) {
541 clk = of_clk_get(np, i);
544 clk_put(qcom->clks[i]);
548 ret = clk_prepare_enable(clk);
551 clk_disable_unprepare(qcom->clks[i]);
552 clk_put(qcom->clks[i]);
565 static const struct property_entry dwc3_qcom_acpi_properties[] = {
566 PROPERTY_ENTRY_STRING("dr_mode", "host"),
570 static const struct software_node dwc3_qcom_swnode = {
571 .properties = dwc3_qcom_acpi_properties,
574 static int dwc3_qcom_acpi_register_core(struct platform_device *pdev)
576 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
577 struct device *dev = &pdev->dev;
578 struct resource *res, *child_res = NULL;
579 struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb :
584 qcom->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
588 qcom->dwc3->dev.parent = dev;
589 qcom->dwc3->dev.type = dev->type;
590 qcom->dwc3->dev.dma_mask = dev->dma_mask;
591 qcom->dwc3->dev.dma_parms = dev->dma_parms;
592 qcom->dwc3->dev.coherent_dma_mask = dev->coherent_dma_mask;
594 child_res = kcalloc(2, sizeof(*child_res), GFP_KERNEL);
598 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
600 dev_err(&pdev->dev, "failed to get memory resource\n");
605 child_res[0].flags = res->flags;
606 child_res[0].start = res->start;
607 child_res[0].end = child_res[0].start +
608 qcom->acpi_pdata->dwc3_core_base_size;
610 irq = platform_get_irq(pdev_irq, 0);
611 child_res[1].flags = IORESOURCE_IRQ;
612 child_res[1].start = child_res[1].end = irq;
614 ret = platform_device_add_resources(qcom->dwc3, child_res, 2);
616 dev_err(&pdev->dev, "failed to add resources\n");
620 ret = device_add_software_node(&qcom->dwc3->dev, &dwc3_qcom_swnode);
622 dev_err(&pdev->dev, "failed to add properties\n");
626 ret = platform_device_add(qcom->dwc3);
628 dev_err(&pdev->dev, "failed to add device\n");
629 device_remove_software_node(&qcom->dwc3->dev);
637 static int dwc3_qcom_of_register_core(struct platform_device *pdev)
639 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
640 struct device_node *np = pdev->dev.of_node, *dwc3_np;
641 struct device *dev = &pdev->dev;
644 dwc3_np = of_get_child_by_name(np, "dwc3");
646 dev_err(dev, "failed to find dwc3 core child\n");
650 ret = of_platform_populate(np, NULL, NULL, dev);
652 dev_err(dev, "failed to register dwc3 core - %d\n", ret);
656 qcom->dwc3 = of_find_device_by_node(dwc3_np);
658 dev_err(dev, "failed to get dwc3 platform device\n");
665 static struct platform_device *
666 dwc3_qcom_create_urs_usb_platdev(struct device *dev)
668 struct fwnode_handle *fwh;
669 struct acpi_device *adev;
674 /* Figure out device id */
675 ret = sscanf(fwnode_get_name(dev->fwnode), "URS%d", &id);
679 /* Find the child using name */
680 snprintf(name, sizeof(name), "USB%d", id);
681 fwh = fwnode_get_named_child_node(dev->fwnode, name);
685 adev = to_acpi_device_node(fwh);
689 return acpi_create_platform_device(adev, NULL);
692 static int dwc3_qcom_probe(struct platform_device *pdev)
694 struct device_node *np = pdev->dev.of_node;
695 struct device *dev = &pdev->dev;
696 struct dwc3_qcom *qcom;
697 struct resource *res, *parent_res = NULL;
699 bool ignore_pipe_clk;
701 qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL);
705 platform_set_drvdata(pdev, qcom);
706 qcom->dev = &pdev->dev;
708 if (has_acpi_companion(dev)) {
709 qcom->acpi_pdata = acpi_device_get_match_data(dev);
710 if (!qcom->acpi_pdata) {
711 dev_err(&pdev->dev, "no supporting ACPI device data\n");
716 qcom->resets = devm_reset_control_array_get_optional_exclusive(dev);
717 if (IS_ERR(qcom->resets)) {
718 ret = PTR_ERR(qcom->resets);
719 dev_err(&pdev->dev, "failed to get resets, err=%d\n", ret);
723 ret = reset_control_assert(qcom->resets);
725 dev_err(&pdev->dev, "failed to assert resets, err=%d\n", ret);
729 usleep_range(10, 1000);
731 ret = reset_control_deassert(qcom->resets);
733 dev_err(&pdev->dev, "failed to deassert resets, err=%d\n", ret);
737 ret = dwc3_qcom_clk_init(qcom, of_clk_get_parent_count(np));
739 dev_err(dev, "failed to get clocks\n");
743 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
748 parent_res = kmemdup(res, sizeof(struct resource), GFP_KERNEL);
752 parent_res->start = res->start +
753 qcom->acpi_pdata->qscratch_base_offset;
754 parent_res->end = parent_res->start +
755 qcom->acpi_pdata->qscratch_base_size;
757 if (qcom->acpi_pdata->is_urs) {
758 qcom->urs_usb = dwc3_qcom_create_urs_usb_platdev(dev);
759 if (!qcom->urs_usb) {
760 dev_err(dev, "failed to create URS USB platdev\n");
766 qcom->qscratch_base = devm_ioremap_resource(dev, parent_res);
767 if (IS_ERR(qcom->qscratch_base)) {
768 dev_err(dev, "failed to map qscratch, err=%d\n", ret);
769 ret = PTR_ERR(qcom->qscratch_base);
773 ret = dwc3_qcom_setup_irq(pdev);
775 dev_err(dev, "failed to setup IRQs, err=%d\n", ret);
780 * Disable pipe_clk requirement if specified. Used when dwc3
781 * operates without SSPHY and only HS/FS/LS modes are supported.
783 ignore_pipe_clk = device_property_read_bool(dev,
784 "qcom,select-utmi-as-pipe-clk");
786 dwc3_qcom_select_utmi_clk(qcom);
789 ret = dwc3_qcom_of_register_core(pdev);
791 ret = dwc3_qcom_acpi_register_core(pdev);
794 dev_err(dev, "failed to register DWC3 Core, err=%d\n", ret);
798 ret = dwc3_qcom_interconnect_init(qcom);
802 qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev);
804 /* enable vbus override for device mode */
805 if (qcom->mode == USB_DR_MODE_PERIPHERAL)
806 dwc3_qcom_vbus_overrride_enable(qcom, true);
808 /* register extcon to override sw_vbus on Vbus change later */
809 ret = dwc3_qcom_register_extcon(qcom);
811 goto interconnect_exit;
813 device_init_wakeup(&pdev->dev, 1);
814 qcom->is_suspended = false;
815 pm_runtime_set_active(dev);
816 pm_runtime_enable(dev);
817 pm_runtime_forbid(dev);
822 dwc3_qcom_interconnect_exit(qcom);
825 of_platform_depopulate(&pdev->dev);
827 platform_device_put(pdev);
829 for (i = qcom->num_clocks - 1; i >= 0; i--) {
830 clk_disable_unprepare(qcom->clks[i]);
831 clk_put(qcom->clks[i]);
834 reset_control_assert(qcom->resets);
839 static int dwc3_qcom_remove(struct platform_device *pdev)
841 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
842 struct device *dev = &pdev->dev;
845 device_remove_software_node(&qcom->dwc3->dev);
846 of_platform_depopulate(dev);
848 for (i = qcom->num_clocks - 1; i >= 0; i--) {
849 clk_disable_unprepare(qcom->clks[i]);
850 clk_put(qcom->clks[i]);
852 qcom->num_clocks = 0;
854 dwc3_qcom_interconnect_exit(qcom);
855 reset_control_assert(qcom->resets);
857 pm_runtime_allow(dev);
858 pm_runtime_disable(dev);
863 static int __maybe_unused dwc3_qcom_pm_suspend(struct device *dev)
865 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
868 ret = dwc3_qcom_suspend(qcom);
870 qcom->pm_suspended = true;
875 static int __maybe_unused dwc3_qcom_pm_resume(struct device *dev)
877 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
880 ret = dwc3_qcom_resume(qcom);
882 qcom->pm_suspended = false;
887 static int __maybe_unused dwc3_qcom_runtime_suspend(struct device *dev)
889 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
891 return dwc3_qcom_suspend(qcom);
894 static int __maybe_unused dwc3_qcom_runtime_resume(struct device *dev)
896 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
898 return dwc3_qcom_resume(qcom);
901 static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = {
902 SET_SYSTEM_SLEEP_PM_OPS(dwc3_qcom_pm_suspend, dwc3_qcom_pm_resume)
903 SET_RUNTIME_PM_OPS(dwc3_qcom_runtime_suspend, dwc3_qcom_runtime_resume,
907 static const struct of_device_id dwc3_qcom_of_match[] = {
908 { .compatible = "qcom,dwc3" },
909 { .compatible = "qcom,msm8996-dwc3" },
910 { .compatible = "qcom,msm8998-dwc3" },
911 { .compatible = "qcom,sdm845-dwc3" },
914 MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match);
917 static const struct dwc3_acpi_pdata sdm845_acpi_pdata = {
918 .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
919 .qscratch_base_size = SDM845_QSCRATCH_SIZE,
920 .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
921 .hs_phy_irq_index = 1,
922 .dp_hs_phy_irq_index = 4,
923 .dm_hs_phy_irq_index = 3,
924 .ss_phy_irq_index = 2
927 static const struct dwc3_acpi_pdata sdm845_acpi_urs_pdata = {
928 .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
929 .qscratch_base_size = SDM845_QSCRATCH_SIZE,
930 .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
931 .hs_phy_irq_index = 1,
932 .dp_hs_phy_irq_index = 4,
933 .dm_hs_phy_irq_index = 3,
934 .ss_phy_irq_index = 2,
938 static const struct acpi_device_id dwc3_qcom_acpi_match[] = {
939 { "QCOM2430", (unsigned long)&sdm845_acpi_pdata },
940 { "QCOM0304", (unsigned long)&sdm845_acpi_urs_pdata },
943 MODULE_DEVICE_TABLE(acpi, dwc3_qcom_acpi_match);
946 static struct platform_driver dwc3_qcom_driver = {
947 .probe = dwc3_qcom_probe,
948 .remove = dwc3_qcom_remove,
951 .pm = &dwc3_qcom_dev_pm_ops,
952 .of_match_table = dwc3_qcom_of_match,
953 .acpi_match_table = ACPI_PTR(dwc3_qcom_acpi_match),
957 module_platform_driver(dwc3_qcom_driver);
959 MODULE_LICENSE("GPL v2");
960 MODULE_DESCRIPTION("DesignWare DWC3 QCOM Glue Driver");