drivers/usb/dwc3/core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * core.c - DesignWare USB3 DRD Controller Core file
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/version.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/slab.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ioport.h>
  21 #include <linux/io.h>
  22 #include <linux/list.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/of.h>
  26 #include <linux/of_graph.h>
  27 #include <linux/acpi.h>
  28 #include <linux/pinctrl/consumer.h>
  29 #include <linux/reset.h>
  30 #include <linux/bitfield.h>
  31
  32 #include <linux/usb/ch9.h>
  33 #include <linux/usb/gadget.h>
  34 #include <linux/usb/of.h>
  35 #include <linux/usb/otg.h>
  36
  37 #include "core.h"
  38 #include "gadget.h"
  39 #include "io.h"
  40
  41 #include "debug.h"
  42 #include "../host/xhci-ext-caps.h"
  43
  44 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY  5000 /* ms */
  45
  46 /**
  47  * dwc3_get_dr_mode - Validates and sets dr_mode
  48  * @dwc: pointer to our context structure
  49  */
  50 static int dwc3_get_dr_mode(struct dwc3 *dwc)
  51 {
  52         enum usb_dr_mode mode;
  53         struct device *dev = dwc->dev;
  54         unsigned int hw_mode;
  55
  56         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
  57                 dwc->dr_mode = USB_DR_MODE_OTG;
  58
  59         mode = dwc->dr_mode;
  60         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
  61
  62         switch (hw_mode) {
  63         case DWC3_GHWPARAMS0_MODE_GADGET:
  64                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
  65                         dev_err(dev,
  66                                 "Controller does not support host mode.\n");
  67                         return -EINVAL;
  68                 }
  69                 mode = USB_DR_MODE_PERIPHERAL;
  70                 break;
  71         case DWC3_GHWPARAMS0_MODE_HOST:
  72                 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
  73                         dev_err(dev,
  74                                 "Controller does not support device mode.\n");
  75                         return -EINVAL;
  76                 }
  77                 mode = USB_DR_MODE_HOST;
  78                 break;
  79         default:
  80                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
  81                         mode = USB_DR_MODE_HOST;
  82                 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
  83                         mode = USB_DR_MODE_PERIPHERAL;
  84
  85                 /*
  86                  * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
  87                  * mode. If the controller supports DRD but the dr_mode is not
  88                  * specified or set to OTG, then set the mode to peripheral.
  89                  */
  90                 if (mode == USB_DR_MODE_OTG && !dwc->edev &&
  91                     (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
  92                      !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
  93                     !DWC3_VER_IS_PRIOR(DWC3, 330A))
  94                         mode = USB_DR_MODE_PERIPHERAL;
  95         }
  96
  97         if (mode != dwc->dr_mode) {
  98                 dev_warn(dev,
  99                          "Configuration mismatch. dr_mode forced to %s\n",
 100                          mode == USB_DR_MODE_HOST ? "host" : "gadget");
 101
 102                 dwc->dr_mode = mode;
 103         }
 104
 105         return 0;
 106 }
 107
 108 void dwc3_enable_susphy(struct dwc3 *dwc, bool enable)
 109 {
 110         u32 reg;
 111
 112         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 113         if (enable && !dwc->dis_u3_susphy_quirk)
 114                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 115         else
 116                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 117
 118         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 119
 120         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 121         if (enable && !dwc->dis_u2_susphy_quirk)
 122                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 123         else
 124                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 125
 126         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 127 }
 128
 129 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
 130 {
 131         u32 reg;
 132
 133         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 134         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
 135         reg |= DWC3_GCTL_PRTCAPDIR(mode);
 136         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 137
 138         dwc->current_dr_role = mode;
 139 }
 140
 141 static void __dwc3_set_mode(struct work_struct *work)
 142 {
 143         struct dwc3 *dwc = work_to_dwc(work);
 144         unsigned long flags;
 145         int ret;
 146         u32 reg;
 147         u32 desired_dr_role;
 148         int i;
 149
 150         mutex_lock(&dwc->mutex);
 151         spin_lock_irqsave(&dwc->lock, flags);
 152         desired_dr_role = dwc->desired_dr_role;
 153         spin_unlock_irqrestore(&dwc->lock, flags);
 154
 155         pm_runtime_get_sync(dwc->dev);
 156
 157         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
 158                 dwc3_otg_update(dwc, 0);
 159
 160         if (!desired_dr_role)
 161                 goto out;
 162
 163         if (desired_dr_role == dwc->current_dr_role)
 164                 goto out;
 165
 166         if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
 167                 goto out;
 168
 169         switch (dwc->current_dr_role) {
 170         case DWC3_GCTL_PRTCAP_HOST:
 171                 dwc3_host_exit(dwc);
 172                 break;
 173         case DWC3_GCTL_PRTCAP_DEVICE:
 174                 dwc3_gadget_exit(dwc);
 175                 dwc3_event_buffers_cleanup(dwc);
 176                 break;
 177         case DWC3_GCTL_PRTCAP_OTG:
 178                 dwc3_otg_exit(dwc);
 179                 spin_lock_irqsave(&dwc->lock, flags);
 180                 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
 181                 spin_unlock_irqrestore(&dwc->lock, flags);
 182                 dwc3_otg_update(dwc, 1);
 183                 break;
 184         default:
 185                 break;
 186         }
 187
 188         /*
 189          * When current_dr_role is not set, there's no role switching.
 190          * Only perform GCTL.CoreSoftReset when there's DRD role switching.
 191          */
 192         if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
 193                         DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
 194                         desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {
 195                 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 196                 reg |= DWC3_GCTL_CORESOFTRESET;
 197                 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 198
 199                 /*
 200                  * Wait for internal clocks to synchronized. DWC_usb31 and
 201                  * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
 202                  * keep it consistent across different IPs, let's wait up to
 203                  * 100ms before clearing GCTL.CORESOFTRESET.
 204                  */
 205                 msleep(100);
 206
 207                 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 208                 reg &= ~DWC3_GCTL_CORESOFTRESET;
 209                 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 210         }
 211
 212         spin_lock_irqsave(&dwc->lock, flags);
 213
 214         dwc3_set_prtcap(dwc, desired_dr_role);
 215
 216         spin_unlock_irqrestore(&dwc->lock, flags);
 217
 218         switch (desired_dr_role) {
 219         case DWC3_GCTL_PRTCAP_HOST:
 220                 ret = dwc3_host_init(dwc);
 221                 if (ret) {
 222                         dev_err(dwc->dev, "failed to initialize host\n");
 223                 } else {
 224                         if (dwc->usb2_phy)
 225                                 otg_set_vbus(dwc->usb2_phy->otg, true);
 226
 227                         for (i = 0; i < dwc->num_usb2_ports; i++)
 228                                 phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
 229                         for (i = 0; i < dwc->num_usb3_ports; i++)
 230                                 phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
 231
 232                         if (dwc->dis_split_quirk) {
 233                                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
 234                                 reg |= DWC3_GUCTL3_SPLITDISABLE;
 235                                 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
 236                         }
 237                 }
 238                 break;
 239         case DWC3_GCTL_PRTCAP_DEVICE:
 240                 dwc3_core_soft_reset(dwc);
 241
 242                 dwc3_event_buffers_setup(dwc);
 243
 244                 if (dwc->usb2_phy)
 245                         otg_set_vbus(dwc->usb2_phy->otg, false);
 246                 phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
 247                 phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);
 248
 249                 ret = dwc3_gadget_init(dwc);
 250                 if (ret)
 251                         dev_err(dwc->dev, "failed to initialize peripheral\n");
 252                 break;
 253         case DWC3_GCTL_PRTCAP_OTG:
 254                 dwc3_otg_init(dwc);
 255                 dwc3_otg_update(dwc, 0);
 256                 break;
 257         default:
 258                 break;
 259         }
 260
 261 out:
 262         pm_runtime_mark_last_busy(dwc->dev);
 263         pm_runtime_put_autosuspend(dwc->dev);
 264         mutex_unlock(&dwc->mutex);
 265 }
 266
 267 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
 268 {
 269         unsigned long flags;
 270
 271         if (dwc->dr_mode != USB_DR_MODE_OTG)
 272                 return;
 273
 274         spin_lock_irqsave(&dwc->lock, flags);
 275         dwc->desired_dr_role = mode;
 276         spin_unlock_irqrestore(&dwc->lock, flags);
 277
 278         queue_work(system_freezable_wq, &dwc->drd_work);
 279 }
 280
 281 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
 282 {
 283         struct dwc3             *dwc = dep->dwc;
 284         u32                     reg;
 285
 286         dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
 287                         DWC3_GDBGFIFOSPACE_NUM(dep->number) |
 288                         DWC3_GDBGFIFOSPACE_TYPE(type));
 289
 290         reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
 291
 292         return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
 293 }
 294
 295 /**
 296  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 297  * @dwc: pointer to our context structure
 298  */
 299 int dwc3_core_soft_reset(struct dwc3 *dwc)
 300 {
 301         u32             reg;
 302         int             retries = 1000;
 303
 304         /*
 305          * We're resetting only the device side because, if we're in host mode,
 306          * XHCI driver will reset the host block. If dwc3 was configured for
 307          * host-only mode, then we can return early.
 308          */
 309         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
 310                 return 0;
 311
 312         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 313         reg |= DWC3_DCTL_CSFTRST;
 314         reg &= ~DWC3_DCTL_RUN_STOP;
 315         dwc3_gadget_dctl_write_safe(dwc, reg);
 316
 317         /*
 318          * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
 319          * is cleared only after all the clocks are synchronized. This can
 320          * take a little more than 50ms. Set the polling rate at 20ms
 321          * for 10 times instead.
 322          */
 323         if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
 324                 retries = 10;
 325
 326         do {
 327                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 328                 if (!(reg & DWC3_DCTL_CSFTRST))
 329                         goto done;
 330
 331                 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
 332                         msleep(20);
 333                 else
 334                         udelay(1);
 335         } while (--retries);
 336
 337         dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n");
 338         return -ETIMEDOUT;
 339
 340 done:
 341         /*
 342          * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
 343          * is cleared, we must wait at least 50ms before accessing the PHY
 344          * domain (synchronization delay).
 345          */
 346         if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
 347                 msleep(50);
 348
 349         return 0;
 350 }
 351
 352 /*
 353  * dwc3_frame_length_adjustment - Adjusts frame length if required
 354  * @dwc3: Pointer to our controller context structure
 355  */
 356 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
 357 {
 358         u32 reg;
 359         u32 dft;
 360
 361         if (DWC3_VER_IS_PRIOR(DWC3, 250A))
 362                 return;
 363
 364         if (dwc->fladj == 0)
 365                 return;
 366
 367         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 368         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 369         if (dft != dwc->fladj) {
 370                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 371                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
 372                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 373         }
 374 }
 375
 376 /**
 377  * dwc3_ref_clk_period - Reference clock period configuration
 378  *              Default reference clock period depends on hardware
 379  *              configuration. For systems with reference clock that differs
 380  *              from the default, this will set clock period in DWC3_GUCTL
 381  *              register.
 382  * @dwc: Pointer to our controller context structure
 383  */
 384 static void dwc3_ref_clk_period(struct dwc3 *dwc)
 385 {
 386         unsigned long period;
 387         unsigned long fladj;
 388         unsigned long decr;
 389         unsigned long rate;
 390         u32 reg;
 391
 392         if (dwc->ref_clk) {
 393                 rate = clk_get_rate(dwc->ref_clk);
 394                 if (!rate)
 395                         return;
 396                 period = NSEC_PER_SEC / rate;
 397         } else if (dwc->ref_clk_per) {
 398                 period = dwc->ref_clk_per;
 399                 rate = NSEC_PER_SEC / period;
 400         } else {
 401                 return;
 402         }
 403
 404         reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
 405         reg &= ~DWC3_GUCTL_REFCLKPER_MASK;
 406         reg |=  FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period);
 407         dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
 408
 409         if (DWC3_VER_IS_PRIOR(DWC3, 250A))
 410                 return;
 411
 412         /*
 413          * The calculation below is
 414          *
 415          * 125000 * (NSEC_PER_SEC / (rate * period) - 1)
 416          *
 417          * but rearranged for fixed-point arithmetic. The division must be
 418          * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and
 419          * neither does rate * period).
 420          *
 421          * Note that rate * period ~= NSEC_PER_SECOND, minus the number of
 422          * nanoseconds of error caused by the truncation which happened during
 423          * the division when calculating rate or period (whichever one was
 424          * derived from the other). We first calculate the relative error, then
 425          * scale it to units of 8 ppm.
 426          */
 427         fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period);
 428         fladj -= 125000;
 429
 430         /*
 431          * The documented 240MHz constant is scaled by 2 to get PLS1 as well.
 432          */
 433         decr = 480000000 / rate;
 434
 435         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 436         reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK
 437             &  ~DWC3_GFLADJ_240MHZDECR
 438             &  ~DWC3_GFLADJ_240MHZDECR_PLS1;
 439         reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj)
 440             |  FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1)
 441             |  FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1);
 442
 443         if (dwc->gfladj_refclk_lpm_sel)
 444                 reg |=  DWC3_GFLADJ_REFCLK_LPM_SEL;
 445
 446         dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 447 }
 448
 449 /**
 450  * dwc3_free_one_event_buffer - Frees one event buffer
 451  * @dwc: Pointer to our controller context structure
 452  * @evt: Pointer to event buffer to be freed
 453  */
 454 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 455                 struct dwc3_event_buffer *evt)
 456 {
 457         dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
 458 }
 459
 460 /**
 461  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 462  * @dwc: Pointer to our controller context structure
 463  * @length: size of the event buffer
 464  *
 465  * Returns a pointer to the allocated event buffer structure on success
 466  * otherwise ERR_PTR(errno).
 467  */
 468 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 469                 unsigned int length)
 470 {
 471         struct dwc3_event_buffer        *evt;
 472
 473         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 474         if (!evt)
 475                 return ERR_PTR(-ENOMEM);
 476
 477         evt->dwc        = dwc;
 478         evt->length     = length;
 479         evt->cache      = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
 480         if (!evt->cache)
 481                 return ERR_PTR(-ENOMEM);
 482
 483         evt->buf        = dma_alloc_coherent(dwc->sysdev, length,
 484                         &evt->dma, GFP_KERNEL);
 485         if (!evt->buf)
 486                 return ERR_PTR(-ENOMEM);
 487
 488         return evt;
 489 }
 490
 491 /**
 492  * dwc3_free_event_buffers - frees all allocated event buffers
 493  * @dwc: Pointer to our controller context structure
 494  */
 495 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 496 {
 497         struct dwc3_event_buffer        *evt;
 498
 499         evt = dwc->ev_buf;
 500         if (evt)
 501                 dwc3_free_one_event_buffer(dwc, evt);
 502 }
 503
 504 /**
 505  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 506  * @dwc: pointer to our controller context structure
 507  * @length: size of event buffer
 508  *
 509  * Returns 0 on success otherwise negative errno. In the error case, dwc
 510  * may contain some buffers allocated but not all which were requested.
 511  */
 512 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length)
 513 {
 514         struct dwc3_event_buffer *evt;
 515         unsigned int hw_mode;
 516
 517         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
 518         if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
 519                 dwc->ev_buf = NULL;
 520                 return 0;
 521         }
 522
 523         evt = dwc3_alloc_one_event_buffer(dwc, length);
 524         if (IS_ERR(evt)) {
 525                 dev_err(dwc->dev, "can't allocate event buffer\n");
 526                 return PTR_ERR(evt);
 527         }
 528         dwc->ev_buf = evt;
 529
 530         return 0;
 531 }
 532
 533 /**
 534  * dwc3_event_buffers_setup - setup our allocated event buffers
 535  * @dwc: pointer to our controller context structure
 536  *
 537  * Returns 0 on success otherwise negative errno.
 538  */
 539 int dwc3_event_buffers_setup(struct dwc3 *dwc)
 540 {
 541         struct dwc3_event_buffer        *evt;
 542
 543         if (!dwc->ev_buf)
 544                 return 0;
 545
 546         evt = dwc->ev_buf;
 547         evt->lpos = 0;
 548         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
 549                         lower_32_bits(evt->dma));
 550         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
 551                         upper_32_bits(evt->dma));
 552         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
 553                         DWC3_GEVNTSIZ_SIZE(evt->length));
 554         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 555
 556         return 0;
 557 }
 558
 559 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 560 {
 561         struct dwc3_event_buffer        *evt;
 562
 563         if (!dwc->ev_buf)
 564                 return;
 565
 566         evt = dwc->ev_buf;
 567
 568         evt->lpos = 0;
 569
 570         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
 571         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
 572         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
 573                         | DWC3_GEVNTSIZ_SIZE(0));
 574         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 575 }
 576
 577 static void dwc3_core_num_eps(struct dwc3 *dwc)
 578 {
 579         struct dwc3_hwparams    *parms = &dwc->hwparams;
 580
 581         dwc->num_eps = DWC3_NUM_EPS(parms);
 582 }
 583
 584 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 585 {
 586         struct dwc3_hwparams    *parms = &dwc->hwparams;
 587
 588         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 589         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 590         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 591         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 592         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 593         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 594         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 595         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 596         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 597
 598         if (DWC3_IP_IS(DWC32))
 599                 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
 600 }
 601
 602 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
 603 {
 604         int intf;
 605         int ret = 0;
 606
 607         intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
 608
 609         if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
 610             (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
 611              dwc->hsphy_interface &&
 612              !strncmp(dwc->hsphy_interface, "ulpi", 4)))
 613                 ret = dwc3_ulpi_init(dwc);
 614
 615         return ret;
 616 }
 617
 618 static int dwc3_ss_phy_setup(struct dwc3 *dwc, int index)
 619 {
 620         u32 reg;
 621
 622         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(index));
 623
 624         /*
 625          * Make sure UX_EXIT_PX is cleared as that causes issues with some
 626          * PHYs. Also, this bit is not supposed to be used in normal operation.
 627          */
 628         reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
 629
 630         /*
 631          * Above DWC_usb3.0 1.94a, it is recommended to set
 632          * DWC3_GUSB3PIPECTL_SUSPHY to '0' during coreConsultant configuration.
 633          * So default value will be '0' when the core is reset. Application
 634          * needs to set it to '1' after the core initialization is completed.
 635          *
 636          * Similarly for DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be
 637          * cleared after power-on reset, and it can be set after core
 638          * initialization.
 639          */
 640         reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 641
 642         if (dwc->u2ss_inp3_quirk)
 643                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 644
 645         if (dwc->dis_rxdet_inp3_quirk)
 646                 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
 647
 648         if (dwc->req_p1p2p3_quirk)
 649                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 650
 651         if (dwc->del_p1p2p3_quirk)
 652                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 653
 654         if (dwc->del_phy_power_chg_quirk)
 655                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 656
 657         if (dwc->lfps_filter_quirk)
 658                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 659
 660         if (dwc->rx_detect_poll_quirk)
 661                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 662
 663         if (dwc->tx_de_emphasis_quirk)
 664                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 665
 666         if (dwc->dis_del_phy_power_chg_quirk)
 667                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 668
 669         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(index), reg);
 670
 671         return 0;
 672 }
 673
 674 static int dwc3_hs_phy_setup(struct dwc3 *dwc, int index)
 675 {
 676         u32 reg;
 677
 678         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(index));
 679
 680         /* Select the HS PHY interface */
 681         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 682         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 683                 if (dwc->hsphy_interface &&
 684                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 685                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 686                         break;
 687                 } else if (dwc->hsphy_interface &&
 688                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 689                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 690                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);
 691                 } else {
 692                         /* Relying on default value. */
 693                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 694                                 break;
 695                 }
 696                 fallthrough;
 697         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 698         default:
 699                 break;
 700         }
 701
 702         switch (dwc->hsphy_mode) {
 703         case USBPHY_INTERFACE_MODE_UTMI:
 704                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 705                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 706                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
 707                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
 708                 break;
 709         case USBPHY_INTERFACE_MODE_UTMIW:
 710                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 711                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 712                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
 713                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 714                 break;
 715         default:
 716                 break;
 717         }
 718
 719         /*
 720          * Above DWC_usb3.0 1.94a, it is recommended to set
 721          * DWC3_GUSB2PHYCFG_SUSPHY to '0' during coreConsultant configuration.
 722          * So default value will be '0' when the core is reset. Application
 723          * needs to set it to '1' after the core initialization is completed.
 724          *
 725          * Similarly for DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared
 726          * after power-on reset, and it can be set after core initialization.
 727          */
 728         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 729
 730         if (dwc->dis_enblslpm_quirk)
 731                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 732         else
 733                 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
 734
 735         if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel)
 736                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 737
 738         /*
 739          * Some ULPI USB PHY does not support internal VBUS supply, to drive
 740          * the CPEN pin requires the configuration of the ULPI DRVVBUSEXTERNAL
 741          * bit of OTG_CTRL register. Controller configures the USB2 PHY
 742          * ULPIEXTVBUSDRV bit[17] of the GUSB2PHYCFG register to drive vBus
 743          * with an external supply.
 744          */
 745         if (dwc->ulpi_ext_vbus_drv)
 746                 reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV;
 747
 748         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg);
 749
 750         return 0;
 751 }
 752
 753 /**
 754  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 755  * @dwc: Pointer to our controller context structure
 756  *
 757  * Returns 0 on success. The USB PHY interfaces are configured but not
 758  * initialized. The PHY interfaces and the PHYs get initialized together with
 759  * the core in dwc3_core_init.
 760  */
 761 static int dwc3_phy_setup(struct dwc3 *dwc)
 762 {
 763         int i;
 764         int ret;
 765
 766         for (i = 0; i < dwc->num_usb3_ports; i++) {
 767                 ret = dwc3_ss_phy_setup(dwc, i);
 768                 if (ret)
 769                         return ret;
 770         }
 771
 772         for (i = 0; i < dwc->num_usb2_ports; i++) {
 773                 ret = dwc3_hs_phy_setup(dwc, i);
 774                 if (ret)
 775                         return ret;
 776         }
 777
 778         return 0;
 779 }
 780
 781 static int dwc3_phy_init(struct dwc3 *dwc)
 782 {
 783         int ret;
 784         int i;
 785         int j;
 786
 787         usb_phy_init(dwc->usb2_phy);
 788         usb_phy_init(dwc->usb3_phy);
 789
 790         for (i = 0; i < dwc->num_usb2_ports; i++) {
 791                 ret = phy_init(dwc->usb2_generic_phy[i]);
 792                 if (ret < 0)
 793                         goto err_exit_usb2_phy;
 794         }
 795
 796         for (j = 0; j < dwc->num_usb3_ports; j++) {
 797                 ret = phy_init(dwc->usb3_generic_phy[j]);
 798                 if (ret < 0)
 799                         goto err_exit_usb3_phy;
 800         }
 801
 802         return 0;
 803
 804 err_exit_usb3_phy:
 805         while (--j >= 0)
 806                 phy_exit(dwc->usb3_generic_phy[j]);
 807
 808 err_exit_usb2_phy:
 809         while (--i >= 0)
 810                 phy_exit(dwc->usb2_generic_phy[i]);
 811
 812         usb_phy_shutdown(dwc->usb3_phy);
 813         usb_phy_shutdown(dwc->usb2_phy);
 814
 815         return ret;
 816 }
 817
 818 static void dwc3_phy_exit(struct dwc3 *dwc)
 819 {
 820         int i;
 821
 822         for (i = 0; i < dwc->num_usb3_ports; i++)
 823                 phy_exit(dwc->usb3_generic_phy[i]);
 824
 825         for (i = 0; i < dwc->num_usb2_ports; i++)
 826                 phy_exit(dwc->usb2_generic_phy[i]);
 827
 828         usb_phy_shutdown(dwc->usb3_phy);
 829         usb_phy_shutdown(dwc->usb2_phy);
 830 }
 831
 832 static int dwc3_phy_power_on(struct dwc3 *dwc)
 833 {
 834         int ret;
 835         int i;
 836         int j;
 837
 838         usb_phy_set_suspend(dwc->usb2_phy, 0);
 839         usb_phy_set_suspend(dwc->usb3_phy, 0);
 840
 841         for (i = 0; i < dwc->num_usb2_ports; i++) {
 842                 ret = phy_power_on(dwc->usb2_generic_phy[i]);
 843                 if (ret < 0)
 844                         goto err_power_off_usb2_phy;
 845         }
 846
 847         for (j = 0; j < dwc->num_usb3_ports; j++) {
 848                 ret = phy_power_on(dwc->usb3_generic_phy[j]);
 849                 if (ret < 0)
 850                         goto err_power_off_usb3_phy;
 851         }
 852
 853         return 0;
 854
 855 err_power_off_usb3_phy:
 856         while (--j >= 0)
 857                 phy_power_off(dwc->usb3_generic_phy[j]);
 858
 859 err_power_off_usb2_phy:
 860         while (--i >= 0)
 861                 phy_power_off(dwc->usb2_generic_phy[i]);
 862
 863         usb_phy_set_suspend(dwc->usb3_phy, 1);
 864         usb_phy_set_suspend(dwc->usb2_phy, 1);
 865
 866         return ret;
 867 }
 868
 869 static void dwc3_phy_power_off(struct dwc3 *dwc)
 870 {
 871         int i;
 872
 873         for (i = 0; i < dwc->num_usb3_ports; i++)
 874                 phy_power_off(dwc->usb3_generic_phy[i]);
 875
 876         for (i = 0; i < dwc->num_usb2_ports; i++)
 877                 phy_power_off(dwc->usb2_generic_phy[i]);
 878
 879         usb_phy_set_suspend(dwc->usb3_phy, 1);
 880         usb_phy_set_suspend(dwc->usb2_phy, 1);
 881 }
 882
 883 static int dwc3_clk_enable(struct dwc3 *dwc)
 884 {
 885         int ret;
 886
 887         ret = clk_prepare_enable(dwc->bus_clk);
 888         if (ret)
 889                 return ret;
 890
 891         ret = clk_prepare_enable(dwc->ref_clk);
 892         if (ret)
 893                 goto disable_bus_clk;
 894
 895         ret = clk_prepare_enable(dwc->susp_clk);
 896         if (ret)
 897                 goto disable_ref_clk;
 898
 899         ret = clk_prepare_enable(dwc->utmi_clk);
 900         if (ret)
 901                 goto disable_susp_clk;
 902
 903         ret = clk_prepare_enable(dwc->pipe_clk);
 904         if (ret)
 905                 goto disable_utmi_clk;
 906
 907         return 0;
 908
 909 disable_utmi_clk:
 910         clk_disable_unprepare(dwc->utmi_clk);
 911 disable_susp_clk:
 912         clk_disable_unprepare(dwc->susp_clk);
 913 disable_ref_clk:
 914         clk_disable_unprepare(dwc->ref_clk);
 915 disable_bus_clk:
 916         clk_disable_unprepare(dwc->bus_clk);
 917         return ret;
 918 }
 919
 920 static void dwc3_clk_disable(struct dwc3 *dwc)
 921 {
 922         clk_disable_unprepare(dwc->pipe_clk);
 923         clk_disable_unprepare(dwc->utmi_clk);
 924         clk_disable_unprepare(dwc->susp_clk);
 925         clk_disable_unprepare(dwc->ref_clk);
 926         clk_disable_unprepare(dwc->bus_clk);
 927 }
 928
 929 static void dwc3_core_exit(struct dwc3 *dwc)
 930 {
 931         dwc3_event_buffers_cleanup(dwc);
 932         dwc3_phy_power_off(dwc);
 933         dwc3_phy_exit(dwc);
 934         dwc3_clk_disable(dwc);
 935         reset_control_assert(dwc->reset);
 936 }
 937
 938 static bool dwc3_core_is_valid(struct dwc3 *dwc)
 939 {
 940         u32 reg;
 941
 942         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 943         dwc->ip = DWC3_GSNPS_ID(reg);
 944
 945         /* This should read as U3 followed by revision number */
 946         if (DWC3_IP_IS(DWC3)) {
 947                 dwc->revision = reg;
 948         } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
 949                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 950                 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
 951         } else {
 952                 return false;
 953         }
 954
 955         return true;
 956 }
 957
 958 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
 959 {
 960         u32 reg;
 961
 962         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 963         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 964
 965         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 966         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 967                 /**
 968                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 969                  * issue which would cause xHCI compliance tests to fail.
 970                  *
 971                  * Because of that we cannot enable clock gating on such
 972                  * configurations.
 973                  *
 974                  * Refers to:
 975                  *
 976                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 977                  * SOF/ITP Mode Used
 978                  */
 979                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 980                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 981                                 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
 982                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 983                 else
 984                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 985                 break;
 986         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 987                 /*
 988                  * REVISIT Enabling this bit so that host-mode hibernation
 989                  * will work. Device-mode hibernation is not yet implemented.
 990                  */
 991                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 992                 break;
 993         default:
 994                 /* nothing */
 995                 break;
 996         }
 997
 998         /* check if current dwc3 is on simulation board */
 999         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
1000                 dev_info(dwc->dev, "Running with FPGA optimizations\n");
1001                 dwc->is_fpga = true;
1002         }
1003
1004         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
1005                         "disable_scramble cannot be used on non-FPGA builds\n");
1006
1007         if (dwc->disable_scramble_quirk && dwc->is_fpga)
1008                 reg |= DWC3_GCTL_DISSCRAMBLE;
1009         else
1010                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
1011
1012         if (dwc->u2exit_lfps_quirk)
1013                 reg |= DWC3_GCTL_U2EXIT_LFPS;
1014
1015         /*
1016          * WORKAROUND: DWC3 revisions <1.90a have a bug
1017          * where the device can fail to connect at SuperSpeed
1018          * and falls back to high-speed mode which causes
1019          * the device to enter a Connect/Disconnect loop
1020          */
1021         if (DWC3_VER_IS_PRIOR(DWC3, 190A))
1022                 reg |= DWC3_GCTL_U2RSTECN;
1023
1024         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1025 }
1026
1027 static int dwc3_core_get_phy(struct dwc3 *dwc);
1028 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
1029
1030 /* set global incr burst type configuration registers */
1031 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
1032 {
1033         struct device *dev = dwc->dev;
1034         /* incrx_mode : for INCR burst type. */
1035         bool incrx_mode;
1036         /* incrx_size : for size of INCRX burst. */
1037         u32 incrx_size;
1038         u32 *vals;
1039         u32 cfg;
1040         int ntype;
1041         int ret;
1042         int i;
1043
1044         cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
1045
1046         /*
1047          * Handle property "snps,incr-burst-type-adjustment".
1048          * Get the number of value from this property:
1049          * result <= 0, means this property is not supported.
1050          * result = 1, means INCRx burst mode supported.
1051          * result > 1, means undefined length burst mode supported.
1052          */
1053         ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
1054         if (ntype <= 0)
1055                 return;
1056
1057         vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
1058         if (!vals)
1059                 return;
1060
1061         /* Get INCR burst type, and parse it */
1062         ret = device_property_read_u32_array(dev,
1063                         "snps,incr-burst-type-adjustment", vals, ntype);
1064         if (ret) {
1065                 kfree(vals);
1066                 dev_err(dev, "Error to get property\n");
1067                 return;
1068         }
1069
1070         incrx_size = *vals;
1071
1072         if (ntype > 1) {
1073                 /* INCRX (undefined length) burst mode */
1074                 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
1075                 for (i = 1; i < ntype; i++) {
1076                         if (vals[i] > incrx_size)
1077                                 incrx_size = vals[i];
1078                 }
1079         } else {
1080                 /* INCRX burst mode */
1081                 incrx_mode = INCRX_BURST_MODE;
1082         }
1083
1084         kfree(vals);
1085
1086         /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
1087         cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
1088         if (incrx_mode)
1089                 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
1090         switch (incrx_size) {
1091         case 256:
1092                 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
1093                 break;
1094         case 128:
1095                 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
1096                 break;
1097         case 64:
1098                 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
1099                 break;
1100         case 32:
1101                 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
1102                 break;
1103         case 16:
1104                 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
1105                 break;
1106         case 8:
1107                 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
1108                 break;
1109         case 4:
1110                 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
1111                 break;
1112         case 1:
1113                 break;
1114         default:
1115                 dev_err(dev, "Invalid property\n");
1116                 break;
1117         }
1118
1119         dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
1120 }
1121
1122 static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc)
1123 {
1124         u32 scale;
1125         u32 reg;
1126
1127         if (!dwc->susp_clk)
1128                 return;
1129
1130         /*
1131          * The power down scale field specifies how many suspend_clk
1132          * periods fit into a 16KHz clock period. When performing
1133          * the division, round up the remainder.
1134          *
1135          * The power down scale value is calculated using the fastest
1136          * frequency of the suspend_clk. If it isn't fixed (but within
1137          * the accuracy requirement), the driver may not know the max
1138          * rate of the suspend_clk, so only update the power down scale
1139          * if the default is less than the calculated value from
1140          * clk_get_rate() or if the default is questionably high
1141          * (3x or more) to be within the requirement.
1142          */
1143         scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000);
1144         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1145         if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) ||
1146             (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) {
1147                 reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK);
1148                 reg |= DWC3_GCTL_PWRDNSCALE(scale);
1149                 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1150         }
1151 }
1152
1153 static void dwc3_config_threshold(struct dwc3 *dwc)
1154 {
1155         u32 reg;
1156         u8 rx_thr_num;
1157         u8 rx_maxburst;
1158         u8 tx_thr_num;
1159         u8 tx_maxburst;
1160
1161         /*
1162          * Must config both number of packets and max burst settings to enable
1163          * RX and/or TX threshold.
1164          */
1165         if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1166                 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1167                 rx_maxburst = dwc->rx_max_burst_prd;
1168                 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1169                 tx_maxburst = dwc->tx_max_burst_prd;
1170
1171                 if (rx_thr_num && rx_maxburst) {
1172                         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1173                         reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1174
1175                         reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1176                         reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1177
1178                         reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1179                         reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1180
1181                         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1182                 }
1183
1184                 if (tx_thr_num && tx_maxburst) {
1185                         reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1186                         reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1187
1188                         reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1189                         reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1190
1191                         reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1192                         reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1193
1194                         dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1195                 }
1196         }
1197
1198         rx_thr_num = dwc->rx_thr_num_pkt;
1199         rx_maxburst = dwc->rx_max_burst;
1200         tx_thr_num = dwc->tx_thr_num_pkt;
1201         tx_maxburst = dwc->tx_max_burst;
1202
1203         if (DWC3_IP_IS(DWC3)) {
1204                 if (rx_thr_num && rx_maxburst) {
1205                         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1206                         reg |= DWC3_GRXTHRCFG_PKTCNTSEL;
1207
1208                         reg &= ~DWC3_GRXTHRCFG_RXPKTCNT(~0);
1209                         reg |= DWC3_GRXTHRCFG_RXPKTCNT(rx_thr_num);
1210
1211                         reg &= ~DWC3_GRXTHRCFG_MAXRXBURSTSIZE(~0);
1212                         reg |= DWC3_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);
1213
1214                         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1215                 }
1216
1217                 if (tx_thr_num && tx_maxburst) {
1218                         reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1219                         reg |= DWC3_GTXTHRCFG_PKTCNTSEL;
1220
1221                         reg &= ~DWC3_GTXTHRCFG_TXPKTCNT(~0);
1222                         reg |= DWC3_GTXTHRCFG_TXPKTCNT(tx_thr_num);
1223
1224                         reg &= ~DWC3_GTXTHRCFG_MAXTXBURSTSIZE(~0);
1225                         reg |= DWC3_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);
1226
1227                         dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1228                 }
1229         } else {
1230                 if (rx_thr_num && rx_maxburst) {
1231                         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1232                         reg |= DWC31_GRXTHRCFG_PKTCNTSEL;
1233
1234                         reg &= ~DWC31_GRXTHRCFG_RXPKTCNT(~0);
1235                         reg |= DWC31_GRXTHRCFG_RXPKTCNT(rx_thr_num);
1236
1237                         reg &= ~DWC31_GRXTHRCFG_MAXRXBURSTSIZE(~0);
1238                         reg |= DWC31_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);
1239
1240                         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1241                 }
1242
1243                 if (tx_thr_num && tx_maxburst) {
1244                         reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1245                         reg |= DWC31_GTXTHRCFG_PKTCNTSEL;
1246
1247                         reg &= ~DWC31_GTXTHRCFG_TXPKTCNT(~0);
1248                         reg |= DWC31_GTXTHRCFG_TXPKTCNT(tx_thr_num);
1249
1250                         reg &= ~DWC31_GTXTHRCFG_MAXTXBURSTSIZE(~0);
1251                         reg |= DWC31_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);
1252
1253                         dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1254                 }
1255         }
1256 }
1257
1258 /**
1259  * dwc3_core_init - Low-level initialization of DWC3 Core
1260  * @dwc: Pointer to our controller context structure
1261  *
1262  * Returns 0 on success otherwise negative errno.
1263  */
1264 static int dwc3_core_init(struct dwc3 *dwc)
1265 {
1266         unsigned int            hw_mode;
1267         u32                     reg;
1268         int                     ret;
1269
1270         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
1271
1272         /*
1273          * Write Linux Version Code to our GUID register so it's easy to figure
1274          * out which kernel version a bug was found.
1275          */
1276         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
1277
1278         ret = dwc3_phy_setup(dwc);
1279         if (ret)
1280                 return ret;
1281
1282         if (!dwc->ulpi_ready) {
1283                 ret = dwc3_core_ulpi_init(dwc);
1284                 if (ret) {
1285                         if (ret == -ETIMEDOUT) {
1286                                 dwc3_core_soft_reset(dwc);
1287                                 ret = -EPROBE_DEFER;
1288                         }
1289                         return ret;
1290                 }
1291                 dwc->ulpi_ready = true;
1292         }
1293
1294         if (!dwc->phys_ready) {
1295                 ret = dwc3_core_get_phy(dwc);
1296                 if (ret)
1297                         goto err_exit_ulpi;
1298                 dwc->phys_ready = true;
1299         }
1300
1301         ret = dwc3_phy_init(dwc);
1302         if (ret)
1303                 goto err_exit_ulpi;
1304
1305         ret = dwc3_core_soft_reset(dwc);
1306         if (ret)
1307                 goto err_exit_phy;
1308
1309         dwc3_core_setup_global_control(dwc);
1310         dwc3_core_num_eps(dwc);
1311
1312         /* Set power down scale of suspend_clk */
1313         dwc3_set_power_down_clk_scale(dwc);
1314
1315         /* Adjust Frame Length */
1316         dwc3_frame_length_adjustment(dwc);
1317
1318         /* Adjust Reference Clock Period */
1319         dwc3_ref_clk_period(dwc);
1320
1321         dwc3_set_incr_burst_type(dwc);
1322
1323         ret = dwc3_phy_power_on(dwc);
1324         if (ret)
1325                 goto err_exit_phy;
1326
1327         ret = dwc3_event_buffers_setup(dwc);
1328         if (ret) {
1329                 dev_err(dwc->dev, "failed to setup event buffers\n");
1330                 goto err_power_off_phy;
1331         }
1332
1333         /*
1334          * ENDXFER polling is available on version 3.10a and later of
1335          * the DWC_usb3 controller. It is NOT available in the
1336          * DWC_usb31 controller.
1337          */
1338         if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1339                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1340                 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1341                 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1342         }
1343
1344         /*
1345          * When configured in HOST mode, after issuing U3/L2 exit controller
1346          * fails to send proper CRC checksum in CRC5 feild. Because of this
1347          * behaviour Transaction Error is generated, resulting in reset and
1348          * re-enumeration of usb device attached. All the termsel, xcvrsel,
1349          * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1
1350          * will correct this problem. This option is to support certain
1351          * legacy ULPI PHYs.
1352          */
1353         if (dwc->resume_hs_terminations) {
1354                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1355                 reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST;
1356                 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1357         }
1358
1359         if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1360                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1361
1362                 /*
1363                  * Enable hardware control of sending remote wakeup
1364                  * in HS when the device is in the L1 state.
1365                  */
1366                 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1367                         reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1368
1369                 /*
1370                  * Decouple USB 2.0 L1 & L2 events which will allow for
1371                  * gadget driver to only receive U3/L2 suspend & wakeup
1372                  * events and prevent the more frequent L1 LPM transitions
1373                  * from interrupting the driver.
1374                  */
1375                 if (!DWC3_VER_IS_PRIOR(DWC3, 300A))
1376                         reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT;
1377
1378                 if (dwc->dis_tx_ipgap_linecheck_quirk)
1379                         reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1380
1381                 if (dwc->parkmode_disable_ss_quirk)
1382                         reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1383
1384                 if (dwc->parkmode_disable_hs_quirk)
1385                         reg |= DWC3_GUCTL1_PARKMODE_DISABLE_HS;
1386
1387                 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY)) {
1388                         if (dwc->maximum_speed == USB_SPEED_FULL ||
1389                             dwc->maximum_speed == USB_SPEED_HIGH)
1390                                 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1391                         else
1392                                 reg &= ~DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1393                 }
1394
1395                 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1396         }
1397
1398         dwc3_config_threshold(dwc);
1399
1400         /*
1401          * Modify this for all supported Super Speed ports when
1402          * multiport support is added.
1403          */
1404         if (hw_mode != DWC3_GHWPARAMS0_MODE_GADGET &&
1405             (DWC3_IP_IS(DWC31)) &&
1406             dwc->maximum_speed == USB_SPEED_SUPER) {
1407                 reg = dwc3_readl(dwc->regs, DWC3_LLUCTL);
1408                 reg |= DWC3_LLUCTL_FORCE_GEN1;
1409                 dwc3_writel(dwc->regs, DWC3_LLUCTL, reg);
1410         }
1411
1412         return 0;
1413
1414 err_power_off_phy:
1415         dwc3_phy_power_off(dwc);
1416 err_exit_phy:
1417         dwc3_phy_exit(dwc);
1418 err_exit_ulpi:
1419         dwc3_ulpi_exit(dwc);
1420
1421         return ret;
1422 }
1423
1424 static int dwc3_core_get_phy(struct dwc3 *dwc)
1425 {
1426         struct device           *dev = dwc->dev;
1427         struct device_node      *node = dev->of_node;
1428         char phy_name[9];
1429         int ret;
1430         u8 i;
1431
1432         if (node) {
1433                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1434                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1435         } else {
1436                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1437                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1438         }
1439
1440         if (IS_ERR(dwc->usb2_phy)) {
1441                 ret = PTR_ERR(dwc->usb2_phy);
1442                 if (ret == -ENXIO || ret == -ENODEV)
1443                         dwc->usb2_phy = NULL;
1444                 else
1445                         return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1446         }
1447
1448         if (IS_ERR(dwc->usb3_phy)) {
1449                 ret = PTR_ERR(dwc->usb3_phy);
1450                 if (ret == -ENXIO || ret == -ENODEV)
1451                         dwc->usb3_phy = NULL;
1452                 else
1453                         return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1454         }
1455
1456         for (i = 0; i < dwc->num_usb2_ports; i++) {
1457                 if (dwc->num_usb2_ports == 1)
1458                         snprintf(phy_name, sizeof(phy_name), "usb2-phy");
1459                 else
1460                         snprintf(phy_name, sizeof(phy_name),  "usb2-%u", i);
1461
1462                 dwc->usb2_generic_phy[i] = devm_phy_get(dev, phy_name);
1463                 if (IS_ERR(dwc->usb2_generic_phy[i])) {
1464                         ret = PTR_ERR(dwc->usb2_generic_phy[i]);
1465                         if (ret == -ENOSYS || ret == -ENODEV)
1466                                 dwc->usb2_generic_phy[i] = NULL;
1467                         else
1468                                 return dev_err_probe(dev, ret, "failed to lookup phy %s\n",
1469                                                         phy_name);
1470                 }
1471         }
1472
1473         for (i = 0; i < dwc->num_usb3_ports; i++) {
1474                 if (dwc->num_usb3_ports == 1)
1475                         snprintf(phy_name, sizeof(phy_name), "usb3-phy");
1476                 else
1477                         snprintf(phy_name, sizeof(phy_name), "usb3-%u", i);
1478
1479                 dwc->usb3_generic_phy[i] = devm_phy_get(dev, phy_name);
1480                 if (IS_ERR(dwc->usb3_generic_phy[i])) {
1481                         ret = PTR_ERR(dwc->usb3_generic_phy[i]);
1482                         if (ret == -ENOSYS || ret == -ENODEV)
1483                                 dwc->usb3_generic_phy[i] = NULL;
1484                         else
1485                                 return dev_err_probe(dev, ret, "failed to lookup phy %s\n",
1486                                                         phy_name);
1487                 }
1488         }
1489
1490         return 0;
1491 }
1492
1493 static int dwc3_core_init_mode(struct dwc3 *dwc)
1494 {
1495         struct device *dev = dwc->dev;
1496         int ret;
1497         int i;
1498
1499         switch (dwc->dr_mode) {
1500         case USB_DR_MODE_PERIPHERAL:
1501                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1502
1503                 if (dwc->usb2_phy)
1504                         otg_set_vbus(dwc->usb2_phy->otg, false);
1505                 phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE);
1506                 phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE);
1507
1508                 ret = dwc3_gadget_init(dwc);
1509                 if (ret)
1510                         return dev_err_probe(dev, ret, "failed to initialize gadget\n");
1511                 break;
1512         case USB_DR_MODE_HOST:
1513                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1514
1515                 if (dwc->usb2_phy)
1516                         otg_set_vbus(dwc->usb2_phy->otg, true);
1517                 for (i = 0; i < dwc->num_usb2_ports; i++)
1518                         phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST);
1519                 for (i = 0; i < dwc->num_usb3_ports; i++)
1520                         phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST);
1521
1522                 ret = dwc3_host_init(dwc);
1523                 if (ret)
1524                         return dev_err_probe(dev, ret, "failed to initialize host\n");
1525                 break;
1526         case USB_DR_MODE_OTG:
1527                 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1528                 ret = dwc3_drd_init(dwc);
1529                 if (ret)
1530                         return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
1531                 break;
1532         default:
1533                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1534                 return -EINVAL;
1535         }
1536
1537         return 0;
1538 }
1539
1540 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1541 {
1542         switch (dwc->dr_mode) {
1543         case USB_DR_MODE_PERIPHERAL:
1544                 dwc3_gadget_exit(dwc);
1545                 break;
1546         case USB_DR_MODE_HOST:
1547                 dwc3_host_exit(dwc);
1548                 break;
1549         case USB_DR_MODE_OTG:
1550                 dwc3_drd_exit(dwc);
1551                 break;
1552         default:
1553                 /* do nothing */
1554                 break;
1555         }
1556
1557         /* de-assert DRVVBUS for HOST and OTG mode */
1558         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1559 }
1560
1561 static void dwc3_get_properties(struct dwc3 *dwc)
1562 {
1563         struct device           *dev = dwc->dev;
1564         u8                      lpm_nyet_threshold;
1565         u8                      tx_de_emphasis;
1566         u8                      hird_threshold;
1567         u8                      rx_thr_num_pkt = 0;
1568         u8                      rx_max_burst = 0;
1569         u8                      tx_thr_num_pkt = 0;
1570         u8                      tx_max_burst = 0;
1571         u8                      rx_thr_num_pkt_prd = 0;
1572         u8                      rx_max_burst_prd = 0;
1573         u8                      tx_thr_num_pkt_prd = 0;
1574         u8                      tx_max_burst_prd = 0;
1575         u8                      tx_fifo_resize_max_num;
1576         const char              *usb_psy_name;
1577         int                     ret;
1578
1579         /* default to highest possible threshold */
1580         lpm_nyet_threshold = 0xf;
1581
1582         /* default to -3.5dB de-emphasis */
1583         tx_de_emphasis = 1;
1584
1585         /*
1586          * default to assert utmi_sleep_n and use maximum allowed HIRD
1587          * threshold value of 0b1100
1588          */
1589         hird_threshold = 12;
1590
1591         /*
1592          * default to a TXFIFO size large enough to fit 6 max packets.  This
1593          * allows for systems with larger bus latencies to have some headroom
1594          * for endpoints that have a large bMaxBurst value.
1595          */
1596         tx_fifo_resize_max_num = 6;
1597
1598         dwc->maximum_speed = usb_get_maximum_speed(dev);
1599         dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
1600         dwc->dr_mode = usb_get_dr_mode(dev);
1601         dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1602
1603         dwc->sysdev_is_parent = device_property_read_bool(dev,
1604                                 "linux,sysdev_is_parent");
1605         if (dwc->sysdev_is_parent)
1606                 dwc->sysdev = dwc->dev->parent;
1607         else
1608                 dwc->sysdev = dwc->dev;
1609
1610         dwc->sys_wakeup = device_may_wakeup(dwc->sysdev);
1611
1612         ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name);
1613         if (ret >= 0) {
1614                 dwc->usb_psy = power_supply_get_by_name(usb_psy_name);
1615                 if (!dwc->usb_psy)
1616                         dev_err(dev, "couldn't get usb power supply\n");
1617         }
1618
1619         dwc->has_lpm_erratum = device_property_read_bool(dev,
1620                                 "snps,has-lpm-erratum");
1621         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1622                                 &lpm_nyet_threshold);
1623         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1624                                 "snps,is-utmi-l1-suspend");
1625         device_property_read_u8(dev, "snps,hird-threshold",
1626                                 &hird_threshold);
1627         dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1628                                 "snps,dis-start-transfer-quirk");
1629         dwc->usb3_lpm_capable = device_property_read_bool(dev,
1630                                 "snps,usb3_lpm_capable");
1631         dwc->usb2_lpm_disable = device_property_read_bool(dev,
1632                                 "snps,usb2-lpm-disable");
1633         dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1634                                 "snps,usb2-gadget-lpm-disable");
1635         device_property_read_u8(dev, "snps,rx-thr-num-pkt",
1636                                 &rx_thr_num_pkt);
1637         device_property_read_u8(dev, "snps,rx-max-burst",
1638                                 &rx_max_burst);
1639         device_property_read_u8(dev, "snps,tx-thr-num-pkt",
1640                                 &tx_thr_num_pkt);
1641         device_property_read_u8(dev, "snps,tx-max-burst",
1642                                 &tx_max_burst);
1643         device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1644                                 &rx_thr_num_pkt_prd);
1645         device_property_read_u8(dev, "snps,rx-max-burst-prd",
1646                                 &rx_max_burst_prd);
1647         device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1648                                 &tx_thr_num_pkt_prd);
1649         device_property_read_u8(dev, "snps,tx-max-burst-prd",
1650                                 &tx_max_burst_prd);
1651         dwc->do_fifo_resize = device_property_read_bool(dev,
1652                                                         "tx-fifo-resize");
1653         if (dwc->do_fifo_resize)
1654                 device_property_read_u8(dev, "tx-fifo-max-num",
1655                                         &tx_fifo_resize_max_num);
1656
1657         dwc->disable_scramble_quirk = device_property_read_bool(dev,
1658                                 "snps,disable_scramble_quirk");
1659         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1660                                 "snps,u2exit_lfps_quirk");
1661         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1662                                 "snps,u2ss_inp3_quirk");
1663         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1664                                 "snps,req_p1p2p3_quirk");
1665         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1666                                 "snps,del_p1p2p3_quirk");
1667         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1668                                 "snps,del_phy_power_chg_quirk");
1669         dwc->lfps_filter_quirk = device_property_read_bool(dev,
1670                                 "snps,lfps_filter_quirk");
1671         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1672                                 "snps,rx_detect_poll_quirk");
1673         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1674                                 "snps,dis_u3_susphy_quirk");
1675         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1676                                 "snps,dis_u2_susphy_quirk");
1677         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1678                                 "snps,dis_enblslpm_quirk");
1679         dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1680                                 "snps,dis-u1-entry-quirk");
1681         dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1682                                 "snps,dis-u2-entry-quirk");
1683         dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1684                                 "snps,dis_rxdet_inp3_quirk");
1685         dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1686                                 "snps,dis-u2-freeclk-exists-quirk");
1687         dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1688                                 "snps,dis-del-phy-power-chg-quirk");
1689         dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1690                                 "snps,dis-tx-ipgap-linecheck-quirk");
1691         dwc->resume_hs_terminations = device_property_read_bool(dev,
1692                                 "snps,resume-hs-terminations");
1693         dwc->ulpi_ext_vbus_drv = device_property_read_bool(dev,
1694                                 "snps,ulpi-ext-vbus-drv");
1695         dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1696                                 "snps,parkmode-disable-ss-quirk");
1697         dwc->parkmode_disable_hs_quirk = device_property_read_bool(dev,
1698                                 "snps,parkmode-disable-hs-quirk");
1699         dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev,
1700                                 "snps,gfladj-refclk-lpm-sel-quirk");
1701
1702         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1703                                 "snps,tx_de_emphasis_quirk");
1704         device_property_read_u8(dev, "snps,tx_de_emphasis",
1705                                 &tx_de_emphasis);
1706         device_property_read_string(dev, "snps,hsphy_interface",
1707                                     &dwc->hsphy_interface);
1708         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1709                                  &dwc->fladj);
1710         device_property_read_u32(dev, "snps,ref-clock-period-ns",
1711                                  &dwc->ref_clk_per);
1712
1713         dwc->dis_metastability_quirk = device_property_read_bool(dev,
1714                                 "snps,dis_metastability_quirk");
1715
1716         dwc->dis_split_quirk = device_property_read_bool(dev,
1717                                 "snps,dis-split-quirk");
1718
1719         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1720         dwc->tx_de_emphasis = tx_de_emphasis;
1721
1722         dwc->hird_threshold = hird_threshold;
1723
1724         dwc->rx_thr_num_pkt = rx_thr_num_pkt;
1725         dwc->rx_max_burst = rx_max_burst;
1726
1727         dwc->tx_thr_num_pkt = tx_thr_num_pkt;
1728         dwc->tx_max_burst = tx_max_burst;
1729
1730         dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1731         dwc->rx_max_burst_prd = rx_max_burst_prd;
1732
1733         dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1734         dwc->tx_max_burst_prd = tx_max_burst_prd;
1735
1736         dwc->imod_interval = 0;
1737
1738         dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
1739 }
1740
1741 /* check whether the core supports IMOD */
1742 bool dwc3_has_imod(struct dwc3 *dwc)
1743 {
1744         return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1745                 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1746                 DWC3_IP_IS(DWC32);
1747 }
1748
1749 static void dwc3_check_params(struct dwc3 *dwc)
1750 {
1751         struct device *dev = dwc->dev;
1752         unsigned int hwparam_gen =
1753                 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1754
1755         /* Check for proper value of imod_interval */
1756         if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1757                 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1758                 dwc->imod_interval = 0;
1759         }
1760
1761         /*
1762          * Workaround for STAR 9000961433 which affects only version
1763          * 3.00a of the DWC_usb3 core. This prevents the controller
1764          * interrupt from being masked while handling events. IMOD
1765          * allows us to work around this issue. Enable it for the
1766          * affected version.
1767          */
1768         if (!dwc->imod_interval &&
1769             DWC3_VER_IS(DWC3, 300A))
1770                 dwc->imod_interval = 1;
1771
1772         /* Check the maximum_speed parameter */
1773         switch (dwc->maximum_speed) {
1774         case USB_SPEED_FULL:
1775         case USB_SPEED_HIGH:
1776                 break;
1777         case USB_SPEED_SUPER:
1778                 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1779                         dev_warn(dev, "UDC doesn't support Gen 1\n");
1780                 break;
1781         case USB_SPEED_SUPER_PLUS:
1782                 if ((DWC3_IP_IS(DWC32) &&
1783                      hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1784                     (!DWC3_IP_IS(DWC32) &&
1785                      hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1786                         dev_warn(dev, "UDC doesn't support SSP\n");
1787                 break;
1788         default:
1789                 dev_err(dev, "invalid maximum_speed parameter %d\n",
1790                         dwc->maximum_speed);
1791                 fallthrough;
1792         case USB_SPEED_UNKNOWN:
1793                 switch (hwparam_gen) {
1794                 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1795                         dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1796                         break;
1797                 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1798                         if (DWC3_IP_IS(DWC32))
1799                                 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1800                         else
1801                                 dwc->maximum_speed = USB_SPEED_SUPER;
1802                         break;
1803                 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1804                         dwc->maximum_speed = USB_SPEED_HIGH;
1805                         break;
1806                 default:
1807                         dwc->maximum_speed = USB_SPEED_SUPER;
1808                         break;
1809                 }
1810                 break;
1811         }
1812
1813         /*
1814          * Currently the controller does not have visibility into the HW
1815          * parameter to determine the maximum number of lanes the HW supports.
1816          * If the number of lanes is not specified in the device property, then
1817          * set the default to support dual-lane for DWC_usb32 and single-lane
1818          * for DWC_usb31 for super-speed-plus.
1819          */
1820         if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1821                 switch (dwc->max_ssp_rate) {
1822                 case USB_SSP_GEN_2x1:
1823                         if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1824                                 dev_warn(dev, "UDC only supports Gen 1\n");
1825                         break;
1826                 case USB_SSP_GEN_1x2:
1827                 case USB_SSP_GEN_2x2:
1828                         if (DWC3_IP_IS(DWC31))
1829                                 dev_warn(dev, "UDC only supports single lane\n");
1830                         break;
1831                 case USB_SSP_GEN_UNKNOWN:
1832                 default:
1833                         switch (hwparam_gen) {
1834                         case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1835                                 if (DWC3_IP_IS(DWC32))
1836                                         dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1837                                 else
1838                                         dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1839                                 break;
1840                         case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1841                                 if (DWC3_IP_IS(DWC32))
1842                                         dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1843                                 break;
1844                         }
1845                         break;
1846                 }
1847         }
1848 }
1849
1850 static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
1851 {
1852         struct device *dev = dwc->dev;
1853         struct device_node *np_phy;
1854         struct extcon_dev *edev = NULL;
1855         const char *name;
1856
1857         if (device_property_read_bool(dev, "extcon"))
1858                 return extcon_get_edev_by_phandle(dev, 0);
1859
1860         /*
1861          * Device tree platforms should get extcon via phandle.
1862          * On ACPI platforms, we get the name from a device property.
1863          * This device property is for kernel internal use only and
1864          * is expected to be set by the glue code.
1865          */
1866         if (device_property_read_string(dev, "linux,extcon-name", &name) == 0)
1867                 return extcon_get_extcon_dev(name);
1868
1869         /*
1870          * Check explicitly if "usb-role-switch" is used since
1871          * extcon_find_edev_by_node() can not be used to check the absence of
1872          * an extcon device. In the absence of an device it will always return
1873          * EPROBE_DEFER.
1874          */
1875         if (IS_ENABLED(CONFIG_USB_ROLE_SWITCH) &&
1876             device_property_read_bool(dev, "usb-role-switch"))
1877                 return NULL;
1878
1879         /*
1880          * Try to get an extcon device from the USB PHY controller's "port"
1881          * node. Check if it has the "port" node first, to avoid printing the
1882          * error message from underlying code, as it's a valid case: extcon
1883          * device (and "port" node) may be missing in case of "usb-role-switch"
1884          * or OTG mode.
1885          */
1886         np_phy = of_parse_phandle(dev->of_node, "phys", 0);
1887         if (of_graph_is_present(np_phy)) {
1888                 struct device_node *np_conn;
1889
1890                 np_conn = of_graph_get_remote_node(np_phy, -1, -1);
1891                 if (np_conn)
1892                         edev = extcon_find_edev_by_node(np_conn);
1893                 of_node_put(np_conn);
1894         }
1895         of_node_put(np_phy);
1896
1897         return edev;
1898 }
1899
1900 static int dwc3_get_clocks(struct dwc3 *dwc)
1901 {
1902         struct device *dev = dwc->dev;
1903
1904         if (!dev->of_node)
1905                 return 0;
1906
1907         /*
1908          * Clocks are optional, but new DT platforms should support all clocks
1909          * as required by the DT-binding.
1910          * Some devices have different clock names in legacy device trees,
1911          * check for them to retain backwards compatibility.
1912          */
1913         dwc->bus_clk = devm_clk_get_optional(dev, "bus_early");
1914         if (IS_ERR(dwc->bus_clk)) {
1915                 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1916                                 "could not get bus clock\n");
1917         }
1918
1919         if (dwc->bus_clk == NULL) {
1920                 dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk");
1921                 if (IS_ERR(dwc->bus_clk)) {
1922                         return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1923                                         "could not get bus clock\n");
1924                 }
1925         }
1926
1927         dwc->ref_clk = devm_clk_get_optional(dev, "ref");
1928         if (IS_ERR(dwc->ref_clk)) {
1929                 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1930                                 "could not get ref clock\n");
1931         }
1932
1933         if (dwc->ref_clk == NULL) {
1934                 dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk");
1935                 if (IS_ERR(dwc->ref_clk)) {
1936                         return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1937                                         "could not get ref clock\n");
1938                 }
1939         }
1940
1941         dwc->susp_clk = devm_clk_get_optional(dev, "suspend");
1942         if (IS_ERR(dwc->susp_clk)) {
1943                 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1944                                 "could not get suspend clock\n");
1945         }
1946
1947         if (dwc->susp_clk == NULL) {
1948                 dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk");
1949                 if (IS_ERR(dwc->susp_clk)) {
1950                         return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1951                                         "could not get suspend clock\n");
1952                 }
1953         }
1954
1955         /* specific to Rockchip RK3588 */
1956         dwc->utmi_clk = devm_clk_get_optional(dev, "utmi");
1957         if (IS_ERR(dwc->utmi_clk)) {
1958                 return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk),
1959                                 "could not get utmi clock\n");
1960         }
1961
1962         /* specific to Rockchip RK3588 */
1963         dwc->pipe_clk = devm_clk_get_optional(dev, "pipe");
1964         if (IS_ERR(dwc->pipe_clk)) {
1965                 return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk),
1966                                 "could not get pipe clock\n");
1967         }
1968
1969         return 0;
1970 }
1971
1972 static int dwc3_get_num_ports(struct dwc3 *dwc)
1973 {
1974         void __iomem *base;
1975         u8 major_revision;
1976         u32 offset;
1977         u32 val;
1978
1979         /*
1980          * Remap xHCI address space to access XHCI ext cap regs since it is
1981          * needed to get information on number of ports present.
1982          */
1983         base = ioremap(dwc->xhci_resources[0].start,
1984                        resource_size(&dwc->xhci_resources[0]));
1985         if (!base)
1986                 return -ENOMEM;
1987
1988         offset = 0;
1989         do {
1990                 offset = xhci_find_next_ext_cap(base, offset,
1991                                                 XHCI_EXT_CAPS_PROTOCOL);
1992                 if (!offset)
1993                         break;
1994
1995                 val = readl(base + offset);
1996                 major_revision = XHCI_EXT_PORT_MAJOR(val);
1997
1998                 val = readl(base + offset + 0x08);
1999                 if (major_revision == 0x03) {
2000                         dwc->num_usb3_ports += XHCI_EXT_PORT_COUNT(val);
2001                 } else if (major_revision <= 0x02) {
2002                         dwc->num_usb2_ports += XHCI_EXT_PORT_COUNT(val);
2003                 } else {
2004                         dev_warn(dwc->dev, "unrecognized port major revision %d\n",
2005                                  major_revision);
2006                 }
2007         } while (1);
2008
2009         dev_dbg(dwc->dev, "hs-ports: %u ss-ports: %u\n",
2010                 dwc->num_usb2_ports, dwc->num_usb3_ports);
2011
2012         iounmap(base);
2013
2014         if (dwc->num_usb2_ports > DWC3_USB2_MAX_PORTS ||
2015             dwc->num_usb3_ports > DWC3_USB3_MAX_PORTS)
2016                 return -EINVAL;
2017
2018         return 0;
2019 }
2020
2021 static int dwc3_probe(struct platform_device *pdev)
2022 {
2023         struct device           *dev = &pdev->dev;
2024         struct resource         *res, dwc_res;
2025         unsigned int            hw_mode;
2026         void __iomem            *regs;
2027         struct dwc3             *dwc;
2028         int                     ret;
2029
2030         dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
2031         if (!dwc)
2032                 return -ENOMEM;
2033
2034         dwc->dev = dev;
2035
2036         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2037         if (!res) {
2038                 dev_err(dev, "missing memory resource\n");
2039                 return -ENODEV;
2040         }
2041
2042         dwc->xhci_resources[0].start = res->start;
2043         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
2044                                         DWC3_XHCI_REGS_END;
2045         dwc->xhci_resources[0].flags = res->flags;
2046         dwc->xhci_resources[0].name = res->name;
2047
2048         /*
2049          * Request memory region but exclude xHCI regs,
2050          * since it will be requested by the xhci-plat driver.
2051          */
2052         dwc_res = *res;
2053         dwc_res.start += DWC3_GLOBALS_REGS_START;
2054
2055         if (dev->of_node) {
2056                 struct device_node *parent = of_get_parent(dev->of_node);
2057
2058                 if (of_device_is_compatible(parent, "realtek,rtd-dwc3")) {
2059                         dwc_res.start -= DWC3_GLOBALS_REGS_START;
2060                         dwc_res.start += DWC3_RTK_RTD_GLOBALS_REGS_START;
2061                 }
2062
2063                 of_node_put(parent);
2064         }
2065
2066         regs = devm_ioremap_resource(dev, &dwc_res);
2067         if (IS_ERR(regs))
2068                 return PTR_ERR(regs);
2069
2070         dwc->regs       = regs;
2071         dwc->regs_size  = resource_size(&dwc_res);
2072
2073         dwc3_get_properties(dwc);
2074
2075         dwc->reset = devm_reset_control_array_get_optional_shared(dev);
2076         if (IS_ERR(dwc->reset)) {
2077                 ret = PTR_ERR(dwc->reset);
2078                 goto err_put_psy;
2079         }
2080
2081         ret = dwc3_get_clocks(dwc);
2082         if (ret)
2083                 goto err_put_psy;
2084
2085         ret = reset_control_deassert(dwc->reset);
2086         if (ret)
2087                 goto err_put_psy;
2088
2089         ret = dwc3_clk_enable(dwc);
2090         if (ret)
2091                 goto err_assert_reset;
2092
2093         if (!dwc3_core_is_valid(dwc)) {
2094                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
2095                 ret = -ENODEV;
2096                 goto err_disable_clks;
2097         }
2098
2099         platform_set_drvdata(pdev, dwc);
2100         dwc3_cache_hwparams(dwc);
2101
2102         if (!dwc->sysdev_is_parent &&
2103             DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) {
2104                 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
2105                 if (ret)
2106                         goto err_disable_clks;
2107         }
2108
2109         /*
2110          * Currently only DWC3 controllers that are host-only capable
2111          * can have more than one port.
2112          */
2113         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
2114         if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) {
2115                 ret = dwc3_get_num_ports(dwc);
2116                 if (ret)
2117                         goto err_disable_clks;
2118         } else {
2119                 dwc->num_usb2_ports = 1;
2120                 dwc->num_usb3_ports = 1;
2121         }
2122
2123         spin_lock_init(&dwc->lock);
2124         mutex_init(&dwc->mutex);
2125
2126         pm_runtime_get_noresume(dev);
2127         pm_runtime_set_active(dev);
2128         pm_runtime_use_autosuspend(dev);
2129         pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
2130         pm_runtime_enable(dev);
2131
2132         pm_runtime_forbid(dev);
2133
2134         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
2135         if (ret) {
2136                 dev_err(dwc->dev, "failed to allocate event buffers\n");
2137                 ret = -ENOMEM;
2138                 goto err_allow_rpm;
2139         }
2140
2141         dwc->edev = dwc3_get_extcon(dwc);
2142         if (IS_ERR(dwc->edev)) {
2143                 ret = dev_err_probe(dwc->dev, PTR_ERR(dwc->edev), "failed to get extcon\n");
2144                 goto err_free_event_buffers;
2145         }
2146
2147         ret = dwc3_get_dr_mode(dwc);
2148         if (ret)
2149                 goto err_free_event_buffers;
2150
2151         ret = dwc3_core_init(dwc);
2152         if (ret) {
2153                 dev_err_probe(dev, ret, "failed to initialize core\n");
2154                 goto err_free_event_buffers;
2155         }
2156
2157         dwc3_check_params(dwc);
2158         dwc3_debugfs_init(dwc);
2159
2160         ret = dwc3_core_init_mode(dwc);
2161         if (ret)
2162                 goto err_exit_debugfs;
2163
2164         pm_runtime_put(dev);
2165
2166         dma_set_max_seg_size(dev, UINT_MAX);
2167
2168         return 0;
2169
2170 err_exit_debugfs:
2171         dwc3_debugfs_exit(dwc);
2172         dwc3_event_buffers_cleanup(dwc);
2173         dwc3_phy_power_off(dwc);
2174         dwc3_phy_exit(dwc);
2175         dwc3_ulpi_exit(dwc);
2176 err_free_event_buffers:
2177         dwc3_free_event_buffers(dwc);
2178 err_allow_rpm:
2179         pm_runtime_allow(dev);
2180         pm_runtime_disable(dev);
2181         pm_runtime_dont_use_autosuspend(dev);
2182         pm_runtime_set_suspended(dev);
2183         pm_runtime_put_noidle(dev);
2184 err_disable_clks:
2185         dwc3_clk_disable(dwc);
2186 err_assert_reset:
2187         reset_control_assert(dwc->reset);
2188 err_put_psy:
2189         if (dwc->usb_psy)
2190                 power_supply_put(dwc->usb_psy);
2191
2192         return ret;
2193 }
2194
2195 static void dwc3_remove(struct platform_device *pdev)
2196 {
2197         struct dwc3     *dwc = platform_get_drvdata(pdev);
2198
2199         pm_runtime_get_sync(&pdev->dev);
2200
2201         dwc3_core_exit_mode(dwc);
2202         dwc3_debugfs_exit(dwc);
2203
2204         dwc3_core_exit(dwc);
2205         dwc3_ulpi_exit(dwc);
2206
2207         pm_runtime_allow(&pdev->dev);
2208         pm_runtime_disable(&pdev->dev);
2209         pm_runtime_dont_use_autosuspend(&pdev->dev);
2210         pm_runtime_put_noidle(&pdev->dev);
2211         /*
2212          * HACK: Clear the driver data, which is currently accessed by parent
2213          * glue drivers, before allowing the parent to suspend.
2214          */
2215         platform_set_drvdata(pdev, NULL);
2216         pm_runtime_set_suspended(&pdev->dev);
2217
2218         dwc3_free_event_buffers(dwc);
2219
2220         if (dwc->usb_psy)
2221                 power_supply_put(dwc->usb_psy);
2222 }
2223
2224 #ifdef CONFIG_PM
2225 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
2226 {
2227         int ret;
2228
2229         ret = reset_control_deassert(dwc->reset);
2230         if (ret)
2231                 return ret;
2232
2233         ret = dwc3_clk_enable(dwc);
2234         if (ret)
2235                 goto assert_reset;
2236
2237         ret = dwc3_core_init(dwc);
2238         if (ret)
2239                 goto disable_clks;
2240
2241         return 0;
2242
2243 disable_clks:
2244         dwc3_clk_disable(dwc);
2245 assert_reset:
2246         reset_control_assert(dwc->reset);
2247
2248         return ret;
2249 }
2250
2251 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
2252 {
2253         unsigned long   flags;
2254         u32 reg;
2255         int i;
2256
2257         switch (dwc->current_dr_role) {
2258         case DWC3_GCTL_PRTCAP_DEVICE:
2259                 if (pm_runtime_suspended(dwc->dev))
2260                         break;
2261                 dwc3_gadget_suspend(dwc);
2262                 synchronize_irq(dwc->irq_gadget);
2263                 dwc3_core_exit(dwc);
2264                 break;
2265         case DWC3_GCTL_PRTCAP_HOST:
2266                 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
2267                         dwc3_core_exit(dwc);
2268                         break;
2269                 }
2270
2271                 /* Let controller to suspend HSPHY before PHY driver suspends */
2272                 if (dwc->dis_u2_susphy_quirk ||
2273                     dwc->dis_enblslpm_quirk) {
2274                         for (i = 0; i < dwc->num_usb2_ports; i++) {
2275                                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
2276                                 reg |=  DWC3_GUSB2PHYCFG_ENBLSLPM |
2277                                         DWC3_GUSB2PHYCFG_SUSPHY;
2278                                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
2279                         }
2280
2281                         /* Give some time for USB2 PHY to suspend */
2282                         usleep_range(5000, 6000);
2283                 }
2284
2285                 for (i = 0; i < dwc->num_usb2_ports; i++)
2286                         phy_pm_runtime_put_sync(dwc->usb2_generic_phy[i]);
2287                 for (i = 0; i < dwc->num_usb3_ports; i++)
2288                         phy_pm_runtime_put_sync(dwc->usb3_generic_phy[i]);
2289                 break;
2290         case DWC3_GCTL_PRTCAP_OTG:
2291                 /* do nothing during runtime_suspend */
2292                 if (PMSG_IS_AUTO(msg))
2293                         break;
2294
2295                 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2296                         spin_lock_irqsave(&dwc->lock, flags);
2297                         dwc3_gadget_suspend(dwc);
2298                         spin_unlock_irqrestore(&dwc->lock, flags);
2299                         synchronize_irq(dwc->irq_gadget);
2300                 }
2301
2302                 dwc3_otg_exit(dwc);
2303                 dwc3_core_exit(dwc);
2304                 break;
2305         default:
2306                 /* do nothing */
2307                 break;
2308         }
2309
2310         return 0;
2311 }
2312
2313 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
2314 {
2315         unsigned long   flags;
2316         int             ret;
2317         u32             reg;
2318         int             i;
2319
2320         switch (dwc->current_dr_role) {
2321         case DWC3_GCTL_PRTCAP_DEVICE:
2322                 ret = dwc3_core_init_for_resume(dwc);
2323                 if (ret)
2324                         return ret;
2325
2326                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
2327                 dwc3_gadget_resume(dwc);
2328                 break;
2329         case DWC3_GCTL_PRTCAP_HOST:
2330                 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
2331                         ret = dwc3_core_init_for_resume(dwc);
2332                         if (ret)
2333                                 return ret;
2334                         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
2335                         break;
2336                 }
2337                 /* Restore GUSB2PHYCFG bits that were modified in suspend */
2338                 for (i = 0; i < dwc->num_usb2_ports; i++) {
2339                         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i));
2340                         if (dwc->dis_u2_susphy_quirk)
2341                                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
2342
2343                         if (dwc->dis_enblslpm_quirk)
2344                                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
2345
2346                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg);
2347                 }
2348
2349                 for (i = 0; i < dwc->num_usb2_ports; i++)
2350                         phy_pm_runtime_get_sync(dwc->usb2_generic_phy[i]);
2351                 for (i = 0; i < dwc->num_usb3_ports; i++)
2352                         phy_pm_runtime_get_sync(dwc->usb3_generic_phy[i]);
2353                 break;
2354         case DWC3_GCTL_PRTCAP_OTG:
2355                 /* nothing to do on runtime_resume */
2356                 if (PMSG_IS_AUTO(msg))
2357                         break;
2358
2359                 ret = dwc3_core_init_for_resume(dwc);
2360                 if (ret)
2361                         return ret;
2362
2363                 dwc3_set_prtcap(dwc, dwc->current_dr_role);
2364
2365                 dwc3_otg_init(dwc);
2366                 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
2367                         dwc3_otg_host_init(dwc);
2368                 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2369                         spin_lock_irqsave(&dwc->lock, flags);
2370                         dwc3_gadget_resume(dwc);
2371                         spin_unlock_irqrestore(&dwc->lock, flags);
2372                 }
2373
2374                 break;
2375         default:
2376                 /* do nothing */
2377                 break;
2378         }
2379
2380         return 0;
2381 }
2382
2383 static int dwc3_runtime_checks(struct dwc3 *dwc)
2384 {
2385         switch (dwc->current_dr_role) {
2386         case DWC3_GCTL_PRTCAP_DEVICE:
2387                 if (dwc->connected)
2388                         return -EBUSY;
2389                 break;
2390         case DWC3_GCTL_PRTCAP_HOST:
2391         default:
2392                 /* do nothing */
2393                 break;
2394         }
2395
2396         return 0;
2397 }
2398
2399 static int dwc3_runtime_suspend(struct device *dev)
2400 {
2401         struct dwc3     *dwc = dev_get_drvdata(dev);
2402         int             ret;
2403
2404         if (dwc3_runtime_checks(dwc))
2405                 return -EBUSY;
2406
2407         ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
2408         if (ret)
2409                 return ret;
2410
2411         return 0;
2412 }
2413
2414 static int dwc3_runtime_resume(struct device *dev)
2415 {
2416         struct dwc3     *dwc = dev_get_drvdata(dev);
2417         int             ret;
2418
2419         ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
2420         if (ret)
2421                 return ret;
2422
2423         switch (dwc->current_dr_role) {
2424         case DWC3_GCTL_PRTCAP_DEVICE:
2425                 dwc3_gadget_process_pending_events(dwc);
2426                 break;
2427         case DWC3_GCTL_PRTCAP_HOST:
2428         default:
2429                 /* do nothing */
2430                 break;
2431         }
2432
2433         pm_runtime_mark_last_busy(dev);
2434
2435         return 0;
2436 }
2437
2438 static int dwc3_runtime_idle(struct device *dev)
2439 {
2440         struct dwc3     *dwc = dev_get_drvdata(dev);
2441
2442         switch (dwc->current_dr_role) {
2443         case DWC3_GCTL_PRTCAP_DEVICE:
2444                 if (dwc3_runtime_checks(dwc))
2445                         return -EBUSY;
2446                 break;
2447         case DWC3_GCTL_PRTCAP_HOST:
2448         default:
2449                 /* do nothing */
2450                 break;
2451         }
2452
2453         pm_runtime_mark_last_busy(dev);
2454         pm_runtime_autosuspend(dev);
2455
2456         return 0;
2457 }
2458 #endif /* CONFIG_PM */
2459
2460 #ifdef CONFIG_PM_SLEEP
2461 static int dwc3_suspend(struct device *dev)
2462 {
2463         struct dwc3     *dwc = dev_get_drvdata(dev);
2464         int             ret;
2465
2466         ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
2467         if (ret)
2468                 return ret;
2469
2470         pinctrl_pm_select_sleep_state(dev);
2471
2472         return 0;
2473 }
2474
2475 static int dwc3_resume(struct device *dev)
2476 {
2477         struct dwc3     *dwc = dev_get_drvdata(dev);
2478         int             ret;
2479
2480         pinctrl_pm_select_default_state(dev);
2481
2482         pm_runtime_disable(dev);
2483         pm_runtime_set_active(dev);
2484
2485         ret = dwc3_resume_common(dwc, PMSG_RESUME);
2486         if (ret) {
2487                 pm_runtime_set_suspended(dev);
2488                 return ret;
2489         }
2490
2491         pm_runtime_enable(dev);
2492
2493         return 0;
2494 }
2495
2496 static void dwc3_complete(struct device *dev)
2497 {
2498         struct dwc3     *dwc = dev_get_drvdata(dev);
2499         u32             reg;
2500
2501         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
2502                         dwc->dis_split_quirk) {
2503                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
2504                 reg |= DWC3_GUCTL3_SPLITDISABLE;
2505                 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
2506         }
2507 }
2508 #else
2509 #define dwc3_complete NULL
2510 #endif /* CONFIG_PM_SLEEP */
2511
2512 static const struct dev_pm_ops dwc3_dev_pm_ops = {
2513         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
2514         .complete = dwc3_complete,
2515         SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
2516                         dwc3_runtime_idle)
2517 };
2518
2519 #ifdef CONFIG_OF
2520 static const struct of_device_id of_dwc3_match[] = {
2521         {
2522                 .compatible = "snps,dwc3"
2523         },
2524         {
2525                 .compatible = "synopsys,dwc3"
2526         },
2527         { },
2528 };
2529 MODULE_DEVICE_TABLE(of, of_dwc3_match);
2530 #endif
2531
2532 #ifdef CONFIG_ACPI
2533
2534 #define ACPI_ID_INTEL_BSW       "808622B7"
2535
2536 static const struct acpi_device_id dwc3_acpi_match[] = {
2537         { ACPI_ID_INTEL_BSW, 0 },
2538         { },
2539 };
2540 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2541 #endif
2542
2543 static struct platform_driver dwc3_driver = {
2544         .probe          = dwc3_probe,
2545         .remove_new     = dwc3_remove,
2546         .driver         = {
2547                 .name   = "dwc3",
2548                 .of_match_table = of_match_ptr(of_dwc3_match),
2549                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
2550                 .pm     = &dwc3_dev_pm_ops,
2551         },
2552 };
2553
2554 module_platform_driver(dwc3_driver);
2555
2556 MODULE_ALIAS("platform:dwc3");
2557 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
2558 MODULE_LICENSE("GPL v2");
2559 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");