1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * hcd.c - DesignWare HS OTG Controller host-mode routines
5 * Copyright (C) 2004-2013 Synopsys, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The names of the above-listed copyright holders may not be used
17 * to endorse or promote products derived from this software without
18 * specific prior written permission.
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 * This file contains the core HCD code, and implements the Linux hc_driver
42 #include <linux/kernel.h>
43 #include <linux/module.h>
44 #include <linux/spinlock.h>
45 #include <linux/interrupt.h>
46 #include <linux/platform_device.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/delay.h>
50 #include <linux/slab.h>
51 #include <linux/usb.h>
53 #include <linux/usb/hcd.h>
54 #include <linux/usb/ch11.h>
59 static void dwc2_port_resume(struct dwc2_hsotg *hsotg);
62 * =========================================================================
63 * Host Core Layer Functions
64 * =========================================================================
68 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
69 * used in both device and host modes
71 * @hsotg: Programming view of the DWC_otg controller
73 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
77 /* Clear any pending OTG Interrupts */
78 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
80 /* Clear any pending interrupts */
81 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
83 /* Enable the interrupts in the GINTMSK */
84 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
86 if (!hsotg->params.host_dma)
87 intmsk |= GINTSTS_RXFLVL;
88 if (!hsotg->params.external_id_pin_ctl)
89 intmsk |= GINTSTS_CONIDSTSCHNG;
91 intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP |
94 if (dwc2_is_device_mode(hsotg) && hsotg->params.lpm)
95 intmsk |= GINTSTS_LPMTRANRCVD;
97 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
101 * Initializes the FSLSPClkSel field of the HCFG register depending on the
104 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
108 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
109 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
110 hsotg->params.ulpi_fs_ls) ||
111 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
113 val = HCFG_FSLSPCLKSEL_48_MHZ;
115 /* High speed PHY running at full speed or high speed */
116 val = HCFG_FSLSPCLKSEL_30_60_MHZ;
119 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
120 hcfg = dwc2_readl(hsotg->regs + HCFG);
121 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
122 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
123 dwc2_writel(hcfg, hsotg->regs + HCFG);
126 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
128 u32 usbcfg, ggpio, i2cctl;
132 * core_init() is now called on every switch so only call the
133 * following for the first time through
136 dev_dbg(hsotg->dev, "FS PHY selected\n");
138 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
139 if (!(usbcfg & GUSBCFG_PHYSEL)) {
140 usbcfg |= GUSBCFG_PHYSEL;
141 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
143 /* Reset after a PHY select */
144 retval = dwc2_core_reset(hsotg, false);
148 "%s: Reset failed, aborting", __func__);
153 if (hsotg->params.activate_stm_fs_transceiver) {
154 ggpio = dwc2_readl(hsotg->regs + GGPIO);
155 if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) {
156 dev_dbg(hsotg->dev, "Activating transceiver\n");
158 * STM32F4x9 uses the GGPIO register as general
159 * core configuration register.
161 ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
162 dwc2_writel(ggpio, hsotg->regs + GGPIO);
168 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
169 * do this on HNP Dev/Host mode switches (done in dev_init and
172 if (dwc2_is_host_mode(hsotg))
173 dwc2_init_fs_ls_pclk_sel(hsotg);
175 if (hsotg->params.i2c_enable) {
176 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
178 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
179 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
180 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
181 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
183 /* Program GI2CCTL.I2CEn */
184 i2cctl = dwc2_readl(hsotg->regs + GI2CCTL);
185 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
186 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
187 i2cctl &= ~GI2CCTL_I2CEN;
188 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
189 i2cctl |= GI2CCTL_I2CEN;
190 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
196 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
198 u32 usbcfg, usbcfg_old;
204 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
208 * HS PHY parameters. These parameters are preserved during soft reset
209 * so only program the first time. Do a soft reset immediately after
212 switch (hsotg->params.phy_type) {
213 case DWC2_PHY_TYPE_PARAM_ULPI:
215 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
216 usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
217 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
218 if (hsotg->params.phy_ulpi_ddr)
219 usbcfg |= GUSBCFG_DDRSEL;
221 /* Set external VBUS indicator as needed. */
222 if (hsotg->params.oc_disable)
223 usbcfg |= (GUSBCFG_ULPI_INT_VBUS_IND |
224 GUSBCFG_INDICATORPASSTHROUGH);
226 case DWC2_PHY_TYPE_PARAM_UTMI:
227 /* UTMI+ interface */
228 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
229 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
230 if (hsotg->params.phy_utmi_width == 16)
231 usbcfg |= GUSBCFG_PHYIF16;
234 dev_err(hsotg->dev, "FS PHY selected at HS!\n");
238 if (usbcfg != usbcfg_old) {
239 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
241 /* Reset after setting the PHY parameters */
242 retval = dwc2_core_reset(hsotg, false);
245 "%s: Reset failed, aborting", __func__);
253 static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
258 if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
259 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) &&
260 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
261 /* If FS/LS mode with FS/LS PHY */
262 retval = dwc2_fs_phy_init(hsotg, select_phy);
267 retval = dwc2_hs_phy_init(hsotg, select_phy);
272 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
273 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
274 hsotg->params.ulpi_fs_ls) {
275 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
276 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
277 usbcfg |= GUSBCFG_ULPI_FS_LS;
278 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
279 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
281 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
282 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
283 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
284 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
290 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
292 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
294 switch (hsotg->hw_params.arch) {
295 case GHWCFG2_EXT_DMA_ARCH:
296 dev_err(hsotg->dev, "External DMA Mode not supported\n");
299 case GHWCFG2_INT_DMA_ARCH:
300 dev_dbg(hsotg->dev, "Internal DMA Mode\n");
301 if (hsotg->params.ahbcfg != -1) {
302 ahbcfg &= GAHBCFG_CTRL_MASK;
303 ahbcfg |= hsotg->params.ahbcfg &
308 case GHWCFG2_SLAVE_ONLY_ARCH:
310 dev_dbg(hsotg->dev, "Slave Only Mode\n");
314 if (hsotg->params.host_dma)
315 ahbcfg |= GAHBCFG_DMA_EN;
317 hsotg->params.dma_desc_enable = false;
319 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
324 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
328 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
329 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
331 switch (hsotg->hw_params.op_mode) {
332 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
333 if (hsotg->params.otg_cap ==
334 DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
335 usbcfg |= GUSBCFG_HNPCAP;
336 if (hsotg->params.otg_cap !=
337 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
338 usbcfg |= GUSBCFG_SRPCAP;
341 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
342 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
343 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
344 if (hsotg->params.otg_cap !=
345 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
346 usbcfg |= GUSBCFG_SRPCAP;
349 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE:
350 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE:
351 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST:
356 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
359 static int dwc2_vbus_supply_init(struct dwc2_hsotg *hsotg)
363 hsotg->vbus_supply = devm_regulator_get_optional(hsotg->dev, "vbus");
364 if (IS_ERR(hsotg->vbus_supply)) {
365 ret = PTR_ERR(hsotg->vbus_supply);
366 hsotg->vbus_supply = NULL;
367 return ret == -ENODEV ? 0 : ret;
370 return regulator_enable(hsotg->vbus_supply);
373 static int dwc2_vbus_supply_exit(struct dwc2_hsotg *hsotg)
375 if (hsotg->vbus_supply)
376 return regulator_disable(hsotg->vbus_supply);
382 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts
384 * @hsotg: Programming view of DWC_otg controller
386 static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
390 dev_dbg(hsotg->dev, "%s()\n", __func__);
392 /* Disable all interrupts */
393 dwc2_writel(0, hsotg->regs + GINTMSK);
394 dwc2_writel(0, hsotg->regs + HAINTMSK);
396 /* Enable the common interrupts */
397 dwc2_enable_common_interrupts(hsotg);
399 /* Enable host mode interrupts without disturbing common interrupts */
400 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
401 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
402 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
406 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts
408 * @hsotg: Programming view of DWC_otg controller
410 static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
412 u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
414 /* Disable host mode interrupts without disturbing common interrupts */
415 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
416 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT);
417 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
421 * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size
422 * For system that have a total fifo depth that is smaller than the default
425 * @hsotg: Programming view of DWC_otg controller
427 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg)
429 struct dwc2_core_params *params = &hsotg->params;
430 struct dwc2_hw_params *hw = &hsotg->hw_params;
431 u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size;
433 total_fifo_size = hw->total_fifo_size;
434 rxfsiz = params->host_rx_fifo_size;
435 nptxfsiz = params->host_nperio_tx_fifo_size;
436 ptxfsiz = params->host_perio_tx_fifo_size;
439 * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth
440 * allocation with support for high bandwidth endpoints. Synopsys
441 * defines MPS(Max Packet size) for a periodic EP=1024, and for
442 * non-periodic as 512.
444 if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) {
446 * For Buffer DMA mode/Scatter Gather DMA mode
447 * 2 * ((Largest Packet size / 4) + 1 + 1) + n
448 * with n = number of host channel.
449 * 2 * ((1024/4) + 2) = 516
451 rxfsiz = 516 + hw->host_channels;
454 * min non-periodic tx fifo depth
455 * 2 * (largest non-periodic USB packet used / 4)
461 * min periodic tx fifo depth
462 * (largest packet size*MC)/4
467 params->host_rx_fifo_size = rxfsiz;
468 params->host_nperio_tx_fifo_size = nptxfsiz;
469 params->host_perio_tx_fifo_size = ptxfsiz;
473 * If the summation of RX, NPTX and PTX fifo sizes is still
474 * bigger than the total_fifo_size, then we have a problem.
476 * We won't be able to allocate as many endpoints. Right now,
477 * we're just printing an error message, but ideally this FIFO
478 * allocation algorithm would be improved in the future.
480 * FIXME improve this FIFO allocation algorithm.
482 if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)))
483 dev_err(hsotg->dev, "invalid fifo sizes\n");
486 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
488 struct dwc2_core_params *params = &hsotg->params;
489 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz;
491 if (!params->enable_dynamic_fifo)
494 dwc2_calculate_dynamic_fifo(hsotg);
497 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
498 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
499 grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
500 grxfsiz |= params->host_rx_fifo_size <<
501 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
502 dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ);
503 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n",
504 dwc2_readl(hsotg->regs + GRXFSIZ));
506 /* Non-periodic Tx FIFO */
507 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
508 dwc2_readl(hsotg->regs + GNPTXFSIZ));
509 nptxfsiz = params->host_nperio_tx_fifo_size <<
510 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
511 nptxfsiz |= params->host_rx_fifo_size <<
512 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
513 dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ);
514 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
515 dwc2_readl(hsotg->regs + GNPTXFSIZ));
517 /* Periodic Tx FIFO */
518 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
519 dwc2_readl(hsotg->regs + HPTXFSIZ));
520 hptxfsiz = params->host_perio_tx_fifo_size <<
521 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
522 hptxfsiz |= (params->host_rx_fifo_size +
523 params->host_nperio_tx_fifo_size) <<
524 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
525 dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ);
526 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
527 dwc2_readl(hsotg->regs + HPTXFSIZ));
529 if (hsotg->params.en_multiple_tx_fifo &&
530 hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) {
532 * This feature was implemented in 2.91a version
533 * Global DFIFOCFG calculation for Host mode -
534 * include RxFIFO, NPTXFIFO and HPTXFIFO
536 dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
537 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
538 dfifocfg |= (params->host_rx_fifo_size +
539 params->host_nperio_tx_fifo_size +
540 params->host_perio_tx_fifo_size) <<
541 GDFIFOCFG_EPINFOBASE_SHIFT &
542 GDFIFOCFG_EPINFOBASE_MASK;
543 dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG);
548 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for
549 * the HFIR register according to PHY type and speed
551 * @hsotg: Programming view of DWC_otg controller
553 * NOTE: The caller can modify the value of the HFIR register only after the
554 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort)
557 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
561 int clock = 60; /* default value */
563 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
564 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
566 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
567 !(usbcfg & GUSBCFG_PHYIF16))
569 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type ==
570 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
572 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
573 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
575 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
576 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16))
578 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
579 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
581 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&
582 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
584 if ((usbcfg & GUSBCFG_PHYSEL) &&
585 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
588 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED)
589 /* High speed case */
590 return 125 * clock - 1;
593 return 1000 * clock - 1;
597 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination
600 * @hsotg: Programming view of DWC_otg controller
601 * @dest: Destination buffer for the packet
602 * @bytes: Number of bytes to copy to the destination
604 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
606 u32 __iomem *fifo = hsotg->regs + HCFIFO(0);
607 u32 *data_buf = (u32 *)dest;
608 int word_count = (bytes + 3) / 4;
612 * Todo: Account for the case where dest is not dword aligned. This
613 * requires reading data from the FIFO into a u32 temp buffer, then
614 * moving it into the data buffer.
617 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
619 for (i = 0; i < word_count; i++, data_buf++)
620 *data_buf = dwc2_readl(fifo);
624 * dwc2_dump_channel_info() - Prints the state of a host channel
626 * @hsotg: Programming view of DWC_otg controller
627 * @chan: Pointer to the channel to dump
629 * Must be called with interrupt disabled and spinlock held
631 * NOTE: This function will be removed once the peripheral controller code
632 * is integrated and the driver is stable
634 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
635 struct dwc2_host_chan *chan)
638 int num_channels = hsotg->params.host_channels;
649 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
650 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
651 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num));
652 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num));
654 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
655 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
657 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n",
659 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
660 chan->dev_addr, chan->ep_num, chan->ep_is_in);
661 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
662 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
663 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start);
664 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started);
665 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
666 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
667 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
668 (unsigned long)chan->xfer_dma);
669 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
670 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
671 dev_dbg(hsotg->dev, " NP inactive sched:\n");
672 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
674 dev_dbg(hsotg->dev, " %p\n", qh);
675 dev_dbg(hsotg->dev, " NP waiting sched:\n");
676 list_for_each_entry(qh, &hsotg->non_periodic_sched_waiting,
678 dev_dbg(hsotg->dev, " %p\n", qh);
679 dev_dbg(hsotg->dev, " NP active sched:\n");
680 list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
682 dev_dbg(hsotg->dev, " %p\n", qh);
683 dev_dbg(hsotg->dev, " Channels:\n");
684 for (i = 0; i < num_channels; i++) {
685 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
687 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan);
689 #endif /* VERBOSE_DEBUG */
692 static int _dwc2_hcd_start(struct usb_hcd *hcd);
694 static void dwc2_host_start(struct dwc2_hsotg *hsotg)
696 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
698 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
699 _dwc2_hcd_start(hcd);
702 static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
704 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
706 hcd->self.is_b_host = 0;
709 static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context,
710 int *hub_addr, int *hub_port)
712 struct urb *urb = context;
715 *hub_addr = urb->dev->tt->hub->devnum;
718 *hub_port = urb->dev->ttport;
722 * =========================================================================
723 * Low Level Host Channel Access Functions
724 * =========================================================================
727 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
728 struct dwc2_host_chan *chan)
730 u32 hcintmsk = HCINTMSK_CHHLTD;
732 switch (chan->ep_type) {
733 case USB_ENDPOINT_XFER_CONTROL:
734 case USB_ENDPOINT_XFER_BULK:
735 dev_vdbg(hsotg->dev, "control/bulk\n");
736 hcintmsk |= HCINTMSK_XFERCOMPL;
737 hcintmsk |= HCINTMSK_STALL;
738 hcintmsk |= HCINTMSK_XACTERR;
739 hcintmsk |= HCINTMSK_DATATGLERR;
740 if (chan->ep_is_in) {
741 hcintmsk |= HCINTMSK_BBLERR;
743 hcintmsk |= HCINTMSK_NAK;
744 hcintmsk |= HCINTMSK_NYET;
746 hcintmsk |= HCINTMSK_ACK;
749 if (chan->do_split) {
750 hcintmsk |= HCINTMSK_NAK;
751 if (chan->complete_split)
752 hcintmsk |= HCINTMSK_NYET;
754 hcintmsk |= HCINTMSK_ACK;
757 if (chan->error_state)
758 hcintmsk |= HCINTMSK_ACK;
761 case USB_ENDPOINT_XFER_INT:
763 dev_vdbg(hsotg->dev, "intr\n");
764 hcintmsk |= HCINTMSK_XFERCOMPL;
765 hcintmsk |= HCINTMSK_NAK;
766 hcintmsk |= HCINTMSK_STALL;
767 hcintmsk |= HCINTMSK_XACTERR;
768 hcintmsk |= HCINTMSK_DATATGLERR;
769 hcintmsk |= HCINTMSK_FRMOVRUN;
772 hcintmsk |= HCINTMSK_BBLERR;
773 if (chan->error_state)
774 hcintmsk |= HCINTMSK_ACK;
775 if (chan->do_split) {
776 if (chan->complete_split)
777 hcintmsk |= HCINTMSK_NYET;
779 hcintmsk |= HCINTMSK_ACK;
783 case USB_ENDPOINT_XFER_ISOC:
785 dev_vdbg(hsotg->dev, "isoc\n");
786 hcintmsk |= HCINTMSK_XFERCOMPL;
787 hcintmsk |= HCINTMSK_FRMOVRUN;
788 hcintmsk |= HCINTMSK_ACK;
790 if (chan->ep_is_in) {
791 hcintmsk |= HCINTMSK_XACTERR;
792 hcintmsk |= HCINTMSK_BBLERR;
796 dev_err(hsotg->dev, "## Unknown EP type ##\n");
800 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
802 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
805 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
806 struct dwc2_host_chan *chan)
808 u32 hcintmsk = HCINTMSK_CHHLTD;
811 * For Descriptor DMA mode core halts the channel on AHB error.
812 * Interrupt is not required.
814 if (!hsotg->params.dma_desc_enable) {
816 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
817 hcintmsk |= HCINTMSK_AHBERR;
820 dev_vdbg(hsotg->dev, "desc DMA enabled\n");
821 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
822 hcintmsk |= HCINTMSK_XFERCOMPL;
825 if (chan->error_state && !chan->do_split &&
826 chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
828 dev_vdbg(hsotg->dev, "setting ACK\n");
829 hcintmsk |= HCINTMSK_ACK;
830 if (chan->ep_is_in) {
831 hcintmsk |= HCINTMSK_DATATGLERR;
832 if (chan->ep_type != USB_ENDPOINT_XFER_INT)
833 hcintmsk |= HCINTMSK_NAK;
837 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
839 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
842 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
843 struct dwc2_host_chan *chan)
847 if (hsotg->params.host_dma) {
849 dev_vdbg(hsotg->dev, "DMA enabled\n");
850 dwc2_hc_enable_dma_ints(hsotg, chan);
853 dev_vdbg(hsotg->dev, "DMA disabled\n");
854 dwc2_hc_enable_slave_ints(hsotg, chan);
857 /* Enable the top level host channel interrupt */
858 intmsk = dwc2_readl(hsotg->regs + HAINTMSK);
859 intmsk |= 1 << chan->hc_num;
860 dwc2_writel(intmsk, hsotg->regs + HAINTMSK);
862 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
864 /* Make sure host channel interrupts are enabled */
865 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
866 intmsk |= GINTSTS_HCHINT;
867 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
869 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
873 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from
874 * a specific endpoint
876 * @hsotg: Programming view of DWC_otg controller
877 * @chan: Information needed to initialize the host channel
879 * The HCCHARn register is set up with the characteristics specified in chan.
880 * Host channel interrupts that may need to be serviced while this transfer is
881 * in progress are enabled.
883 static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
885 u8 hc_num = chan->hc_num;
891 dev_vdbg(hsotg->dev, "%s()\n", __func__);
893 /* Clear old interrupt conditions for this host channel */
894 hcintmsk = 0xffffffff;
895 hcintmsk &= ~HCINTMSK_RESERVED14_31;
896 dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num));
898 /* Enable channel interrupts required for this transfer */
899 dwc2_hc_enable_ints(hsotg, chan);
902 * Program the HCCHARn register with the endpoint characteristics for
903 * the current transfer
905 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK;
906 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK;
908 hcchar |= HCCHAR_EPDIR;
909 if (chan->speed == USB_SPEED_LOW)
910 hcchar |= HCCHAR_LSPDDEV;
911 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
912 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
913 dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num));
915 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
918 dev_vdbg(hsotg->dev, "%s: Channel %d\n",
920 dev_vdbg(hsotg->dev, " Dev Addr: %d\n",
922 dev_vdbg(hsotg->dev, " Ep Num: %d\n",
924 dev_vdbg(hsotg->dev, " Is In: %d\n",
926 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n",
927 chan->speed == USB_SPEED_LOW);
928 dev_vdbg(hsotg->dev, " Ep Type: %d\n",
930 dev_vdbg(hsotg->dev, " Max Pkt: %d\n",
934 /* Program the HCSPLT register for SPLITs */
935 if (chan->do_split) {
938 "Programming HC %d with split --> %s\n",
940 chan->complete_split ? "CSPLIT" : "SSPLIT");
941 if (chan->complete_split)
942 hcsplt |= HCSPLT_COMPSPLT;
943 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT &
945 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT &
947 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT &
950 dev_vdbg(hsotg->dev, " comp split %d\n",
951 chan->complete_split);
952 dev_vdbg(hsotg->dev, " xact pos %d\n",
954 dev_vdbg(hsotg->dev, " hub addr %d\n",
956 dev_vdbg(hsotg->dev, " hub port %d\n",
958 dev_vdbg(hsotg->dev, " is_in %d\n",
960 dev_vdbg(hsotg->dev, " Max Pkt %d\n",
962 dev_vdbg(hsotg->dev, " xferlen %d\n",
967 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num));
971 * dwc2_hc_halt() - Attempts to halt a host channel
973 * @hsotg: Controller register interface
974 * @chan: Host channel to halt
975 * @halt_status: Reason for halting the channel
977 * This function should only be called in Slave mode or to abort a transfer in
978 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the
979 * controller halts the channel when the transfer is complete or a condition
980 * occurs that requires application intervention.
982 * In slave mode, checks for a free request queue entry, then sets the Channel
983 * Enable and Channel Disable bits of the Host Channel Characteristics
984 * register of the specified channel to intiate the halt. If there is no free
985 * request queue entry, sets only the Channel Disable bit of the HCCHARn
986 * register to flush requests for this channel. In the latter case, sets a
987 * flag to indicate that the host channel needs to be halted when a request
988 * queue slot is open.
990 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
991 * HCCHARn register. The controller ensures there is space in the request
992 * queue before submitting the halt request.
994 * Some time may elapse before the core flushes any posted requests for this
995 * host channel and halts. The Channel Halted interrupt handler completes the
996 * deactivation of the host channel.
998 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
999 enum dwc2_halt_status halt_status)
1001 u32 nptxsts, hptxsts, hcchar;
1004 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1007 * In buffer DMA or external DMA mode channel can't be halted
1008 * for non-split periodic channels. At the end of the next
1009 * uframe/frame (in the worst case), the core generates a channel
1010 * halted and disables the channel automatically.
1012 if ((hsotg->params.g_dma && !hsotg->params.g_dma_desc) ||
1013 hsotg->hw_params.arch == GHWCFG2_EXT_DMA_ARCH) {
1014 if (!chan->do_split &&
1015 (chan->ep_type == USB_ENDPOINT_XFER_ISOC ||
1016 chan->ep_type == USB_ENDPOINT_XFER_INT)) {
1017 dev_err(hsotg->dev, "%s() Channel can't be halted\n",
1023 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS)
1024 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status);
1026 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1027 halt_status == DWC2_HC_XFER_AHB_ERR) {
1029 * Disable all channel interrupts except Ch Halted. The QTD
1030 * and QH state associated with this transfer has been cleared
1031 * (in the case of URB_DEQUEUE), so the channel needs to be
1032 * shut down carefully to prevent crashes.
1034 u32 hcintmsk = HCINTMSK_CHHLTD;
1036 dev_vdbg(hsotg->dev, "dequeue/error\n");
1037 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
1040 * Make sure no other interrupts besides halt are currently
1041 * pending. Handling another interrupt could cause a crash due
1042 * to the QTD and QH state.
1044 dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1047 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
1048 * even if the channel was already halted for some other
1051 chan->halt_status = halt_status;
1053 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1054 if (!(hcchar & HCCHAR_CHENA)) {
1056 * The channel is either already halted or it hasn't
1057 * started yet. In DMA mode, the transfer may halt if
1058 * it finishes normally or a condition occurs that
1059 * requires driver intervention. Don't want to halt
1060 * the channel again. In either Slave or DMA mode,
1061 * it's possible that the transfer has been assigned
1062 * to a channel, but not started yet when an URB is
1063 * dequeued. Don't want to halt a channel that hasn't
1069 if (chan->halt_pending) {
1071 * A halt has already been issued for this channel. This might
1072 * happen when a transfer is aborted by a higher level in
1075 dev_vdbg(hsotg->dev,
1076 "*** %s: Channel %d, chan->halt_pending already set ***\n",
1077 __func__, chan->hc_num);
1081 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1083 /* No need to set the bit in DDMA for disabling the channel */
1084 /* TODO check it everywhere channel is disabled */
1085 if (!hsotg->params.dma_desc_enable) {
1087 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
1088 hcchar |= HCCHAR_CHENA;
1091 dev_dbg(hsotg->dev, "desc DMA enabled\n");
1093 hcchar |= HCCHAR_CHDIS;
1095 if (!hsotg->params.host_dma) {
1097 dev_vdbg(hsotg->dev, "DMA not enabled\n");
1098 hcchar |= HCCHAR_CHENA;
1100 /* Check for space in the request queue to issue the halt */
1101 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1102 chan->ep_type == USB_ENDPOINT_XFER_BULK) {
1103 dev_vdbg(hsotg->dev, "control/bulk\n");
1104 nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
1105 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
1106 dev_vdbg(hsotg->dev, "Disabling channel\n");
1107 hcchar &= ~HCCHAR_CHENA;
1111 dev_vdbg(hsotg->dev, "isoc/intr\n");
1112 hptxsts = dwc2_readl(hsotg->regs + HPTXSTS);
1113 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
1114 hsotg->queuing_high_bandwidth) {
1116 dev_vdbg(hsotg->dev, "Disabling channel\n");
1117 hcchar &= ~HCCHAR_CHENA;
1122 dev_vdbg(hsotg->dev, "DMA enabled\n");
1125 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1126 chan->halt_status = halt_status;
1128 if (hcchar & HCCHAR_CHENA) {
1130 dev_vdbg(hsotg->dev, "Channel enabled\n");
1131 chan->halt_pending = 1;
1132 chan->halt_on_queue = 0;
1135 dev_vdbg(hsotg->dev, "Channel disabled\n");
1136 chan->halt_on_queue = 1;
1140 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1142 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n",
1144 dev_vdbg(hsotg->dev, " halt_pending: %d\n",
1145 chan->halt_pending);
1146 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n",
1147 chan->halt_on_queue);
1148 dev_vdbg(hsotg->dev, " halt_status: %d\n",
1154 * dwc2_hc_cleanup() - Clears the transfer state for a host channel
1156 * @hsotg: Programming view of DWC_otg controller
1157 * @chan: Identifies the host channel to clean up
1159 * This function is normally called after a transfer is done and the host
1160 * channel is being released
1162 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1166 chan->xfer_started = 0;
1168 list_del_init(&chan->split_order_list_entry);
1171 * Clear channel interrupt enables and any unhandled channel interrupt
1174 dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num));
1175 hcintmsk = 0xffffffff;
1176 hcintmsk &= ~HCINTMSK_RESERVED14_31;
1177 dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1181 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in
1182 * which frame a periodic transfer should occur
1184 * @hsotg: Programming view of DWC_otg controller
1185 * @chan: Identifies the host channel to set up and its properties
1186 * @hcchar: Current value of the HCCHAR register for the specified host channel
1188 * This function has no effect on non-periodic transfers
1190 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
1191 struct dwc2_host_chan *chan, u32 *hcchar)
1193 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1194 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1204 * Try to figure out if we're an even or odd frame. If we set
1205 * even and the current frame number is even the the transfer
1206 * will happen immediately. Similar if both are odd. If one is
1207 * even and the other is odd then the transfer will happen when
1208 * the frame number ticks.
1210 * There's a bit of a balancing act to get this right.
1211 * Sometimes we may want to send data in the current frame (AK
1212 * right away). We might want to do this if the frame number
1213 * _just_ ticked, but we might also want to do this in order
1214 * to continue a split transaction that happened late in a
1215 * microframe (so we didn't know to queue the next transfer
1216 * until the frame number had ticked). The problem is that we
1217 * need a lot of knowledge to know if there's actually still
1218 * time to send things or if it would be better to wait until
1221 * We can look at how much time is left in the current frame
1222 * and make a guess about whether we'll have time to transfer.
1226 /* Get speed host is running at */
1227 host_speed = (chan->speed != USB_SPEED_HIGH &&
1228 !chan->do_split) ? chan->speed : USB_SPEED_HIGH;
1230 /* See how many bytes are in the periodic FIFO right now */
1231 fifo_space = (dwc2_readl(hsotg->regs + HPTXSTS) &
1232 TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT;
1233 bytes_in_fifo = sizeof(u32) *
1234 (hsotg->params.host_perio_tx_fifo_size -
1238 * Roughly estimate bus time for everything in the periodic
1239 * queue + our new transfer. This is "rough" because we're
1240 * using a function that makes takes into account IN/OUT
1241 * and INT/ISO and we're just slamming in one value for all
1242 * transfers. This should be an over-estimate and that should
1243 * be OK, but we can probably tighten it.
1245 xfer_ns = usb_calc_bus_time(host_speed, false, false,
1246 chan->xfer_len + bytes_in_fifo);
1247 xfer_us = NS_TO_US(xfer_ns);
1249 /* See what frame number we'll be at by the time we finish */
1250 frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us);
1252 /* This is when we were scheduled to be on the wire */
1253 wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1);
1256 * If we'd finish _after_ the frame we're scheduled in then
1257 * it's hopeless. Just schedule right away and hope for the
1258 * best. Note that it _might_ be wise to call back into the
1259 * scheduler to pick a better frame, but this is better than
1262 if (dwc2_frame_num_gt(frame_number, wire_frame)) {
1263 dwc2_sch_vdbg(hsotg,
1264 "QH=%p EO MISS fr=%04x=>%04x (%+d)\n",
1265 chan->qh, wire_frame, frame_number,
1266 dwc2_frame_num_dec(frame_number,
1268 wire_frame = frame_number;
1271 * We picked a different frame number; communicate this
1272 * back to the scheduler so it doesn't try to schedule
1273 * another in the same frame.
1275 * Remember that next_active_frame is 1 before the wire
1278 chan->qh->next_active_frame =
1279 dwc2_frame_num_dec(frame_number, 1);
1283 *hcchar |= HCCHAR_ODDFRM;
1285 *hcchar &= ~HCCHAR_ODDFRM;
1289 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan)
1291 /* Set up the initial PID for the transfer */
1292 if (chan->speed == USB_SPEED_HIGH) {
1293 if (chan->ep_is_in) {
1294 if (chan->multi_count == 1)
1295 chan->data_pid_start = DWC2_HC_PID_DATA0;
1296 else if (chan->multi_count == 2)
1297 chan->data_pid_start = DWC2_HC_PID_DATA1;
1299 chan->data_pid_start = DWC2_HC_PID_DATA2;
1301 if (chan->multi_count == 1)
1302 chan->data_pid_start = DWC2_HC_PID_DATA0;
1304 chan->data_pid_start = DWC2_HC_PID_MDATA;
1307 chan->data_pid_start = DWC2_HC_PID_DATA0;
1312 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with
1315 * @hsotg: Programming view of DWC_otg controller
1316 * @chan: Information needed to initialize the host channel
1318 * This function should only be called in Slave mode. For a channel associated
1319 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel
1320 * associated with a periodic EP, the periodic Tx FIFO is written.
1322 * Upon return the xfer_buf and xfer_count fields in chan are incremented by
1323 * the number of bytes written to the Tx FIFO.
1325 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
1326 struct dwc2_host_chan *chan)
1329 u32 remaining_count;
1332 u32 __iomem *data_fifo;
1333 u32 *data_buf = (u32 *)chan->xfer_buf;
1336 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1338 data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num));
1340 remaining_count = chan->xfer_len - chan->xfer_count;
1341 if (remaining_count > chan->max_packet)
1342 byte_count = chan->max_packet;
1344 byte_count = remaining_count;
1346 dword_count = (byte_count + 3) / 4;
1348 if (((unsigned long)data_buf & 0x3) == 0) {
1349 /* xfer_buf is DWORD aligned */
1350 for (i = 0; i < dword_count; i++, data_buf++)
1351 dwc2_writel(*data_buf, data_fifo);
1353 /* xfer_buf is not DWORD aligned */
1354 for (i = 0; i < dword_count; i++, data_buf++) {
1355 u32 data = data_buf[0] | data_buf[1] << 8 |
1356 data_buf[2] << 16 | data_buf[3] << 24;
1357 dwc2_writel(data, data_fifo);
1361 chan->xfer_count += byte_count;
1362 chan->xfer_buf += byte_count;
1366 * dwc2_hc_do_ping() - Starts a PING transfer
1368 * @hsotg: Programming view of DWC_otg controller
1369 * @chan: Information needed to initialize the host channel
1371 * This function should only be called in Slave mode. The Do Ping bit is set in
1372 * the HCTSIZ register, then the channel is enabled.
1374 static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
1375 struct dwc2_host_chan *chan)
1381 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1384 hctsiz = TSIZ_DOPNG;
1385 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
1386 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1388 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1389 hcchar |= HCCHAR_CHENA;
1390 hcchar &= ~HCCHAR_CHDIS;
1391 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1395 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host
1396 * channel and starts the transfer
1398 * @hsotg: Programming view of DWC_otg controller
1399 * @chan: Information needed to initialize the host channel. The xfer_len value
1400 * may be reduced to accommodate the max widths of the XferSize and
1401 * PktCnt fields in the HCTSIZn register. The multi_count value may be
1402 * changed to reflect the final xfer_len value.
1404 * This function may be called in either Slave mode or DMA mode. In Slave mode,
1405 * the caller must ensure that there is sufficient space in the request queue
1408 * For an OUT transfer in Slave mode, it loads a data packet into the
1409 * appropriate FIFO. If necessary, additional data packets are loaded in the
1412 * For an IN transfer in Slave mode, a data packet is requested. The data
1413 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
1414 * additional data packets are requested in the Host ISR.
1416 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
1417 * register along with a packet count of 1 and the channel is enabled. This
1418 * causes a single PING transaction to occur. Other fields in HCTSIZ are
1419 * simply set to 0 since no data transfer occurs in this case.
1421 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
1422 * all the information required to perform the subsequent data transfer. In
1423 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
1424 * controller performs the entire PING protocol, then starts the data
1427 static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1428 struct dwc2_host_chan *chan)
1430 u32 max_hc_xfer_size = hsotg->params.max_transfer_size;
1431 u16 max_hc_pkt_count = hsotg->params.max_packet_count;
1438 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1440 if (chan->do_ping) {
1441 if (!hsotg->params.host_dma) {
1443 dev_vdbg(hsotg->dev, "ping, no DMA\n");
1444 dwc2_hc_do_ping(hsotg, chan);
1445 chan->xfer_started = 1;
1450 dev_vdbg(hsotg->dev, "ping, DMA\n");
1452 hctsiz |= TSIZ_DOPNG;
1455 if (chan->do_split) {
1457 dev_vdbg(hsotg->dev, "split\n");
1460 if (chan->complete_split && !chan->ep_is_in)
1462 * For CSPLIT OUT Transfer, set the size to 0 so the
1463 * core doesn't expect any data written to the FIFO
1466 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet)
1467 chan->xfer_len = chan->max_packet;
1468 else if (!chan->ep_is_in && chan->xfer_len > 188)
1469 chan->xfer_len = 188;
1471 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1474 /* For split set ec_mc for immediate retries */
1475 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1476 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1482 dev_vdbg(hsotg->dev, "no split\n");
1484 * Ensure that the transfer length and packet count will fit
1485 * in the widths allocated for them in the HCTSIZn register
1487 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1488 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1490 * Make sure the transfer size is no larger than one
1491 * (micro)frame's worth of data. (A check was done
1492 * when the periodic transfer was accepted to ensure
1493 * that a (micro)frame's worth of data can be
1494 * programmed into a channel.)
1496 u32 max_periodic_len =
1497 chan->multi_count * chan->max_packet;
1499 if (chan->xfer_len > max_periodic_len)
1500 chan->xfer_len = max_periodic_len;
1501 } else if (chan->xfer_len > max_hc_xfer_size) {
1503 * Make sure that xfer_len is a multiple of max packet
1507 max_hc_xfer_size - chan->max_packet + 1;
1510 if (chan->xfer_len > 0) {
1511 num_packets = (chan->xfer_len + chan->max_packet - 1) /
1513 if (num_packets > max_hc_pkt_count) {
1514 num_packets = max_hc_pkt_count;
1515 chan->xfer_len = num_packets * chan->max_packet;
1518 /* Need 1 packet for transfer length of 0 */
1524 * Always program an integral # of max packets for IN
1527 chan->xfer_len = num_packets * chan->max_packet;
1529 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1530 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1532 * Make sure that the multi_count field matches the
1533 * actual transfer length
1535 chan->multi_count = num_packets;
1537 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1538 dwc2_set_pid_isoc(chan);
1540 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1543 /* The ec_mc gets the multi_count for non-split */
1544 ec_mc = chan->multi_count;
1547 chan->start_pkt_count = num_packets;
1548 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
1549 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1550 TSIZ_SC_MC_PID_MASK;
1551 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1553 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
1554 hctsiz, chan->hc_num);
1556 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1558 dev_vdbg(hsotg->dev, " Xfer Size: %d\n",
1559 (hctsiz & TSIZ_XFERSIZE_MASK) >>
1560 TSIZ_XFERSIZE_SHIFT);
1561 dev_vdbg(hsotg->dev, " Num Pkts: %d\n",
1562 (hctsiz & TSIZ_PKTCNT_MASK) >>
1564 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1565 (hctsiz & TSIZ_SC_MC_PID_MASK) >>
1566 TSIZ_SC_MC_PID_SHIFT);
1569 if (hsotg->params.host_dma) {
1570 dma_addr_t dma_addr;
1572 if (chan->align_buf) {
1574 dev_vdbg(hsotg->dev, "align_buf\n");
1575 dma_addr = chan->align_buf;
1577 dma_addr = chan->xfer_dma;
1579 dwc2_writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num));
1582 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
1583 (unsigned long)dma_addr, chan->hc_num);
1586 /* Start the split */
1587 if (chan->do_split) {
1588 u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
1590 hcsplt |= HCSPLT_SPLTENA;
1591 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num));
1594 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1595 hcchar &= ~HCCHAR_MULTICNT_MASK;
1596 hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK;
1597 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1599 if (hcchar & HCCHAR_CHDIS)
1600 dev_warn(hsotg->dev,
1601 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1602 __func__, chan->hc_num, hcchar);
1604 /* Set host channel enable after all other setup is complete */
1605 hcchar |= HCCHAR_CHENA;
1606 hcchar &= ~HCCHAR_CHDIS;
1609 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1610 (hcchar & HCCHAR_MULTICNT_MASK) >>
1611 HCCHAR_MULTICNT_SHIFT);
1613 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1615 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1618 chan->xfer_started = 1;
1621 if (!hsotg->params.host_dma &&
1622 !chan->ep_is_in && chan->xfer_len > 0)
1623 /* Load OUT packet into the appropriate Tx FIFO */
1624 dwc2_hc_write_packet(hsotg, chan);
1628 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a
1629 * host channel and starts the transfer in Descriptor DMA mode
1631 * @hsotg: Programming view of DWC_otg controller
1632 * @chan: Information needed to initialize the host channel
1634 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
1635 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field
1636 * with micro-frame bitmap.
1638 * Initializes HCDMA register with descriptor list address and CTD value then
1639 * starts the transfer via enabling the channel.
1641 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1642 struct dwc2_host_chan *chan)
1648 hctsiz |= TSIZ_DOPNG;
1650 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1651 dwc2_set_pid_isoc(chan);
1653 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
1654 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1655 TSIZ_SC_MC_PID_MASK;
1657 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */
1658 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK;
1660 /* Non-zero only for high-speed interrupt endpoints */
1661 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK;
1664 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1666 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1667 chan->data_pid_start);
1668 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1);
1671 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1673 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr,
1674 chan->desc_list_sz, DMA_TO_DEVICE);
1676 dwc2_writel(chan->desc_list_addr, hsotg->regs + HCDMA(chan->hc_num));
1679 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n",
1680 &chan->desc_list_addr, chan->hc_num);
1682 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1683 hcchar &= ~HCCHAR_MULTICNT_MASK;
1684 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1685 HCCHAR_MULTICNT_MASK;
1687 if (hcchar & HCCHAR_CHDIS)
1688 dev_warn(hsotg->dev,
1689 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1690 __func__, chan->hc_num, hcchar);
1692 /* Set host channel enable after all other setup is complete */
1693 hcchar |= HCCHAR_CHENA;
1694 hcchar &= ~HCCHAR_CHDIS;
1697 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1698 (hcchar & HCCHAR_MULTICNT_MASK) >>
1699 HCCHAR_MULTICNT_SHIFT);
1701 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1703 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1706 chan->xfer_started = 1;
1711 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by
1712 * a previous call to dwc2_hc_start_transfer()
1714 * @hsotg: Programming view of DWC_otg controller
1715 * @chan: Information needed to initialize the host channel
1717 * The caller must ensure there is sufficient space in the request queue and Tx
1718 * Data FIFO. This function should only be called in Slave mode. In DMA mode,
1719 * the controller acts autonomously to complete transfers programmed to a host
1722 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
1723 * if there is any data remaining to be queued. For an IN transfer, another
1724 * data packet is always requested. For the SETUP phase of a control transfer,
1725 * this function does nothing.
1727 * Return: 1 if a new request is queued, 0 if no more requests are required
1730 static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
1731 struct dwc2_host_chan *chan)
1734 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1738 /* SPLITs always queue just once per channel */
1741 if (chan->data_pid_start == DWC2_HC_PID_SETUP)
1742 /* SETUPs are queued only once since they can't be NAK'd */
1745 if (chan->ep_is_in) {
1747 * Always queue another request for other IN transfers. If
1748 * back-to-back INs are issued and NAKs are received for both,
1749 * the driver may still be processing the first NAK when the
1750 * second NAK is received. When the interrupt handler clears
1751 * the NAK interrupt for the first NAK, the second NAK will
1752 * not be seen. So we can't depend on the NAK interrupt
1753 * handler to requeue a NAK'd request. Instead, IN requests
1754 * are issued each time this function is called. When the
1755 * transfer completes, the extra requests for the channel will
1758 u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1760 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1761 hcchar |= HCCHAR_CHENA;
1762 hcchar &= ~HCCHAR_CHDIS;
1764 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n",
1766 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1773 if (chan->xfer_count < chan->xfer_len) {
1774 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1775 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1776 u32 hcchar = dwc2_readl(hsotg->regs +
1777 HCCHAR(chan->hc_num));
1779 dwc2_hc_set_even_odd_frame(hsotg, chan,
1783 /* Load OUT packet into the appropriate Tx FIFO */
1784 dwc2_hc_write_packet(hsotg, chan);
1793 * =========================================================================
1795 * =========================================================================
1799 * Processes all the URBs in a single list of QHs. Completes them with
1800 * -ETIMEDOUT and frees the QTD.
1802 * Must be called with interrupt disabled and spinlock held
1804 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
1805 struct list_head *qh_list)
1807 struct dwc2_qh *qh, *qh_tmp;
1808 struct dwc2_qtd *qtd, *qtd_tmp;
1810 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1811 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1813 dwc2_host_complete(hsotg, qtd, -ECONNRESET);
1814 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1819 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
1820 struct list_head *qh_list)
1822 struct dwc2_qtd *qtd, *qtd_tmp;
1823 struct dwc2_qh *qh, *qh_tmp;
1824 unsigned long flags;
1827 /* The list hasn't been initialized yet */
1830 spin_lock_irqsave(&hsotg->lock, flags);
1832 /* Ensure there are no QTDs or URBs left */
1833 dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
1835 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1836 dwc2_hcd_qh_unlink(hsotg, qh);
1838 /* Free each QTD in the QH's QTD list */
1839 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1841 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1843 if (qh->channel && qh->channel->qh == qh)
1844 qh->channel->qh = NULL;
1846 spin_unlock_irqrestore(&hsotg->lock, flags);
1847 dwc2_hcd_qh_free(hsotg, qh);
1848 spin_lock_irqsave(&hsotg->lock, flags);
1851 spin_unlock_irqrestore(&hsotg->lock, flags);
1855 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
1856 * and periodic schedules. The QTD associated with each URB is removed from
1857 * the schedule and freed. This function may be called when a disconnect is
1858 * detected or when the HCD is being stopped.
1860 * Must be called with interrupt disabled and spinlock held
1862 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
1864 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
1865 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_waiting);
1866 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
1867 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
1868 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
1869 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
1870 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
1874 * dwc2_hcd_start() - Starts the HCD when switching to Host mode
1876 * @hsotg: Pointer to struct dwc2_hsotg
1878 void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
1882 if (hsotg->op_state == OTG_STATE_B_HOST) {
1884 * Reset the port. During a HNP mode switch the reset
1885 * needs to occur within 1ms and have a duration of at
1888 hprt0 = dwc2_read_hprt0(hsotg);
1890 dwc2_writel(hprt0, hsotg->regs + HPRT0);
1893 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
1894 msecs_to_jiffies(50));
1897 /* Must be called with interrupt disabled and spinlock held */
1898 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
1900 int num_channels = hsotg->params.host_channels;
1901 struct dwc2_host_chan *channel;
1905 if (!hsotg->params.host_dma) {
1906 /* Flush out any channel requests in slave mode */
1907 for (i = 0; i < num_channels; i++) {
1908 channel = hsotg->hc_ptr_array[i];
1909 if (!list_empty(&channel->hc_list_entry))
1911 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1912 if (hcchar & HCCHAR_CHENA) {
1913 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
1914 hcchar |= HCCHAR_CHDIS;
1915 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
1920 for (i = 0; i < num_channels; i++) {
1921 channel = hsotg->hc_ptr_array[i];
1922 if (!list_empty(&channel->hc_list_entry))
1924 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1925 if (hcchar & HCCHAR_CHENA) {
1926 /* Halt the channel */
1927 hcchar |= HCCHAR_CHDIS;
1928 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
1931 dwc2_hc_cleanup(hsotg, channel);
1932 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
1934 * Added for Descriptor DMA to prevent channel double cleanup in
1935 * release_channel_ddma(), which is called from ep_disable when
1936 * device disconnects
1940 /* All channels have been freed, mark them available */
1941 if (hsotg->params.uframe_sched) {
1942 hsotg->available_host_channels =
1943 hsotg->params.host_channels;
1945 hsotg->non_periodic_channels = 0;
1946 hsotg->periodic_channels = 0;
1951 * dwc2_hcd_connect() - Handles connect of the HCD
1953 * @hsotg: Pointer to struct dwc2_hsotg
1955 * Must be called with interrupt disabled and spinlock held
1957 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg)
1959 if (hsotg->lx_state != DWC2_L0)
1960 usb_hcd_resume_root_hub(hsotg->priv);
1962 hsotg->flags.b.port_connect_status_change = 1;
1963 hsotg->flags.b.port_connect_status = 1;
1967 * dwc2_hcd_disconnect() - Handles disconnect of the HCD
1969 * @hsotg: Pointer to struct dwc2_hsotg
1970 * @force: If true, we won't try to reconnect even if we see device connected.
1972 * Must be called with interrupt disabled and spinlock held
1974 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
1979 /* Set status flags for the hub driver */
1980 hsotg->flags.b.port_connect_status_change = 1;
1981 hsotg->flags.b.port_connect_status = 0;
1984 * Shutdown any transfers in process by clearing the Tx FIFO Empty
1985 * interrupt mask and status bits and disabling subsequent host
1986 * channel interrupts.
1988 intr = dwc2_readl(hsotg->regs + GINTMSK);
1989 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
1990 dwc2_writel(intr, hsotg->regs + GINTMSK);
1991 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
1992 dwc2_writel(intr, hsotg->regs + GINTSTS);
1995 * Turn off the vbus power only if the core has transitioned to device
1996 * mode. If still in host mode, need to keep power on to detect a
1999 if (dwc2_is_device_mode(hsotg)) {
2000 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
2001 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
2002 dwc2_writel(0, hsotg->regs + HPRT0);
2005 dwc2_disable_host_interrupts(hsotg);
2008 /* Respond with an error status to all URBs in the schedule */
2009 dwc2_kill_all_urbs(hsotg);
2011 if (dwc2_is_host_mode(hsotg))
2012 /* Clean up any host channels that were in use */
2013 dwc2_hcd_cleanup_channels(hsotg);
2015 dwc2_host_disconnect(hsotg);
2018 * Add an extra check here to see if we're actually connected but
2019 * we don't have a detection interrupt pending. This can happen if:
2020 * 1. hardware sees connect
2021 * 2. hardware sees disconnect
2022 * 3. hardware sees connect
2023 * 4. dwc2_port_intr() - clears connect interrupt
2024 * 5. dwc2_handle_common_intr() - calls here
2026 * Without the extra check here we will end calling disconnect
2027 * and won't get any future interrupts to handle the connect.
2030 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
2031 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS))
2032 dwc2_hcd_connect(hsotg);
2037 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
2039 * @hsotg: Pointer to struct dwc2_hsotg
2041 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
2043 if (hsotg->bus_suspended) {
2044 hsotg->flags.b.port_suspend_change = 1;
2045 usb_hcd_resume_root_hub(hsotg->priv);
2048 if (hsotg->lx_state == DWC2_L1)
2049 hsotg->flags.b.port_l1_change = 1;
2053 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
2055 * @hsotg: Pointer to struct dwc2_hsotg
2057 * Must be called with interrupt disabled and spinlock held
2059 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
2061 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
2064 * The root hub should be disconnected before this function is called.
2065 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
2066 * and the QH lists (via ..._hcd_endpoint_disable).
2069 /* Turn off all host-specific interrupts */
2070 dwc2_disable_host_interrupts(hsotg);
2072 /* Turn off the vbus power */
2073 dev_dbg(hsotg->dev, "PortPower off\n");
2074 dwc2_writel(0, hsotg->regs + HPRT0);
2077 /* Caller must hold driver lock */
2078 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
2079 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh,
2080 struct dwc2_qtd *qtd)
2086 if (!hsotg->flags.b.port_connect_status) {
2087 /* No longer connected */
2088 dev_err(hsotg->dev, "Not connected\n");
2092 dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
2094 /* Some configurations cannot support LS traffic on a FS root port */
2095 if ((dev_speed == USB_SPEED_LOW) &&
2096 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
2097 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
2098 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
2099 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
2101 if (prtspd == HPRT0_SPD_FULL_SPEED)
2108 dwc2_hcd_qtd_init(qtd, urb);
2109 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh);
2112 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
2117 intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
2118 if (!(intr_mask & GINTSTS_SOF)) {
2119 enum dwc2_transaction_type tr_type;
2121 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
2122 !(qtd->urb->flags & URB_GIVEBACK_ASAP))
2124 * Do not schedule SG transactions until qtd has
2125 * URB_GIVEBACK_ASAP set
2129 tr_type = dwc2_hcd_select_transactions(hsotg);
2130 if (tr_type != DWC2_TRANSACTION_NONE)
2131 dwc2_hcd_queue_transactions(hsotg, tr_type);
2137 /* Must be called with interrupt disabled and spinlock held */
2138 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
2139 struct dwc2_hcd_urb *urb)
2142 struct dwc2_qtd *urb_qtd;
2146 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
2152 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
2158 if (urb_qtd->in_process && qh->channel) {
2159 dwc2_dump_channel_info(hsotg, qh->channel);
2161 /* The QTD is in process (it has been assigned to a channel) */
2162 if (hsotg->flags.b.port_connect_status)
2164 * If still connected (i.e. in host mode), halt the
2165 * channel so it can be used for other transfers. If
2166 * no longer connected, the host registers can't be
2167 * written to halt the channel since the core is in
2170 dwc2_hc_halt(hsotg, qh->channel,
2171 DWC2_HC_XFER_URB_DEQUEUE);
2175 * Free the QTD and clean up the associated QH. Leave the QH in the
2176 * schedule if it has any remaining QTDs.
2178 if (!hsotg->params.dma_desc_enable) {
2179 u8 in_process = urb_qtd->in_process;
2181 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
2183 dwc2_hcd_qh_deactivate(hsotg, qh, 0);
2185 } else if (list_empty(&qh->qtd_list)) {
2186 dwc2_hcd_qh_unlink(hsotg, qh);
2189 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
2195 /* Must NOT be called with interrupt disabled or spinlock held */
2196 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
2197 struct usb_host_endpoint *ep, int retry)
2199 struct dwc2_qtd *qtd, *qtd_tmp;
2201 unsigned long flags;
2204 spin_lock_irqsave(&hsotg->lock, flags);
2212 while (!list_empty(&qh->qtd_list) && retry--) {
2215 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
2220 spin_unlock_irqrestore(&hsotg->lock, flags);
2222 spin_lock_irqsave(&hsotg->lock, flags);
2230 dwc2_hcd_qh_unlink(hsotg, qh);
2232 /* Free each QTD in the QH's QTD list */
2233 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
2234 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
2238 if (qh->channel && qh->channel->qh == qh)
2239 qh->channel->qh = NULL;
2241 spin_unlock_irqrestore(&hsotg->lock, flags);
2243 dwc2_hcd_qh_free(hsotg, qh);
2249 spin_unlock_irqrestore(&hsotg->lock, flags);
2254 /* Must be called with interrupt disabled and spinlock held */
2255 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
2256 struct usb_host_endpoint *ep)
2258 struct dwc2_qh *qh = ep->hcpriv;
2263 qh->data_toggle = DWC2_HC_PID_DATA0;
2269 * dwc2_core_init() - Initializes the DWC_otg controller registers and
2270 * prepares the core for device mode or host mode operation
2272 * @hsotg: Programming view of the DWC_otg controller
2273 * @initial_setup: If true then this is the first init for this instance.
2275 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
2280 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2282 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2284 /* Set ULPI External VBUS bit if needed */
2285 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
2286 if (hsotg->params.phy_ulpi_ext_vbus)
2287 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV;
2289 /* Set external TS Dline pulsing bit if needed */
2290 usbcfg &= ~GUSBCFG_TERMSELDLPULSE;
2291 if (hsotg->params.ts_dline)
2292 usbcfg |= GUSBCFG_TERMSELDLPULSE;
2294 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
2297 * Reset the Controller
2299 * We only need to reset the controller if this is a re-init.
2300 * For the first init we know for sure that earlier code reset us (it
2301 * needed to in order to properly detect various parameters).
2303 if (!initial_setup) {
2304 retval = dwc2_core_reset(hsotg, false);
2306 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n",
2313 * This needs to happen in FS mode before any other programming occurs
2315 retval = dwc2_phy_init(hsotg, initial_setup);
2319 /* Program the GAHBCFG Register */
2320 retval = dwc2_gahbcfg_init(hsotg);
2324 /* Program the GUSBCFG register */
2325 dwc2_gusbcfg_init(hsotg);
2327 /* Program the GOTGCTL register */
2328 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2329 otgctl &= ~GOTGCTL_OTGVER;
2330 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
2332 /* Clear the SRP success bit for FS-I2c */
2333 hsotg->srp_success = 0;
2335 /* Enable common interrupts */
2336 dwc2_enable_common_interrupts(hsotg);
2339 * Do device or host initialization based on mode during PCD and
2340 * HCD initialization
2342 if (dwc2_is_host_mode(hsotg)) {
2343 dev_dbg(hsotg->dev, "Host Mode\n");
2344 hsotg->op_state = OTG_STATE_A_HOST;
2346 dev_dbg(hsotg->dev, "Device Mode\n");
2347 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
2354 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for
2357 * @hsotg: Programming view of DWC_otg controller
2359 * This function flushes the Tx and Rx FIFOs and flushes any entries in the
2360 * request queues. Host channels are reset to ensure that they are ready for
2361 * performing transfers.
2363 static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2365 u32 hcfg, hfir, otgctl, usbcfg;
2367 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2369 /* Set HS/FS Timeout Calibration to 7 (max available value).
2370 * The number of PHY clocks that the application programs in
2371 * this field is added to the high/full speed interpacket timeout
2372 * duration in the core to account for any additional delays
2373 * introduced by the PHY. This can be required, because the delay
2374 * introduced by the PHY in generating the linestate condition
2375 * can vary from one PHY to another.
2377 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2378 usbcfg |= GUSBCFG_TOUTCAL(7);
2379 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
2381 /* Restart the Phy Clock */
2382 dwc2_writel(0, hsotg->regs + PCGCTL);
2384 /* Initialize Host Configuration Register */
2385 dwc2_init_fs_ls_pclk_sel(hsotg);
2386 if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
2387 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) {
2388 hcfg = dwc2_readl(hsotg->regs + HCFG);
2389 hcfg |= HCFG_FSLSSUPP;
2390 dwc2_writel(hcfg, hsotg->regs + HCFG);
2394 * This bit allows dynamic reloading of the HFIR register during
2395 * runtime. This bit needs to be programmed during initial configuration
2396 * and its value must not be changed during runtime.
2398 if (hsotg->params.reload_ctl) {
2399 hfir = dwc2_readl(hsotg->regs + HFIR);
2400 hfir |= HFIR_RLDCTRL;
2401 dwc2_writel(hfir, hsotg->regs + HFIR);
2404 if (hsotg->params.dma_desc_enable) {
2405 u32 op_mode = hsotg->hw_params.op_mode;
2407 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
2408 !hsotg->hw_params.dma_desc_enable ||
2409 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
2410 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
2411 op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
2413 "Hardware does not support descriptor DMA mode -\n");
2415 "falling back to buffer DMA mode.\n");
2416 hsotg->params.dma_desc_enable = false;
2418 hcfg = dwc2_readl(hsotg->regs + HCFG);
2419 hcfg |= HCFG_DESCDMA;
2420 dwc2_writel(hcfg, hsotg->regs + HCFG);
2424 /* Configure data FIFO sizes */
2425 dwc2_config_fifos(hsotg);
2427 /* TODO - check this */
2428 /* Clear Host Set HNP Enable in the OTG Control Register */
2429 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2430 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2431 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
2433 /* Make sure the FIFOs are flushed */
2434 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
2435 dwc2_flush_rx_fifo(hsotg);
2437 /* Clear Host Set HNP Enable in the OTG Control Register */
2438 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2439 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2440 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
2442 if (!hsotg->params.dma_desc_enable) {
2443 int num_channels, i;
2446 /* Flush out any leftover queued requests */
2447 num_channels = hsotg->params.host_channels;
2448 for (i = 0; i < num_channels; i++) {
2449 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2450 hcchar &= ~HCCHAR_CHENA;
2451 hcchar |= HCCHAR_CHDIS;
2452 hcchar &= ~HCCHAR_EPDIR;
2453 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
2456 /* Halt all channels to put them into a known state */
2457 for (i = 0; i < num_channels; i++) {
2458 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2459 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
2460 hcchar &= ~HCCHAR_EPDIR;
2461 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
2462 dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
2465 if (dwc2_hsotg_wait_bit_clear(hsotg, HCCHAR(i),
2466 HCCHAR_CHENA, 1000)) {
2467 dev_warn(hsotg->dev, "Unable to clear enable on channel %d\n",
2473 /* Enable ACG feature in host mode, if supported */
2474 dwc2_enable_acg(hsotg);
2476 /* Turn on the vbus power */
2477 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state);
2478 if (hsotg->op_state == OTG_STATE_A_HOST) {
2479 u32 hprt0 = dwc2_read_hprt0(hsotg);
2481 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n",
2482 !!(hprt0 & HPRT0_PWR));
2483 if (!(hprt0 & HPRT0_PWR)) {
2485 dwc2_writel(hprt0, hsotg->regs + HPRT0);
2489 dwc2_enable_host_interrupts(hsotg);
2493 * Initializes dynamic portions of the DWC_otg HCD state
2495 * Must be called with interrupt disabled and spinlock held
2497 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
2499 struct dwc2_host_chan *chan, *chan_tmp;
2503 hsotg->flags.d32 = 0;
2504 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
2506 if (hsotg->params.uframe_sched) {
2507 hsotg->available_host_channels =
2508 hsotg->params.host_channels;
2510 hsotg->non_periodic_channels = 0;
2511 hsotg->periodic_channels = 0;
2515 * Put all channels in the free channel list and clean up channel
2518 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
2520 list_del_init(&chan->hc_list_entry);
2522 num_channels = hsotg->params.host_channels;
2523 for (i = 0; i < num_channels; i++) {
2524 chan = hsotg->hc_ptr_array[i];
2525 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
2526 dwc2_hc_cleanup(hsotg, chan);
2529 /* Initialize the DWC core for host mode operation */
2530 dwc2_core_host_init(hsotg);
2533 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
2534 struct dwc2_host_chan *chan,
2535 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
2537 int hub_addr, hub_port;
2540 chan->xact_pos = qtd->isoc_split_pos;
2541 chan->complete_split = qtd->complete_split;
2542 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
2543 chan->hub_addr = (u8)hub_addr;
2544 chan->hub_port = (u8)hub_port;
2547 static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
2548 struct dwc2_host_chan *chan,
2549 struct dwc2_qtd *qtd)
2551 struct dwc2_hcd_urb *urb = qtd->urb;
2552 struct dwc2_hcd_iso_packet_desc *frame_desc;
2554 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
2555 case USB_ENDPOINT_XFER_CONTROL:
2556 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
2558 switch (qtd->control_phase) {
2559 case DWC2_CONTROL_SETUP:
2560 dev_vdbg(hsotg->dev, " Control setup transaction\n");
2563 chan->data_pid_start = DWC2_HC_PID_SETUP;
2564 if (hsotg->params.host_dma)
2565 chan->xfer_dma = urb->setup_dma;
2567 chan->xfer_buf = urb->setup_packet;
2571 case DWC2_CONTROL_DATA:
2572 dev_vdbg(hsotg->dev, " Control data transaction\n");
2573 chan->data_pid_start = qtd->data_toggle;
2576 case DWC2_CONTROL_STATUS:
2578 * Direction is opposite of data direction or IN if no
2581 dev_vdbg(hsotg->dev, " Control status transaction\n");
2582 if (urb->length == 0)
2586 dwc2_hcd_is_pipe_out(&urb->pipe_info);
2589 chan->data_pid_start = DWC2_HC_PID_DATA1;
2591 if (hsotg->params.host_dma)
2592 chan->xfer_dma = hsotg->status_buf_dma;
2594 chan->xfer_buf = hsotg->status_buf;
2599 case USB_ENDPOINT_XFER_BULK:
2600 chan->ep_type = USB_ENDPOINT_XFER_BULK;
2603 case USB_ENDPOINT_XFER_INT:
2604 chan->ep_type = USB_ENDPOINT_XFER_INT;
2607 case USB_ENDPOINT_XFER_ISOC:
2608 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
2609 if (hsotg->params.dma_desc_enable)
2612 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
2613 frame_desc->status = 0;
2615 if (hsotg->params.host_dma) {
2616 chan->xfer_dma = urb->dma;
2617 chan->xfer_dma += frame_desc->offset +
2618 qtd->isoc_split_offset;
2620 chan->xfer_buf = urb->buf;
2621 chan->xfer_buf += frame_desc->offset +
2622 qtd->isoc_split_offset;
2625 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
2627 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
2628 if (chan->xfer_len <= 188)
2629 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
2631 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
2637 static int dwc2_alloc_split_dma_aligned_buf(struct dwc2_hsotg *hsotg,
2639 struct dwc2_host_chan *chan)
2641 if (!hsotg->unaligned_cache ||
2642 chan->max_packet > DWC2_KMEM_UNALIGNED_BUF_SIZE)
2645 if (!qh->dw_align_buf) {
2646 qh->dw_align_buf = kmem_cache_alloc(hsotg->unaligned_cache,
2647 GFP_ATOMIC | GFP_DMA);
2648 if (!qh->dw_align_buf)
2652 qh->dw_align_buf_dma = dma_map_single(hsotg->dev, qh->dw_align_buf,
2653 DWC2_KMEM_UNALIGNED_BUF_SIZE,
2656 if (dma_mapping_error(hsotg->dev, qh->dw_align_buf_dma)) {
2657 dev_err(hsotg->dev, "can't map align_buf\n");
2658 chan->align_buf = 0;
2662 chan->align_buf = qh->dw_align_buf_dma;
2666 #define DWC2_USB_DMA_ALIGN 4
2668 static void dwc2_free_dma_aligned_buffer(struct urb *urb)
2670 void *stored_xfer_buffer;
2673 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
2676 /* Restore urb->transfer_buffer from the end of the allocated area */
2677 memcpy(&stored_xfer_buffer, urb->transfer_buffer +
2678 urb->transfer_buffer_length, sizeof(urb->transfer_buffer));
2680 if (usb_urb_dir_in(urb)) {
2681 if (usb_pipeisoc(urb->pipe))
2682 length = urb->transfer_buffer_length;
2684 length = urb->actual_length;
2686 memcpy(stored_xfer_buffer, urb->transfer_buffer, length);
2688 kfree(urb->transfer_buffer);
2689 urb->transfer_buffer = stored_xfer_buffer;
2691 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
2694 static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
2697 size_t kmalloc_size;
2699 if (urb->num_sgs || urb->sg ||
2700 urb->transfer_buffer_length == 0 ||
2701 !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1)))
2705 * Allocate a buffer with enough padding for original transfer_buffer
2706 * pointer. This allocation is guaranteed to be aligned properly for
2709 kmalloc_size = urb->transfer_buffer_length +
2710 sizeof(urb->transfer_buffer);
2712 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
2717 * Position value of original urb->transfer_buffer pointer to the end
2718 * of allocation for later referencing
2720 memcpy(kmalloc_ptr + urb->transfer_buffer_length,
2721 &urb->transfer_buffer, sizeof(urb->transfer_buffer));
2723 if (usb_urb_dir_out(urb))
2724 memcpy(kmalloc_ptr, urb->transfer_buffer,
2725 urb->transfer_buffer_length);
2726 urb->transfer_buffer = kmalloc_ptr;
2728 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
2733 static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
2738 /* We assume setup_dma is always aligned; warn if not */
2739 WARN_ON_ONCE(urb->setup_dma &&
2740 (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1)));
2742 ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags);
2746 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2748 dwc2_free_dma_aligned_buffer(urb);
2753 static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
2755 usb_hcd_unmap_urb_for_dma(hcd, urb);
2756 dwc2_free_dma_aligned_buffer(urb);
2760 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
2761 * channel and initializes the host channel to perform the transactions. The
2762 * host channel is removed from the free list.
2764 * @hsotg: The HCD state structure
2765 * @qh: Transactions from the first QTD for this QH are selected and assigned
2766 * to a free host channel
2768 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
2770 struct dwc2_host_chan *chan;
2771 struct dwc2_hcd_urb *urb;
2772 struct dwc2_qtd *qtd;
2775 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
2777 if (list_empty(&qh->qtd_list)) {
2778 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
2782 if (list_empty(&hsotg->free_hc_list)) {
2783 dev_dbg(hsotg->dev, "No free channel to assign\n");
2787 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
2790 /* Remove host channel from free list */
2791 list_del_init(&chan->hc_list_entry);
2793 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
2796 qtd->in_process = 1;
2799 * Use usb_pipedevice to determine device address. This address is
2800 * 0 before the SET_ADDRESS command and the correct address afterward.
2802 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
2803 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
2804 chan->speed = qh->dev_speed;
2805 chan->max_packet = dwc2_max_packet(qh->maxp);
2807 chan->xfer_started = 0;
2808 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
2809 chan->error_state = (qtd->error_count > 0);
2810 chan->halt_on_queue = 0;
2811 chan->halt_pending = 0;
2815 * The following values may be modified in the transfer type section
2816 * below. The xfer_len value may be reduced when the transfer is
2817 * started to accommodate the max widths of the XferSize and PktCnt
2818 * fields in the HCTSIZn register.
2821 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
2825 chan->do_ping = qh->ping_state;
2827 chan->data_pid_start = qh->data_toggle;
2828 chan->multi_count = 1;
2830 if (urb->actual_length > urb->length &&
2831 !dwc2_hcd_is_pipe_in(&urb->pipe_info))
2832 urb->actual_length = urb->length;
2834 if (hsotg->params.host_dma)
2835 chan->xfer_dma = urb->dma + urb->actual_length;
2837 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
2839 chan->xfer_len = urb->length - urb->actual_length;
2840 chan->xfer_count = 0;
2842 /* Set the split attributes if required */
2844 dwc2_hc_init_split(hsotg, chan, qtd, urb);
2848 /* Set the transfer attributes */
2849 dwc2_hc_init_xfer(hsotg, chan, qtd);
2851 /* For non-dword aligned buffers */
2852 if (hsotg->params.host_dma && qh->do_split &&
2853 chan->ep_is_in && (chan->xfer_dma & 0x3)) {
2854 dev_vdbg(hsotg->dev, "Non-aligned buffer\n");
2855 if (dwc2_alloc_split_dma_aligned_buf(hsotg, qh, chan)) {
2857 "Failed to allocate memory to handle non-aligned buffer\n");
2858 /* Add channel back to free list */
2859 chan->align_buf = 0;
2860 chan->multi_count = 0;
2861 list_add_tail(&chan->hc_list_entry,
2862 &hsotg->free_hc_list);
2863 qtd->in_process = 0;
2869 * We assume that DMA is always aligned in non-split
2870 * case or split out case. Warn if not.
2872 WARN_ON_ONCE(hsotg->params.host_dma &&
2873 (chan->xfer_dma & 0x3));
2874 chan->align_buf = 0;
2877 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
2878 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
2880 * This value may be modified when the transfer is started
2881 * to reflect the actual transfer length
2883 chan->multi_count = dwc2_hb_mult(qh->maxp);
2885 if (hsotg->params.dma_desc_enable) {
2886 chan->desc_list_addr = qh->desc_list_dma;
2887 chan->desc_list_sz = qh->desc_list_sz;
2890 dwc2_hc_init(hsotg, chan);
2897 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
2898 * schedule and assigns them to available host channels. Called from the HCD
2899 * interrupt handler functions.
2901 * @hsotg: The HCD state structure
2903 * Return: The types of new transactions that were assigned to host channels
2905 enum dwc2_transaction_type dwc2_hcd_select_transactions(
2906 struct dwc2_hsotg *hsotg)
2908 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
2909 struct list_head *qh_ptr;
2913 #ifdef DWC2_DEBUG_SOF
2914 dev_vdbg(hsotg->dev, " Select Transactions\n");
2917 /* Process entries in the periodic ready list */
2918 qh_ptr = hsotg->periodic_sched_ready.next;
2919 while (qh_ptr != &hsotg->periodic_sched_ready) {
2920 if (list_empty(&hsotg->free_hc_list))
2922 if (hsotg->params.uframe_sched) {
2923 if (hsotg->available_host_channels <= 1)
2925 hsotg->available_host_channels--;
2927 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2928 if (dwc2_assign_and_init_hc(hsotg, qh))
2932 * Move the QH from the periodic ready schedule to the
2933 * periodic assigned schedule
2935 qh_ptr = qh_ptr->next;
2936 list_move_tail(&qh->qh_list_entry,
2937 &hsotg->periodic_sched_assigned);
2938 ret_val = DWC2_TRANSACTION_PERIODIC;
2942 * Process entries in the inactive portion of the non-periodic
2943 * schedule. Some free host channels may not be used if they are
2944 * reserved for periodic transfers.
2946 num_channels = hsotg->params.host_channels;
2947 qh_ptr = hsotg->non_periodic_sched_inactive.next;
2948 while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
2949 if (!hsotg->params.uframe_sched &&
2950 hsotg->non_periodic_channels >= num_channels -
2951 hsotg->periodic_channels)
2953 if (list_empty(&hsotg->free_hc_list))
2955 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2956 if (hsotg->params.uframe_sched) {
2957 if (hsotg->available_host_channels < 1)
2959 hsotg->available_host_channels--;
2962 if (dwc2_assign_and_init_hc(hsotg, qh))
2966 * Move the QH from the non-periodic inactive schedule to the
2967 * non-periodic active schedule
2969 qh_ptr = qh_ptr->next;
2970 list_move_tail(&qh->qh_list_entry,
2971 &hsotg->non_periodic_sched_active);
2973 if (ret_val == DWC2_TRANSACTION_NONE)
2974 ret_val = DWC2_TRANSACTION_NON_PERIODIC;
2976 ret_val = DWC2_TRANSACTION_ALL;
2978 if (!hsotg->params.uframe_sched)
2979 hsotg->non_periodic_channels++;
2986 * dwc2_queue_transaction() - Attempts to queue a single transaction request for
2987 * a host channel associated with either a periodic or non-periodic transfer
2989 * @hsotg: The HCD state structure
2990 * @chan: Host channel descriptor associated with either a periodic or
2991 * non-periodic transfer
2992 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
2993 * for periodic transfers or the non-periodic Tx FIFO
2994 * for non-periodic transfers
2996 * Return: 1 if a request is queued and more requests may be needed to
2997 * complete the transfer, 0 if no more requests are required for this
2998 * transfer, -1 if there is insufficient space in the Tx FIFO
3000 * This function assumes that there is space available in the appropriate
3001 * request queue. For an OUT transfer or SETUP transaction in Slave mode,
3002 * it checks whether space is available in the appropriate Tx FIFO.
3004 * Must be called with interrupt disabled and spinlock held
3006 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
3007 struct dwc2_host_chan *chan,
3008 u16 fifo_dwords_avail)
3013 /* Put ourselves on the list to keep order straight */
3014 list_move_tail(&chan->split_order_list_entry,
3015 &hsotg->split_order);
3017 if (hsotg->params.host_dma) {
3018 if (hsotg->params.dma_desc_enable) {
3019 if (!chan->xfer_started ||
3020 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
3021 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
3022 chan->qh->ping_state = 0;
3024 } else if (!chan->xfer_started) {
3025 dwc2_hc_start_transfer(hsotg, chan);
3026 chan->qh->ping_state = 0;
3028 } else if (chan->halt_pending) {
3029 /* Don't queue a request if the channel has been halted */
3030 } else if (chan->halt_on_queue) {
3031 dwc2_hc_halt(hsotg, chan, chan->halt_status);
3032 } else if (chan->do_ping) {
3033 if (!chan->xfer_started)
3034 dwc2_hc_start_transfer(hsotg, chan);
3035 } else if (!chan->ep_is_in ||
3036 chan->data_pid_start == DWC2_HC_PID_SETUP) {
3037 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
3038 if (!chan->xfer_started) {
3039 dwc2_hc_start_transfer(hsotg, chan);
3042 retval = dwc2_hc_continue_transfer(hsotg, chan);
3048 if (!chan->xfer_started) {
3049 dwc2_hc_start_transfer(hsotg, chan);
3052 retval = dwc2_hc_continue_transfer(hsotg, chan);
3060 * Processes periodic channels for the next frame and queues transactions for
3061 * these channels to the DWC_otg controller. After queueing transactions, the
3062 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
3063 * to queue as Periodic Tx FIFO or request queue space becomes available.
3064 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
3066 * Must be called with interrupt disabled and spinlock held
3068 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
3070 struct list_head *qh_ptr;
3076 bool no_queue_space = false;
3077 bool no_fifo_space = false;
3080 /* If empty list then just adjust interrupt enables */
3081 if (list_empty(&hsotg->periodic_sched_assigned))
3085 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
3087 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
3088 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3089 TXSTS_QSPCAVAIL_SHIFT;
3090 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3091 TXSTS_FSPCAVAIL_SHIFT;
3094 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n",
3096 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n",
3100 qh_ptr = hsotg->periodic_sched_assigned.next;
3101 while (qh_ptr != &hsotg->periodic_sched_assigned) {
3102 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
3103 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3104 TXSTS_QSPCAVAIL_SHIFT;
3105 if (qspcavail == 0) {
3106 no_queue_space = true;
3110 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
3112 qh_ptr = qh_ptr->next;
3116 /* Make sure EP's TT buffer is clean before queueing qtds */
3117 if (qh->tt_buffer_dirty) {
3118 qh_ptr = qh_ptr->next;
3123 * Set a flag if we're queuing high-bandwidth in slave mode.
3124 * The flag prevents any halts to get into the request queue in
3125 * the middle of multiple high-bandwidth packets getting queued.
3127 if (!hsotg->params.host_dma &&
3128 qh->channel->multi_count > 1)
3129 hsotg->queuing_high_bandwidth = 1;
3131 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3132 TXSTS_FSPCAVAIL_SHIFT;
3133 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
3135 no_fifo_space = true;
3140 * In Slave mode, stay on the current transfer until there is
3141 * nothing more to do or the high-bandwidth request count is
3142 * reached. In DMA mode, only need to queue one request. The
3143 * controller automatically handles multiple packets for
3144 * high-bandwidth transfers.
3146 if (hsotg->params.host_dma || status == 0 ||
3147 qh->channel->requests == qh->channel->multi_count) {
3148 qh_ptr = qh_ptr->next;
3150 * Move the QH from the periodic assigned schedule to
3151 * the periodic queued schedule
3153 list_move_tail(&qh->qh_list_entry,
3154 &hsotg->periodic_sched_queued);
3156 /* done queuing high bandwidth */
3157 hsotg->queuing_high_bandwidth = 0;
3162 if (no_queue_space || no_fifo_space ||
3163 (!hsotg->params.host_dma &&
3164 !list_empty(&hsotg->periodic_sched_assigned))) {
3166 * May need to queue more transactions as the request
3167 * queue or Tx FIFO empties. Enable the periodic Tx
3168 * FIFO empty interrupt. (Always use the half-empty
3169 * level to ensure that new requests are loaded as
3170 * soon as possible.)
3172 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3173 if (!(gintmsk & GINTSTS_PTXFEMP)) {
3174 gintmsk |= GINTSTS_PTXFEMP;
3175 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3179 * Disable the Tx FIFO empty interrupt since there are
3180 * no more transactions that need to be queued right
3181 * now. This function is called from interrupt
3182 * handlers to queue more transactions as transfer
3185 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3186 if (gintmsk & GINTSTS_PTXFEMP) {
3187 gintmsk &= ~GINTSTS_PTXFEMP;
3188 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3194 * Processes active non-periodic channels and queues transactions for these
3195 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
3196 * FIFO Empty interrupt is enabled if there are more transactions to queue as
3197 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
3198 * FIFO Empty interrupt is disabled.
3200 * Must be called with interrupt disabled and spinlock held
3202 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
3204 struct list_head *orig_qh_ptr;
3211 int no_queue_space = 0;
3212 int no_fifo_space = 0;
3215 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
3217 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3218 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3219 TXSTS_QSPCAVAIL_SHIFT;
3220 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3221 TXSTS_FSPCAVAIL_SHIFT;
3222 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n",
3224 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n",
3228 * Keep track of the starting point. Skip over the start-of-list
3231 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
3232 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3233 orig_qh_ptr = hsotg->non_periodic_qh_ptr;
3236 * Process once through the active list or until no more space is
3237 * available in the request queue or the Tx FIFO
3240 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3241 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3242 TXSTS_QSPCAVAIL_SHIFT;
3243 if (!hsotg->params.host_dma && qspcavail == 0) {
3248 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
3253 /* Make sure EP's TT buffer is clean before queueing qtds */
3254 if (qh->tt_buffer_dirty)
3257 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3258 TXSTS_FSPCAVAIL_SHIFT;
3259 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
3263 } else if (status < 0) {
3268 /* Advance to next QH, skipping start-of-list entry */
3269 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3270 if (hsotg->non_periodic_qh_ptr ==
3271 &hsotg->non_periodic_sched_active)
3272 hsotg->non_periodic_qh_ptr =
3273 hsotg->non_periodic_qh_ptr->next;
3274 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
3276 if (!hsotg->params.host_dma) {
3277 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3278 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3279 TXSTS_QSPCAVAIL_SHIFT;
3280 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3281 TXSTS_FSPCAVAIL_SHIFT;
3282 dev_vdbg(hsotg->dev,
3283 " NP Tx Req Queue Space Avail (after queue): %d\n",
3285 dev_vdbg(hsotg->dev,
3286 " NP Tx FIFO Space Avail (after queue): %d\n",
3289 if (more_to_do || no_queue_space || no_fifo_space) {
3291 * May need to queue more transactions as the request
3292 * queue or Tx FIFO empties. Enable the non-periodic
3293 * Tx FIFO empty interrupt. (Always use the half-empty
3294 * level to ensure that new requests are loaded as
3295 * soon as possible.)
3297 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3298 gintmsk |= GINTSTS_NPTXFEMP;
3299 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3302 * Disable the Tx FIFO empty interrupt since there are
3303 * no more transactions that need to be queued right
3304 * now. This function is called from interrupt
3305 * handlers to queue more transactions as transfer
3308 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3309 gintmsk &= ~GINTSTS_NPTXFEMP;
3310 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3316 * dwc2_hcd_queue_transactions() - Processes the currently active host channels
3317 * and queues transactions for these channels to the DWC_otg controller. Called
3318 * from the HCD interrupt handler functions.
3320 * @hsotg: The HCD state structure
3321 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
3324 * Must be called with interrupt disabled and spinlock held
3326 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
3327 enum dwc2_transaction_type tr_type)
3329 #ifdef DWC2_DEBUG_SOF
3330 dev_vdbg(hsotg->dev, "Queue Transactions\n");
3332 /* Process host channels associated with periodic transfers */
3333 if (tr_type == DWC2_TRANSACTION_PERIODIC ||
3334 tr_type == DWC2_TRANSACTION_ALL)
3335 dwc2_process_periodic_channels(hsotg);
3337 /* Process host channels associated with non-periodic transfers */
3338 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
3339 tr_type == DWC2_TRANSACTION_ALL) {
3340 if (!list_empty(&hsotg->non_periodic_sched_active)) {
3341 dwc2_process_non_periodic_channels(hsotg);
3344 * Ensure NP Tx FIFO empty interrupt is disabled when
3345 * there are no non-periodic transfers to process
3347 u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3349 gintmsk &= ~GINTSTS_NPTXFEMP;
3350 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3355 static void dwc2_conn_id_status_change(struct work_struct *work)
3357 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
3361 unsigned long flags;
3363 dev_dbg(hsotg->dev, "%s()\n", __func__);
3365 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
3366 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
3367 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
3368 !!(gotgctl & GOTGCTL_CONID_B));
3370 /* B-Device connector (Device Mode) */
3371 if (gotgctl & GOTGCTL_CONID_B) {
3372 dwc2_vbus_supply_exit(hsotg);
3373 /* Wait for switch to device mode */
3374 dev_dbg(hsotg->dev, "connId B\n");
3375 if (hsotg->bus_suspended) {
3376 dev_info(hsotg->dev,
3377 "Do port resume before switching to device mode\n");
3378 dwc2_port_resume(hsotg);
3380 while (!dwc2_is_device_mode(hsotg)) {
3381 dev_info(hsotg->dev,
3382 "Waiting for Peripheral Mode, Mode=%s\n",
3383 dwc2_is_host_mode(hsotg) ? "Host" :
3387 * Sometimes the initial GOTGCTRL read is wrong, so
3388 * check it again and jump to host mode if that was
3391 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
3392 if (!(gotgctl & GOTGCTL_CONID_B))
3399 "Connection id status change timed out\n");
3400 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3401 dwc2_core_init(hsotg, false);
3402 dwc2_enable_global_interrupts(hsotg);
3403 spin_lock_irqsave(&hsotg->lock, flags);
3404 dwc2_hsotg_core_init_disconnected(hsotg, false);
3405 spin_unlock_irqrestore(&hsotg->lock, flags);
3406 /* Enable ACG feature in device mode,if supported */
3407 dwc2_enable_acg(hsotg);
3408 dwc2_hsotg_core_connect(hsotg);
3411 /* A-Device connector (Host Mode) */
3412 dev_dbg(hsotg->dev, "connId A\n");
3413 while (!dwc2_is_host_mode(hsotg)) {
3414 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
3415 dwc2_is_host_mode(hsotg) ?
3416 "Host" : "Peripheral");
3423 "Connection id status change timed out\n");
3425 spin_lock_irqsave(&hsotg->lock, flags);
3426 dwc2_hsotg_disconnect(hsotg);
3427 spin_unlock_irqrestore(&hsotg->lock, flags);
3429 hsotg->op_state = OTG_STATE_A_HOST;
3430 /* Initialize the Core for Host mode */
3431 dwc2_core_init(hsotg, false);
3432 dwc2_enable_global_interrupts(hsotg);
3433 dwc2_hcd_start(hsotg);
3437 static void dwc2_wakeup_detected(struct timer_list *t)
3439 struct dwc2_hsotg *hsotg = from_timer(hsotg, t, wkp_timer);
3442 dev_dbg(hsotg->dev, "%s()\n", __func__);
3445 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
3446 * so that OPT tests pass with all PHYs.)
3448 hprt0 = dwc2_read_hprt0(hsotg);
3449 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
3450 hprt0 &= ~HPRT0_RES;
3451 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3452 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
3453 dwc2_readl(hsotg->regs + HPRT0));
3455 dwc2_hcd_rem_wakeup(hsotg);
3456 hsotg->bus_suspended = false;
3458 /* Change to L0 state */
3459 hsotg->lx_state = DWC2_L0;
3462 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
3464 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
3466 return hcd->self.b_hnp_enable;
3469 /* Must NOT be called with interrupt disabled or spinlock held */
3470 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
3472 unsigned long flags;
3477 dev_dbg(hsotg->dev, "%s()\n", __func__);
3479 spin_lock_irqsave(&hsotg->lock, flags);
3481 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
3482 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
3483 gotgctl |= GOTGCTL_HSTSETHNPEN;
3484 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
3485 hsotg->op_state = OTG_STATE_A_SUSPEND;
3488 hprt0 = dwc2_read_hprt0(hsotg);
3489 hprt0 |= HPRT0_SUSP;
3490 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3492 hsotg->bus_suspended = true;
3495 * If power_down is supported, Phy clock will be suspended
3496 * after registers are backuped.
3498 if (!hsotg->params.power_down) {
3499 /* Suspend the Phy Clock */
3500 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3501 pcgctl |= PCGCTL_STOPPCLK;
3502 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3506 /* For HNP the bus must be suspended for at least 200ms */
3507 if (dwc2_host_is_b_hnp_enabled(hsotg)) {
3508 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3509 pcgctl &= ~PCGCTL_STOPPCLK;
3510 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3512 spin_unlock_irqrestore(&hsotg->lock, flags);
3516 spin_unlock_irqrestore(&hsotg->lock, flags);
3520 /* Must NOT be called with interrupt disabled or spinlock held */
3521 static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
3523 unsigned long flags;
3527 spin_lock_irqsave(&hsotg->lock, flags);
3530 * If power_down is supported, Phy clock is already resumed
3531 * after registers restore.
3533 if (!hsotg->params.power_down) {
3534 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3535 pcgctl &= ~PCGCTL_STOPPCLK;
3536 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3537 spin_unlock_irqrestore(&hsotg->lock, flags);
3539 spin_lock_irqsave(&hsotg->lock, flags);
3542 hprt0 = dwc2_read_hprt0(hsotg);
3544 hprt0 &= ~HPRT0_SUSP;
3545 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3546 spin_unlock_irqrestore(&hsotg->lock, flags);
3548 msleep(USB_RESUME_TIMEOUT);
3550 spin_lock_irqsave(&hsotg->lock, flags);
3551 hprt0 = dwc2_read_hprt0(hsotg);
3552 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP);
3553 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3554 hsotg->bus_suspended = false;
3555 spin_unlock_irqrestore(&hsotg->lock, flags);
3558 /* Handles hub class-specific requests */
3559 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3560 u16 wvalue, u16 windex, char *buf, u16 wlength)
3562 struct usb_hub_descriptor *hub_desc;
3570 case ClearHubFeature:
3571 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
3574 case C_HUB_LOCAL_POWER:
3575 case C_HUB_OVER_CURRENT:
3576 /* Nothing required here */
3582 "ClearHubFeature request %1xh unknown\n",
3587 case ClearPortFeature:
3588 if (wvalue != USB_PORT_FEAT_L1)
3589 if (!windex || windex > 1)
3592 case USB_PORT_FEAT_ENABLE:
3594 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
3595 hprt0 = dwc2_read_hprt0(hsotg);
3597 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3600 case USB_PORT_FEAT_SUSPEND:
3602 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
3604 if (hsotg->bus_suspended) {
3605 if (hsotg->hibernated)
3606 dwc2_exit_hibernation(hsotg, 0, 0, 1);
3608 dwc2_port_resume(hsotg);
3612 case USB_PORT_FEAT_POWER:
3614 "ClearPortFeature USB_PORT_FEAT_POWER\n");
3615 hprt0 = dwc2_read_hprt0(hsotg);
3616 hprt0 &= ~HPRT0_PWR;
3617 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3620 case USB_PORT_FEAT_INDICATOR:
3622 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
3623 /* Port indicator not supported */
3626 case USB_PORT_FEAT_C_CONNECTION:
3628 * Clears driver's internal Connect Status Change flag
3631 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
3632 hsotg->flags.b.port_connect_status_change = 0;
3635 case USB_PORT_FEAT_C_RESET:
3636 /* Clears driver's internal Port Reset Change flag */
3638 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
3639 hsotg->flags.b.port_reset_change = 0;
3642 case USB_PORT_FEAT_C_ENABLE:
3644 * Clears the driver's internal Port Enable/Disable
3648 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
3649 hsotg->flags.b.port_enable_change = 0;
3652 case USB_PORT_FEAT_C_SUSPEND:
3654 * Clears the driver's internal Port Suspend Change
3655 * flag, which is set when resume signaling on the host
3659 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
3660 hsotg->flags.b.port_suspend_change = 0;
3663 case USB_PORT_FEAT_C_PORT_L1:
3665 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
3666 hsotg->flags.b.port_l1_change = 0;
3669 case USB_PORT_FEAT_C_OVER_CURRENT:
3671 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
3672 hsotg->flags.b.port_over_current_change = 0;
3678 "ClearPortFeature request %1xh unknown or unsupported\n",
3683 case GetHubDescriptor:
3684 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
3685 hub_desc = (struct usb_hub_descriptor *)buf;
3686 hub_desc->bDescLength = 9;
3687 hub_desc->bDescriptorType = USB_DT_HUB;
3688 hub_desc->bNbrPorts = 1;
3689 hub_desc->wHubCharacteristics =
3690 cpu_to_le16(HUB_CHAR_COMMON_LPSM |
3691 HUB_CHAR_INDV_PORT_OCPM);
3692 hub_desc->bPwrOn2PwrGood = 1;
3693 hub_desc->bHubContrCurrent = 0;
3694 hub_desc->u.hs.DeviceRemovable[0] = 0;
3695 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
3699 dev_dbg(hsotg->dev, "GetHubStatus\n");
3704 dev_vdbg(hsotg->dev,
3705 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
3707 if (!windex || windex > 1)
3711 if (hsotg->flags.b.port_connect_status_change)
3712 port_status |= USB_PORT_STAT_C_CONNECTION << 16;
3713 if (hsotg->flags.b.port_enable_change)
3714 port_status |= USB_PORT_STAT_C_ENABLE << 16;
3715 if (hsotg->flags.b.port_suspend_change)
3716 port_status |= USB_PORT_STAT_C_SUSPEND << 16;
3717 if (hsotg->flags.b.port_l1_change)
3718 port_status |= USB_PORT_STAT_C_L1 << 16;
3719 if (hsotg->flags.b.port_reset_change)
3720 port_status |= USB_PORT_STAT_C_RESET << 16;
3721 if (hsotg->flags.b.port_over_current_change) {
3722 dev_warn(hsotg->dev, "Overcurrent change detected\n");
3723 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
3726 if (!hsotg->flags.b.port_connect_status) {
3728 * The port is disconnected, which means the core is
3729 * either in device mode or it soon will be. Just
3730 * return 0's for the remainder of the port status
3731 * since the port register can't be read if the core
3732 * is in device mode.
3734 *(__le32 *)buf = cpu_to_le32(port_status);
3738 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
3739 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
3741 if (hprt0 & HPRT0_CONNSTS)
3742 port_status |= USB_PORT_STAT_CONNECTION;
3743 if (hprt0 & HPRT0_ENA)
3744 port_status |= USB_PORT_STAT_ENABLE;
3745 if (hprt0 & HPRT0_SUSP)
3746 port_status |= USB_PORT_STAT_SUSPEND;
3747 if (hprt0 & HPRT0_OVRCURRACT)
3748 port_status |= USB_PORT_STAT_OVERCURRENT;
3749 if (hprt0 & HPRT0_RST)
3750 port_status |= USB_PORT_STAT_RESET;
3751 if (hprt0 & HPRT0_PWR)
3752 port_status |= USB_PORT_STAT_POWER;
3754 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
3755 if (speed == HPRT0_SPD_HIGH_SPEED)
3756 port_status |= USB_PORT_STAT_HIGH_SPEED;
3757 else if (speed == HPRT0_SPD_LOW_SPEED)
3758 port_status |= USB_PORT_STAT_LOW_SPEED;
3760 if (hprt0 & HPRT0_TSTCTL_MASK)
3761 port_status |= USB_PORT_STAT_TEST;
3762 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
3764 if (hsotg->params.dma_desc_fs_enable) {
3766 * Enable descriptor DMA only if a full speed
3767 * device is connected.
3769 if (hsotg->new_connection &&
3771 (USB_PORT_STAT_CONNECTION |
3772 USB_PORT_STAT_HIGH_SPEED |
3773 USB_PORT_STAT_LOW_SPEED)) ==
3774 USB_PORT_STAT_CONNECTION)) {
3777 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n");
3778 hsotg->params.dma_desc_enable = true;
3779 hcfg = dwc2_readl(hsotg->regs + HCFG);
3780 hcfg |= HCFG_DESCDMA;
3781 dwc2_writel(hcfg, hsotg->regs + HCFG);
3782 hsotg->new_connection = false;
3786 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
3787 *(__le32 *)buf = cpu_to_le32(port_status);
3791 dev_dbg(hsotg->dev, "SetHubFeature\n");
3792 /* No HUB features supported */
3795 case SetPortFeature:
3796 dev_dbg(hsotg->dev, "SetPortFeature\n");
3797 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
3800 if (!hsotg->flags.b.port_connect_status) {
3802 * The port is disconnected, which means the core is
3803 * either in device mode or it soon will be. Just
3804 * return without doing anything since the port
3805 * register can't be written if the core is in device
3812 case USB_PORT_FEAT_SUSPEND:
3814 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
3815 if (windex != hsotg->otg_port)
3817 if (hsotg->params.power_down == 2)
3818 dwc2_enter_hibernation(hsotg, 1);
3820 dwc2_port_suspend(hsotg, windex);
3823 case USB_PORT_FEAT_POWER:
3825 "SetPortFeature - USB_PORT_FEAT_POWER\n");
3826 hprt0 = dwc2_read_hprt0(hsotg);
3828 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3831 case USB_PORT_FEAT_RESET:
3832 if (hsotg->params.power_down == 2 &&
3834 dwc2_exit_hibernation(hsotg, 0, 1, 1);
3835 hprt0 = dwc2_read_hprt0(hsotg);
3837 "SetPortFeature - USB_PORT_FEAT_RESET\n");
3838 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3839 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
3840 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3841 /* ??? Original driver does this */
3842 dwc2_writel(0, hsotg->regs + PCGCTL);
3844 hprt0 = dwc2_read_hprt0(hsotg);
3845 /* Clear suspend bit if resetting from suspend state */
3846 hprt0 &= ~HPRT0_SUSP;
3849 * When B-Host the Port reset bit is set in the Start
3850 * HCD Callback function, so that the reset is started
3851 * within 1ms of the HNP success interrupt
3853 if (!dwc2_hcd_is_b_host(hsotg)) {
3854 hprt0 |= HPRT0_PWR | HPRT0_RST;
3856 "In host mode, hprt0=%08x\n", hprt0);
3857 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3860 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
3862 hprt0 &= ~HPRT0_RST;
3863 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3864 hsotg->lx_state = DWC2_L0; /* Now back to On state */
3867 case USB_PORT_FEAT_INDICATOR:
3869 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
3873 case USB_PORT_FEAT_TEST:
3874 hprt0 = dwc2_read_hprt0(hsotg);
3876 "SetPortFeature - USB_PORT_FEAT_TEST\n");
3877 hprt0 &= ~HPRT0_TSTCTL_MASK;
3878 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT;
3879 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3885 "SetPortFeature %1xh unknown or unsupported\n",
3895 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
3896 typereq, windex, wvalue);
3903 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
3910 retval = (hsotg->flags.b.port_connect_status_change ||
3911 hsotg->flags.b.port_reset_change ||
3912 hsotg->flags.b.port_enable_change ||
3913 hsotg->flags.b.port_suspend_change ||
3914 hsotg->flags.b.port_over_current_change);
3918 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
3919 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n",
3920 hsotg->flags.b.port_connect_status_change);
3921 dev_dbg(hsotg->dev, " port_reset_change: %d\n",
3922 hsotg->flags.b.port_reset_change);
3923 dev_dbg(hsotg->dev, " port_enable_change: %d\n",
3924 hsotg->flags.b.port_enable_change);
3925 dev_dbg(hsotg->dev, " port_suspend_change: %d\n",
3926 hsotg->flags.b.port_suspend_change);
3927 dev_dbg(hsotg->dev, " port_over_current_change: %d\n",
3928 hsotg->flags.b.port_over_current_change);
3934 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
3936 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM);
3938 #ifdef DWC2_DEBUG_SOF
3939 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
3940 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
3942 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3945 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us)
3947 u32 hprt = dwc2_readl(hsotg->regs + HPRT0);
3948 u32 hfir = dwc2_readl(hsotg->regs + HFIR);
3949 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM);
3950 unsigned int us_per_frame;
3951 unsigned int frame_number;
3952 unsigned int remaining;
3953 unsigned int interval;
3954 unsigned int phy_clks;
3956 /* High speed has 125 us per (micro) frame; others are 1 ms per */
3957 us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125;
3959 /* Extract fields */
3960 frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3961 remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT;
3962 interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT;
3965 * Number of phy clocks since the last tick of the frame number after
3968 phy_clks = (interval - remaining) +
3969 DIV_ROUND_UP(interval * us, us_per_frame);
3971 return dwc2_frame_num_inc(frame_number, phy_clks / interval);
3974 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
3976 return hsotg->op_state == OTG_STATE_B_HOST;
3979 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
3983 struct dwc2_hcd_urb *urb;
3984 u32 size = sizeof(*urb) + iso_desc_count *
3985 sizeof(struct dwc2_hcd_iso_packet_desc);
3987 urb = kzalloc(size, mem_flags);
3989 urb->packet_count = iso_desc_count;
3993 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
3994 struct dwc2_hcd_urb *urb, u8 dev_addr,
3995 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)
3998 ep_type == USB_ENDPOINT_XFER_BULK ||
3999 ep_type == USB_ENDPOINT_XFER_CONTROL)
4000 dev_vdbg(hsotg->dev,
4001 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
4002 dev_addr, ep_num, ep_dir, ep_type, mps);
4003 urb->pipe_info.dev_addr = dev_addr;
4004 urb->pipe_info.ep_num = ep_num;
4005 urb->pipe_info.pipe_type = ep_type;
4006 urb->pipe_info.pipe_dir = ep_dir;
4007 urb->pipe_info.mps = mps;
4011 * NOTE: This function will be removed once the peripheral controller code
4012 * is integrated and the driver is stable
4014 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
4017 struct dwc2_host_chan *chan;
4018 struct dwc2_hcd_urb *urb;
4019 struct dwc2_qtd *qtd;
4025 num_channels = hsotg->params.host_channels;
4026 dev_dbg(hsotg->dev, "\n");
4028 "************************************************************\n");
4029 dev_dbg(hsotg->dev, "HCD State:\n");
4030 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels);
4032 for (i = 0; i < num_channels; i++) {
4033 chan = hsotg->hc_ptr_array[i];
4034 dev_dbg(hsotg->dev, " Channel %d:\n", i);
4036 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
4037 chan->dev_addr, chan->ep_num, chan->ep_is_in);
4038 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed);
4039 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
4040 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
4041 dev_dbg(hsotg->dev, " data_pid_start: %d\n",
4042 chan->data_pid_start);
4043 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count);
4044 dev_dbg(hsotg->dev, " xfer_started: %d\n",
4045 chan->xfer_started);
4046 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
4047 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
4048 (unsigned long)chan->xfer_dma);
4049 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
4050 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count);
4051 dev_dbg(hsotg->dev, " halt_on_queue: %d\n",
4052 chan->halt_on_queue);
4053 dev_dbg(hsotg->dev, " halt_pending: %d\n",
4054 chan->halt_pending);
4055 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
4056 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split);
4057 dev_dbg(hsotg->dev, " complete_split: %d\n",
4058 chan->complete_split);
4059 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr);
4060 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port);
4061 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos);
4062 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests);
4063 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
4065 if (chan->xfer_started) {
4066 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
4068 hfnum = dwc2_readl(hsotg->regs + HFNUM);
4069 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
4070 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i));
4071 hcint = dwc2_readl(hsotg->regs + HCINT(i));
4072 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i));
4073 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum);
4074 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar);
4075 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz);
4076 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint);
4077 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk);
4080 if (!(chan->xfer_started && chan->qh))
4083 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
4084 if (!qtd->in_process)
4087 dev_dbg(hsotg->dev, " URB Info:\n");
4088 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n",
4092 " Dev: %d, EP: %d %s\n",
4093 dwc2_hcd_get_dev_addr(&urb->pipe_info),
4094 dwc2_hcd_get_ep_num(&urb->pipe_info),
4095 dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
4098 " Max packet size: %d\n",
4099 dwc2_hcd_get_mps(&urb->pipe_info));
4101 " transfer_buffer: %p\n",
4104 " transfer_dma: %08lx\n",
4105 (unsigned long)urb->dma);
4107 " transfer_buffer_length: %d\n",
4109 dev_dbg(hsotg->dev, " actual_length: %d\n",
4110 urb->actual_length);
4115 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n",
4116 hsotg->non_periodic_channels);
4117 dev_dbg(hsotg->dev, " periodic_channels: %d\n",
4118 hsotg->periodic_channels);
4119 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
4120 np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
4121 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n",
4122 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
4123 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n",
4124 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
4125 p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
4126 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
4127 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
4128 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
4129 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
4130 dwc2_dump_global_registers(hsotg);
4131 dwc2_dump_host_registers(hsotg);
4133 "************************************************************\n");
4134 dev_dbg(hsotg->dev, "\n");
4138 struct wrapper_priv_data {
4139 struct dwc2_hsotg *hsotg;
4142 /* Gets the dwc2_hsotg from a usb_hcd */
4143 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
4145 struct wrapper_priv_data *p;
4147 p = (struct wrapper_priv_data *)&hcd->hcd_priv;
4152 * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context
4154 * This will get the dwc2_tt structure (and ttport) associated with the given
4155 * context (which is really just a struct urb pointer).
4157 * The first time this is called for a given TT we allocate memory for our
4158 * structure. When everyone is done and has called dwc2_host_put_tt_info()
4159 * then the refcount for the structure will go to 0 and we'll free it.
4161 * @hsotg: The HCD state structure for the DWC OTG controller.
4162 * @context: The priv pointer from a struct dwc2_hcd_urb.
4163 * @mem_flags: Flags for allocating memory.
4164 * @ttport: We'll return this device's port number here. That's used to
4165 * reference into the bitmap if we're on a multi_tt hub.
4167 * Return: a pointer to a struct dwc2_tt. Don't forget to call
4168 * dwc2_host_put_tt_info()! Returns NULL upon memory alloc failure.
4171 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context,
4172 gfp_t mem_flags, int *ttport)
4174 struct urb *urb = context;
4175 struct dwc2_tt *dwc_tt = NULL;
4178 *ttport = urb->dev->ttport;
4180 dwc_tt = urb->dev->tt->hcpriv;
4185 * For single_tt we need one schedule. For multi_tt
4186 * we need one per port.
4188 bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP *
4189 sizeof(dwc_tt->periodic_bitmaps[0]);
4190 if (urb->dev->tt->multi)
4191 bitmap_size *= urb->dev->tt->hub->maxchild;
4193 dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size,
4198 dwc_tt->usb_tt = urb->dev->tt;
4199 dwc_tt->usb_tt->hcpriv = dwc_tt;
4209 * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info()
4211 * Frees resources allocated by dwc2_host_get_tt_info() if all current holders
4212 * of the structure are done.
4214 * It's OK to call this with NULL.
4216 * @hsotg: The HCD state structure for the DWC OTG controller.
4217 * @dwc_tt: The pointer returned by dwc2_host_get_tt_info.
4219 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt)
4221 /* Model kfree and make put of NULL a no-op */
4225 WARN_ON(dwc_tt->refcount < 1);
4228 if (!dwc_tt->refcount) {
4229 dwc_tt->usb_tt->hcpriv = NULL;
4234 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
4236 struct urb *urb = context;
4238 return urb->dev->speed;
4241 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4244 struct usb_bus *bus = hcd_to_bus(hcd);
4247 bus->bandwidth_allocated += bw / urb->interval;
4248 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4249 bus->bandwidth_isoc_reqs++;
4251 bus->bandwidth_int_reqs++;
4254 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4257 struct usb_bus *bus = hcd_to_bus(hcd);
4260 bus->bandwidth_allocated -= bw / urb->interval;
4261 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4262 bus->bandwidth_isoc_reqs--;
4264 bus->bandwidth_int_reqs--;
4268 * Sets the final status of an URB and returns it to the upper layer. Any
4269 * required cleanup of the URB is performed.
4271 * Must be called with interrupt disabled and spinlock held
4273 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
4280 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
4285 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
4289 urb = qtd->urb->priv;
4291 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
4295 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
4298 dev_vdbg(hsotg->dev,
4299 "%s: urb %p device %d ep %d-%s status %d actual %d\n",
4300 __func__, urb, usb_pipedevice(urb->pipe),
4301 usb_pipeendpoint(urb->pipe),
4302 usb_pipein(urb->pipe) ? "IN" : "OUT", status,
4303 urb->actual_length);
4305 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4306 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
4307 for (i = 0; i < urb->number_of_packets; ++i) {
4308 urb->iso_frame_desc[i].actual_length =
4309 dwc2_hcd_urb_get_iso_desc_actual_length(
4311 urb->iso_frame_desc[i].status =
4312 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
4316 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
4317 for (i = 0; i < urb->number_of_packets; i++)
4318 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
4319 i, urb->iso_frame_desc[i].status);
4322 urb->status = status;
4324 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
4325 urb->actual_length < urb->transfer_buffer_length)
4326 urb->status = -EREMOTEIO;
4329 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4330 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4331 struct usb_host_endpoint *ep = urb->ep;
4334 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
4335 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4339 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
4344 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
4348 * Work queue function for starting the HCD when A-Cable is connected
4350 static void dwc2_hcd_start_func(struct work_struct *work)
4352 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4355 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
4356 dwc2_host_start(hsotg);
4360 * Reset work queue function
4362 static void dwc2_hcd_reset_func(struct work_struct *work)
4364 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4366 unsigned long flags;
4369 dev_dbg(hsotg->dev, "USB RESET function called\n");
4371 spin_lock_irqsave(&hsotg->lock, flags);
4373 hprt0 = dwc2_read_hprt0(hsotg);
4374 hprt0 &= ~HPRT0_RST;
4375 dwc2_writel(hprt0, hsotg->regs + HPRT0);
4376 hsotg->flags.b.port_reset_change = 1;
4378 spin_unlock_irqrestore(&hsotg->lock, flags);
4382 * =========================================================================
4383 * Linux HC Driver Functions
4384 * =========================================================================
4388 * Initializes the DWC_otg controller and its root hub and prepares it for host
4389 * mode operation. Activates the root port. Returns 0 on success and a negative
4390 * error code on failure.
4392 static int _dwc2_hcd_start(struct usb_hcd *hcd)
4394 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4395 struct usb_bus *bus = hcd_to_bus(hcd);
4396 unsigned long flags;
4398 dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
4400 spin_lock_irqsave(&hsotg->lock, flags);
4401 hsotg->lx_state = DWC2_L0;
4402 hcd->state = HC_STATE_RUNNING;
4403 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4405 if (dwc2_is_device_mode(hsotg)) {
4406 spin_unlock_irqrestore(&hsotg->lock, flags);
4407 return 0; /* why 0 ?? */
4410 dwc2_hcd_reinit(hsotg);
4412 /* Initialize and connect root hub if one is not already attached */
4413 if (bus->root_hub) {
4414 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
4415 /* Inform the HUB driver to resume */
4416 usb_hcd_resume_root_hub(hcd);
4419 spin_unlock_irqrestore(&hsotg->lock, flags);
4421 return dwc2_vbus_supply_init(hsotg);
4425 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
4428 static void _dwc2_hcd_stop(struct usb_hcd *hcd)
4430 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4431 unsigned long flags;
4433 /* Turn off all host-specific interrupts */
4434 dwc2_disable_host_interrupts(hsotg);
4436 /* Wait for interrupt processing to finish */
4437 synchronize_irq(hcd->irq);
4439 spin_lock_irqsave(&hsotg->lock, flags);
4440 /* Ensure hcd is disconnected */
4441 dwc2_hcd_disconnect(hsotg, true);
4442 dwc2_hcd_stop(hsotg);
4443 hsotg->lx_state = DWC2_L3;
4444 hcd->state = HC_STATE_HALT;
4445 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4446 spin_unlock_irqrestore(&hsotg->lock, flags);
4448 dwc2_vbus_supply_exit(hsotg);
4450 usleep_range(1000, 3000);
4453 static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
4455 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4456 unsigned long flags;
4460 spin_lock_irqsave(&hsotg->lock, flags);
4462 if (dwc2_is_device_mode(hsotg))
4465 if (hsotg->lx_state != DWC2_L0)
4468 if (!HCD_HW_ACCESSIBLE(hcd))
4471 if (hsotg->op_state == OTG_STATE_B_PERIPHERAL)
4474 if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL)
4475 goto skip_power_saving;
4478 * Drive USB suspend and disable port Power
4479 * if usb bus is not suspended.
4481 if (!hsotg->bus_suspended) {
4482 hprt0 = dwc2_read_hprt0(hsotg);
4483 hprt0 |= HPRT0_SUSP;
4484 hprt0 &= ~HPRT0_PWR;
4485 dwc2_writel(hprt0, hsotg->regs + HPRT0);
4486 dwc2_vbus_supply_exit(hsotg);
4489 /* Enter partial_power_down */
4490 ret = dwc2_enter_partial_power_down(hsotg);
4492 if (ret != -ENOTSUPP)
4494 "enter partial_power_down failed\n");
4495 goto skip_power_saving;
4498 /* Ask phy to be suspended */
4499 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4500 spin_unlock_irqrestore(&hsotg->lock, flags);
4501 usb_phy_set_suspend(hsotg->uphy, true);
4502 spin_lock_irqsave(&hsotg->lock, flags);
4505 /* After entering partial_power_down, hardware is no more accessible */
4506 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4509 hsotg->lx_state = DWC2_L2;
4511 spin_unlock_irqrestore(&hsotg->lock, flags);
4516 static int _dwc2_hcd_resume(struct usb_hcd *hcd)
4518 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4519 unsigned long flags;
4522 spin_lock_irqsave(&hsotg->lock, flags);
4524 if (dwc2_is_device_mode(hsotg))
4527 if (hsotg->lx_state != DWC2_L2)
4530 if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL) {
4531 hsotg->lx_state = DWC2_L0;
4536 * Set HW accessible bit before powering on the controller
4537 * since an interrupt may rise.
4539 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4542 * Enable power if not already done.
4543 * This must not be spinlocked since duration
4544 * of this call is unknown.
4546 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4547 spin_unlock_irqrestore(&hsotg->lock, flags);
4548 usb_phy_set_suspend(hsotg->uphy, false);
4549 spin_lock_irqsave(&hsotg->lock, flags);
4552 /* Exit partial_power_down */
4553 ret = dwc2_exit_partial_power_down(hsotg, true);
4554 if (ret && (ret != -ENOTSUPP))
4555 dev_err(hsotg->dev, "exit partial_power_down failed\n");
4557 hsotg->lx_state = DWC2_L0;
4559 spin_unlock_irqrestore(&hsotg->lock, flags);
4561 if (hsotg->bus_suspended) {
4562 spin_lock_irqsave(&hsotg->lock, flags);
4563 hsotg->flags.b.port_suspend_change = 1;
4564 spin_unlock_irqrestore(&hsotg->lock, flags);
4565 dwc2_port_resume(hsotg);
4567 dwc2_vbus_supply_init(hsotg);
4569 /* Wait for controller to correctly update D+/D- level */
4570 usleep_range(3000, 5000);
4573 * Clear Port Enable and Port Status changes.
4574 * Enable Port Power.
4576 dwc2_writel(HPRT0_PWR | HPRT0_CONNDET |
4577 HPRT0_ENACHG, hsotg->regs + HPRT0);
4578 /* Wait for controller to detect Port Connect */
4579 usleep_range(5000, 7000);
4584 spin_unlock_irqrestore(&hsotg->lock, flags);
4589 /* Returns the current frame number */
4590 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
4592 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4594 return dwc2_hcd_get_frame_number(hsotg);
4597 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
4600 #ifdef VERBOSE_DEBUG
4601 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4602 char *pipetype = NULL;
4605 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
4606 dev_vdbg(hsotg->dev, " Device address: %d\n",
4607 usb_pipedevice(urb->pipe));
4608 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n",
4609 usb_pipeendpoint(urb->pipe),
4610 usb_pipein(urb->pipe) ? "IN" : "OUT");
4612 switch (usb_pipetype(urb->pipe)) {
4614 pipetype = "CONTROL";
4619 case PIPE_INTERRUPT:
4620 pipetype = "INTERRUPT";
4622 case PIPE_ISOCHRONOUS:
4623 pipetype = "ISOCHRONOUS";
4627 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype,
4628 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
4631 switch (urb->dev->speed) {
4632 case USB_SPEED_HIGH:
4635 case USB_SPEED_FULL:
4646 dev_vdbg(hsotg->dev, " Speed: %s\n", speed);
4647 dev_vdbg(hsotg->dev, " Max packet size: %d\n",
4648 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
4649 dev_vdbg(hsotg->dev, " Data buffer length: %d\n",
4650 urb->transfer_buffer_length);
4651 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
4652 urb->transfer_buffer, (unsigned long)urb->transfer_dma);
4653 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
4654 urb->setup_packet, (unsigned long)urb->setup_dma);
4655 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval);
4657 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4660 for (i = 0; i < urb->number_of_packets; i++) {
4661 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i);
4662 dev_vdbg(hsotg->dev, " offset: %d, length %d\n",
4663 urb->iso_frame_desc[i].offset,
4664 urb->iso_frame_desc[i].length);
4671 * Starts processing a USB transfer request specified by a USB Request Block
4672 * (URB). mem_flags indicates the type of memory allocation to use while
4673 * processing this URB.
4675 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
4678 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4679 struct usb_host_endpoint *ep = urb->ep;
4680 struct dwc2_hcd_urb *dwc2_urb;
4683 int alloc_bandwidth = 0;
4687 unsigned long flags;
4689 bool qh_allocated = false;
4690 struct dwc2_qtd *qtd;
4693 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
4694 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
4700 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4701 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4702 spin_lock_irqsave(&hsotg->lock, flags);
4703 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
4704 alloc_bandwidth = 1;
4705 spin_unlock_irqrestore(&hsotg->lock, flags);
4708 switch (usb_pipetype(urb->pipe)) {
4710 ep_type = USB_ENDPOINT_XFER_CONTROL;
4712 case PIPE_ISOCHRONOUS:
4713 ep_type = USB_ENDPOINT_XFER_ISOC;
4716 ep_type = USB_ENDPOINT_XFER_BULK;
4718 case PIPE_INTERRUPT:
4719 ep_type = USB_ENDPOINT_XFER_INT;
4723 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
4728 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
4729 usb_pipeendpoint(urb->pipe), ep_type,
4730 usb_pipein(urb->pipe),
4731 usb_maxpacket(urb->dev, urb->pipe,
4732 !(usb_pipein(urb->pipe))));
4734 buf = urb->transfer_buffer;
4736 if (hcd->self.uses_dma) {
4737 if (!buf && (urb->transfer_dma & 3)) {
4739 "%s: unaligned transfer with no transfer_buffer",
4746 if (!(urb->transfer_flags & URB_NO_INTERRUPT))
4747 tflags |= URB_GIVEBACK_ASAP;
4748 if (urb->transfer_flags & URB_ZERO_PACKET)
4749 tflags |= URB_SEND_ZERO_PACKET;
4751 dwc2_urb->priv = urb;
4752 dwc2_urb->buf = buf;
4753 dwc2_urb->dma = urb->transfer_dma;
4754 dwc2_urb->length = urb->transfer_buffer_length;
4755 dwc2_urb->setup_packet = urb->setup_packet;
4756 dwc2_urb->setup_dma = urb->setup_dma;
4757 dwc2_urb->flags = tflags;
4758 dwc2_urb->interval = urb->interval;
4759 dwc2_urb->status = -EINPROGRESS;
4761 for (i = 0; i < urb->number_of_packets; ++i)
4762 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
4763 urb->iso_frame_desc[i].offset,
4764 urb->iso_frame_desc[i].length);
4766 urb->hcpriv = dwc2_urb;
4767 qh = (struct dwc2_qh *)ep->hcpriv;
4768 /* Create QH for the endpoint if it doesn't exist */
4770 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags);
4776 qh_allocated = true;
4779 qtd = kzalloc(sizeof(*qtd), mem_flags);
4785 spin_lock_irqsave(&hsotg->lock, flags);
4786 retval = usb_hcd_link_urb_to_ep(hcd, urb);
4790 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
4794 if (alloc_bandwidth) {
4795 dwc2_allocate_bus_bandwidth(hcd,
4796 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4800 spin_unlock_irqrestore(&hsotg->lock, flags);
4805 dwc2_urb->priv = NULL;
4806 usb_hcd_unlink_urb_from_ep(hcd, urb);
4807 if (qh_allocated && qh->channel && qh->channel->qh == qh)
4808 qh->channel->qh = NULL;
4810 spin_unlock_irqrestore(&hsotg->lock, flags);
4816 struct dwc2_qtd *qtd2, *qtd2_tmp;
4819 dwc2_hcd_qh_unlink(hsotg, qh);
4820 /* Free each QTD in the QH's QTD list */
4821 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list,
4823 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh);
4824 dwc2_hcd_qh_free(hsotg, qh);
4833 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
4835 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
4838 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4840 unsigned long flags;
4842 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
4843 dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
4845 spin_lock_irqsave(&hsotg->lock, flags);
4847 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
4852 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
4856 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
4858 usb_hcd_unlink_urb_from_ep(hcd, urb);
4863 /* Higher layer software sets URB status */
4864 spin_unlock(&hsotg->lock);
4865 usb_hcd_giveback_urb(hcd, urb, status);
4866 spin_lock(&hsotg->lock);
4868 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
4869 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status);
4871 spin_unlock_irqrestore(&hsotg->lock, flags);
4877 * Frees resources in the DWC_otg controller related to a given endpoint. Also
4878 * clears state in the HCD related to the endpoint. Any URBs for the endpoint
4879 * must already be dequeued.
4881 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
4882 struct usb_host_endpoint *ep)
4884 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4887 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
4888 ep->desc.bEndpointAddress, ep->hcpriv);
4889 dwc2_hcd_endpoint_disable(hsotg, ep, 250);
4893 * Resets endpoint specific parameter values, in current version used to reset
4894 * the data toggle (as a WA). This function can be called from usb_clear_halt
4897 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
4898 struct usb_host_endpoint *ep)
4900 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4901 unsigned long flags;
4904 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
4905 ep->desc.bEndpointAddress);
4907 spin_lock_irqsave(&hsotg->lock, flags);
4908 dwc2_hcd_endpoint_reset(hsotg, ep);
4909 spin_unlock_irqrestore(&hsotg->lock, flags);
4913 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
4914 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
4917 * This function is called by the USB core when an interrupt occurs
4919 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
4921 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4923 return dwc2_handle_hcd_intr(hsotg);
4927 * Creates Status Change bitmap for the root hub and root port. The bitmap is
4928 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
4929 * is the status change indicator for the single root port. Returns 1 if either
4930 * change indicator is 1, otherwise returns 0.
4932 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
4934 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4936 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
4940 /* Handles hub class-specific requests */
4941 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
4942 u16 windex, char *buf, u16 wlength)
4944 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
4945 wvalue, windex, buf, wlength);
4949 /* Handles hub TT buffer clear completions */
4950 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
4951 struct usb_host_endpoint *ep)
4953 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4955 unsigned long flags;
4961 spin_lock_irqsave(&hsotg->lock, flags);
4962 qh->tt_buffer_dirty = 0;
4964 if (hsotg->flags.b.port_connect_status)
4965 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
4967 spin_unlock_irqrestore(&hsotg->lock, flags);
4971 * HPRT0_SPD_HIGH_SPEED: high speed
4972 * HPRT0_SPD_FULL_SPEED: full speed
4974 static void dwc2_change_bus_speed(struct usb_hcd *hcd, int speed)
4976 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4978 if (hsotg->params.speed == speed)
4981 hsotg->params.speed = speed;
4982 queue_work(hsotg->wq_otg, &hsotg->wf_otg);
4985 static void dwc2_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
4987 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4989 if (!hsotg->params.change_speed_quirk)
4993 * On removal, set speed to default high-speed.
4995 if (udev->parent && udev->parent->speed > USB_SPEED_UNKNOWN &&
4996 udev->parent->speed < USB_SPEED_HIGH) {
4997 dev_info(hsotg->dev, "Set speed to default high-speed\n");
4998 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
5002 static int dwc2_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
5004 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
5006 if (!hsotg->params.change_speed_quirk)
5009 if (udev->speed == USB_SPEED_HIGH) {
5010 dev_info(hsotg->dev, "Set speed to high-speed\n");
5011 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
5012 } else if ((udev->speed == USB_SPEED_FULL ||
5013 udev->speed == USB_SPEED_LOW)) {
5015 * Change speed setting to full-speed if there's
5016 * a full-speed or low-speed device plugged in.
5018 dev_info(hsotg->dev, "Set speed to full-speed\n");
5019 dwc2_change_bus_speed(hcd, HPRT0_SPD_FULL_SPEED);
5025 static struct hc_driver dwc2_hc_driver = {
5026 .description = "dwc2_hsotg",
5027 .product_desc = "DWC OTG Controller",
5028 .hcd_priv_size = sizeof(struct wrapper_priv_data),
5030 .irq = _dwc2_hcd_irq,
5031 .flags = HCD_MEMORY | HCD_USB2 | HCD_BH,
5033 .start = _dwc2_hcd_start,
5034 .stop = _dwc2_hcd_stop,
5035 .urb_enqueue = _dwc2_hcd_urb_enqueue,
5036 .urb_dequeue = _dwc2_hcd_urb_dequeue,
5037 .endpoint_disable = _dwc2_hcd_endpoint_disable,
5038 .endpoint_reset = _dwc2_hcd_endpoint_reset,
5039 .get_frame_number = _dwc2_hcd_get_frame_number,
5041 .hub_status_data = _dwc2_hcd_hub_status_data,
5042 .hub_control = _dwc2_hcd_hub_control,
5043 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
5045 .bus_suspend = _dwc2_hcd_suspend,
5046 .bus_resume = _dwc2_hcd_resume,
5048 .map_urb_for_dma = dwc2_map_urb_for_dma,
5049 .unmap_urb_for_dma = dwc2_unmap_urb_for_dma,
5053 * Frees secondary storage associated with the dwc2_hsotg structure contained
5054 * in the struct usb_hcd field
5056 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
5062 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
5064 /* Free memory for QH/QTD lists */
5065 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
5066 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_waiting);
5067 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
5068 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
5069 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
5070 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
5071 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
5073 /* Free memory for the host channels */
5074 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
5075 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
5078 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
5080 hsotg->hc_ptr_array[i] = NULL;
5085 if (hsotg->params.host_dma) {
5086 if (hsotg->status_buf) {
5087 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
5089 hsotg->status_buf_dma);
5090 hsotg->status_buf = NULL;
5093 kfree(hsotg->status_buf);
5094 hsotg->status_buf = NULL;
5097 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
5099 /* Disable all interrupts */
5100 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
5101 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
5102 dwc2_writel(0, hsotg->regs + GINTMSK);
5104 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
5105 dctl = dwc2_readl(hsotg->regs + DCTL);
5106 dctl |= DCTL_SFTDISCON;
5107 dwc2_writel(dctl, hsotg->regs + DCTL);
5110 if (hsotg->wq_otg) {
5111 if (!cancel_work_sync(&hsotg->wf_otg))
5112 flush_workqueue(hsotg->wq_otg);
5113 destroy_workqueue(hsotg->wq_otg);
5116 del_timer(&hsotg->wkp_timer);
5119 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
5121 /* Turn off all host-specific interrupts */
5122 dwc2_disable_host_interrupts(hsotg);
5124 dwc2_hcd_free(hsotg);
5128 * Initializes the HCD. This function allocates memory for and initializes the
5129 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
5130 * USB bus with the core and calls the hc_driver->start() function. It returns
5131 * a negative error on failure.
5133 int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
5135 struct platform_device *pdev = to_platform_device(hsotg->dev);
5136 struct resource *res;
5137 struct usb_hcd *hcd;
5138 struct dwc2_host_chan *channel;
5140 int i, num_channels;
5146 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
5150 hcfg = dwc2_readl(hsotg->regs + HCFG);
5151 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
5153 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5154 hsotg->frame_num_array = kcalloc(FRAME_NUM_ARRAY_SIZE,
5155 sizeof(*hsotg->frame_num_array),
5157 if (!hsotg->frame_num_array)
5159 hsotg->last_frame_num_array =
5160 kcalloc(FRAME_NUM_ARRAY_SIZE,
5161 sizeof(*hsotg->last_frame_num_array), GFP_KERNEL);
5162 if (!hsotg->last_frame_num_array)
5165 hsotg->last_frame_num = HFNUM_MAX_FRNUM;
5167 /* Check if the bus driver or platform code has setup a dma_mask */
5168 if (hsotg->params.host_dma &&
5169 !hsotg->dev->dma_mask) {
5170 dev_warn(hsotg->dev,
5171 "dma_mask not set, disabling DMA\n");
5172 hsotg->params.host_dma = false;
5173 hsotg->params.dma_desc_enable = false;
5176 /* Set device flags indicating whether the HCD supports DMA */
5177 if (hsotg->params.host_dma) {
5178 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5179 dev_warn(hsotg->dev, "can't set DMA mask\n");
5180 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5181 dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
5184 if (hsotg->params.change_speed_quirk) {
5185 dwc2_hc_driver.free_dev = dwc2_free_dev;
5186 dwc2_hc_driver.reset_device = dwc2_reset_device;
5189 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
5193 if (!hsotg->params.host_dma)
5194 hcd->self.uses_dma = 0;
5198 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5199 hcd->rsrc_start = res->start;
5200 hcd->rsrc_len = resource_size(res);
5202 ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg;
5206 * Disable the global interrupt until all the interrupt handlers are
5209 dwc2_disable_global_interrupts(hsotg);
5211 /* Initialize the DWC_otg core, and select the Phy type */
5212 retval = dwc2_core_init(hsotg, true);
5216 /* Create new workqueue and init work */
5218 hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0);
5219 if (!hsotg->wq_otg) {
5220 dev_err(hsotg->dev, "Failed to create workqueue\n");
5223 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
5225 timer_setup(&hsotg->wkp_timer, dwc2_wakeup_detected, 0);
5227 /* Initialize the non-periodic schedule */
5228 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
5229 INIT_LIST_HEAD(&hsotg->non_periodic_sched_waiting);
5230 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
5232 /* Initialize the periodic schedule */
5233 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
5234 INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
5235 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
5236 INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
5238 INIT_LIST_HEAD(&hsotg->split_order);
5241 * Create a host channel descriptor for each host channel implemented
5242 * in the controller. Initialize the channel descriptor array.
5244 INIT_LIST_HEAD(&hsotg->free_hc_list);
5245 num_channels = hsotg->params.host_channels;
5246 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
5248 for (i = 0; i < num_channels; i++) {
5249 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
5252 channel->hc_num = i;
5253 INIT_LIST_HEAD(&channel->split_order_list_entry);
5254 hsotg->hc_ptr_array[i] = channel;
5257 /* Initialize hsotg start work */
5258 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
5260 /* Initialize port reset work */
5261 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
5264 * Allocate space for storing data on status transactions. Normally no
5265 * data is sent, but this space acts as a bit bucket. This must be
5266 * done after usb_add_hcd since that function allocates the DMA buffer
5269 if (hsotg->params.host_dma)
5270 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
5271 DWC2_HCD_STATUS_BUF_SIZE,
5272 &hsotg->status_buf_dma, GFP_KERNEL);
5274 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
5277 if (!hsotg->status_buf)
5281 * Create kmem caches to handle descriptor buffers in descriptor
5283 * Alignment must be set to 512 bytes.
5285 if (hsotg->params.dma_desc_enable ||
5286 hsotg->params.dma_desc_fs_enable) {
5287 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc",
5288 sizeof(struct dwc2_dma_desc) *
5289 MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA,
5291 if (!hsotg->desc_gen_cache) {
5293 "unable to create dwc2 generic desc cache\n");
5296 * Disable descriptor dma mode since it will not be
5299 hsotg->params.dma_desc_enable = false;
5300 hsotg->params.dma_desc_fs_enable = false;
5303 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc",
5304 sizeof(struct dwc2_dma_desc) *
5305 MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL);
5306 if (!hsotg->desc_hsisoc_cache) {
5308 "unable to create dwc2 hs isoc desc cache\n");
5310 kmem_cache_destroy(hsotg->desc_gen_cache);
5313 * Disable descriptor dma mode since it will not be
5316 hsotg->params.dma_desc_enable = false;
5317 hsotg->params.dma_desc_fs_enable = false;
5321 if (hsotg->params.host_dma) {
5323 * Create kmem caches to handle non-aligned buffer
5324 * in Buffer DMA mode.
5326 hsotg->unaligned_cache = kmem_cache_create("dwc2-unaligned-dma",
5327 DWC2_KMEM_UNALIGNED_BUF_SIZE, 4,
5328 SLAB_CACHE_DMA, NULL);
5329 if (!hsotg->unaligned_cache)
5331 "unable to create dwc2 unaligned cache\n");
5334 hsotg->otg_port = 1;
5335 hsotg->frame_list = NULL;
5336 hsotg->frame_list_dma = 0;
5337 hsotg->periodic_qh_count = 0;
5339 /* Initiate lx_state to L3 disconnected state */
5340 hsotg->lx_state = DWC2_L3;
5342 hcd->self.otg_port = hsotg->otg_port;
5344 /* Don't support SG list at this point */
5345 hcd->self.sg_tablesize = 0;
5347 if (!IS_ERR_OR_NULL(hsotg->uphy))
5348 otg_set_host(hsotg->uphy->otg, &hcd->self);
5351 * Finish generic HCD initialization and start the HCD. This function
5352 * allocates the DMA buffer pool, registers the USB bus, requests the
5353 * IRQ line, and calls hcd_start method.
5355 retval = usb_add_hcd(hcd, hsotg->irq, IRQF_SHARED);
5359 device_wakeup_enable(hcd->self.controller);
5361 dwc2_hcd_dump_state(hsotg);
5363 dwc2_enable_global_interrupts(hsotg);
5368 kmem_cache_destroy(hsotg->unaligned_cache);
5369 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5370 kmem_cache_destroy(hsotg->desc_gen_cache);
5372 dwc2_hcd_release(hsotg);
5377 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5378 kfree(hsotg->last_frame_num_array);
5379 kfree(hsotg->frame_num_array);
5382 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
5388 * Frees memory and resources associated with the HCD and deregisters the bus.
5390 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
5392 struct usb_hcd *hcd;
5394 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
5396 hcd = dwc2_hsotg_to_hcd(hsotg);
5397 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
5400 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
5405 if (!IS_ERR_OR_NULL(hsotg->uphy))
5406 otg_set_host(hsotg->uphy->otg, NULL);
5408 usb_remove_hcd(hcd);
5411 kmem_cache_destroy(hsotg->unaligned_cache);
5412 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5413 kmem_cache_destroy(hsotg->desc_gen_cache);
5415 dwc2_hcd_release(hsotg);
5418 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5419 kfree(hsotg->last_frame_num_array);
5420 kfree(hsotg->frame_num_array);
5425 * dwc2_backup_host_registers() - Backup controller host registers.
5426 * When suspending usb bus, registers needs to be backuped
5427 * if controller power is disabled once suspended.
5429 * @hsotg: Programming view of the DWC_otg controller
5431 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
5433 struct dwc2_hregs_backup *hr;
5436 dev_dbg(hsotg->dev, "%s\n", __func__);
5438 /* Backup Host regs */
5439 hr = &hsotg->hr_backup;
5440 hr->hcfg = dwc2_readl(hsotg->regs + HCFG);
5441 hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
5442 for (i = 0; i < hsotg->params.host_channels; ++i)
5443 hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i));
5445 hr->hprt0 = dwc2_read_hprt0(hsotg);
5446 hr->hfir = dwc2_readl(hsotg->regs + HFIR);
5447 hr->hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
5454 * dwc2_restore_host_registers() - Restore controller host registers.
5455 * When resuming usb bus, device registers needs to be restored
5456 * if controller power were disabled.
5458 * @hsotg: Programming view of the DWC_otg controller
5460 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
5462 struct dwc2_hregs_backup *hr;
5465 dev_dbg(hsotg->dev, "%s\n", __func__);
5467 /* Restore host regs */
5468 hr = &hsotg->hr_backup;
5470 dev_err(hsotg->dev, "%s: no host registers to restore\n",
5476 dwc2_writel(hr->hcfg, hsotg->regs + HCFG);
5477 dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK);
5479 for (i = 0; i < hsotg->params.host_channels; ++i)
5480 dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i));
5482 dwc2_writel(hr->hprt0, hsotg->regs + HPRT0);
5483 dwc2_writel(hr->hfir, hsotg->regs + HFIR);
5484 dwc2_writel(hr->hptxfsiz, hsotg->regs + HPTXFSIZ);
5485 hsotg->frame_number = 0;
5491 * dwc2_host_enter_hibernation() - Put controller in Hibernation.
5493 * @hsotg: Programming view of the DWC_otg controller
5495 int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
5497 unsigned long flags;
5504 dev_dbg(hsotg->dev, "Preparing host for hibernation\n");
5505 ret = dwc2_backup_global_registers(hsotg);
5507 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5511 ret = dwc2_backup_host_registers(hsotg);
5513 dev_err(hsotg->dev, "%s: failed to backup host registers\n",
5518 /* Enter USB Suspend Mode */
5519 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
5520 hprt0 |= HPRT0_SUSP;
5521 hprt0 &= ~HPRT0_ENA;
5522 dwc2_writel(hprt0, hsotg->regs + HPRT0);
5524 /* Wait for the HPRT0.PrtSusp register field to be set */
5525 if (dwc2_hsotg_wait_bit_set(hsotg, HPRT0, HPRT0_SUSP, 3000))
5526 dev_warn(hsotg->dev, "Suspend wasn't generated\n");
5529 * We need to disable interrupts to prevent servicing of any IRQ
5530 * during going to hibernation
5532 spin_lock_irqsave(&hsotg->lock, flags);
5533 hsotg->lx_state = DWC2_L2;
5535 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
5536 if (gusbcfg & GUSBCFG_ULPI_UTMI_SEL) {
5537 /* ULPI interface */
5538 /* Suspend the Phy Clock */
5539 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
5540 pcgcctl |= PCGCTL_STOPPCLK;
5541 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
5544 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5545 gpwrdn |= GPWRDN_PMUACTV;
5546 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5549 /* UTMI+ Interface */
5550 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5551 gpwrdn |= GPWRDN_PMUACTV;
5552 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5555 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
5556 pcgcctl |= PCGCTL_STOPPCLK;
5557 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
5561 /* Enable interrupts from wake up logic */
5562 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5563 gpwrdn |= GPWRDN_PMUINTSEL;
5564 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5567 /* Unmask host mode interrupts in GPWRDN */
5568 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5569 gpwrdn |= GPWRDN_DISCONN_DET_MSK;
5570 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5571 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5572 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5575 /* Enable Power Down Clamp */
5576 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5577 gpwrdn |= GPWRDN_PWRDNCLMP;
5578 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5581 /* Switch off VDD */
5582 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5583 gpwrdn |= GPWRDN_PWRDNSWTCH;
5584 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5586 hsotg->hibernated = 1;
5587 hsotg->bus_suspended = 1;
5588 dev_dbg(hsotg->dev, "Host hibernation completed\n");
5589 spin_unlock_irqrestore(&hsotg->lock, flags);
5594 * dwc2_host_exit_hibernation()
5596 * @hsotg: Programming view of the DWC_otg controller
5597 * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5598 * @param reset: indicates whether resume is initiated by Reset.
5600 * Return: non-zero if failed to enter to hibernation.
5602 * This function is for exiting from Host mode hibernation by
5603 * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
5605 int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
5611 struct dwc2_gregs_backup *gr;
5612 struct dwc2_hregs_backup *hr;
5614 gr = &hsotg->gr_backup;
5615 hr = &hsotg->hr_backup;
5618 "%s: called with rem_wakeup = %d reset = %d\n",
5619 __func__, rem_wakeup, reset);
5621 dwc2_hib_restore_common(hsotg, rem_wakeup, 1);
5622 hsotg->hibernated = 0;
5625 * This step is not described in functional spec but if not wait for
5626 * this delay, mismatch interrupts occurred because just after restore
5627 * core is in Device mode(gintsts.curmode == 0)
5631 /* Clear all pending interupts */
5632 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
5634 /* De-assert Restore */
5635 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5636 gpwrdn &= ~GPWRDN_RESTORE;
5637 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5640 /* Restore GUSBCFG, HCFG */
5641 dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG);
5642 dwc2_writel(hr->hcfg, hsotg->regs + HCFG);
5644 /* De-assert Wakeup Logic */
5645 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5646 gpwrdn &= ~GPWRDN_PMUACTV;
5647 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5652 hprt0 &= ~HPRT0_ENA;
5653 hprt0 &= ~HPRT0_SUSP;
5654 dwc2_writel(hprt0, hsotg->regs + HPRT0);
5658 hprt0 &= ~HPRT0_ENA;
5659 hprt0 &= ~HPRT0_SUSP;
5663 dwc2_writel(hprt0, hsotg->regs + HPRT0);
5665 /* Wait for Resume time and then program HPRT again */
5667 hprt0 &= ~HPRT0_RST;
5668 dwc2_writel(hprt0, hsotg->regs + HPRT0);
5671 dwc2_writel(hprt0, hsotg->regs + HPRT0);
5673 /* Wait for Resume time and then program HPRT again */
5675 hprt0 &= ~HPRT0_RES;
5676 dwc2_writel(hprt0, hsotg->regs + HPRT0);
5678 /* Clear all interrupt status */
5679 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
5680 hprt0 |= HPRT0_CONNDET;
5681 hprt0 |= HPRT0_ENACHG;
5682 hprt0 &= ~HPRT0_ENA;
5683 dwc2_writel(hprt0, hsotg->regs + HPRT0);
5685 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
5687 /* Clear all pending interupts */
5688 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
5690 /* Restore global registers */
5691 ret = dwc2_restore_global_registers(hsotg);
5693 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5698 /* Restore host registers */
5699 ret = dwc2_restore_host_registers(hsotg);
5701 dev_err(hsotg->dev, "%s: failed to restore host registers\n",
5706 dwc2_hcd_rem_wakeup(hsotg);
5708 hsotg->hibernated = 0;
5709 hsotg->bus_suspended = 0;
5710 hsotg->lx_state = DWC2_L0;
5711 dev_dbg(hsotg->dev, "Host hibernation restore complete\n");