1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Universal Flash Storage Host controller driver Core
4 * Copyright (C) 2011-2013 Samsung India Software Operations
5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
8 * Santosh Yaraganavi <santosh.sy@samsung.com>
9 * Vinayak Holikatti <h.vinayak@samsung.com>
12 #include <linux/async.h>
13 #include <linux/devfreq.h>
14 #include <linux/nls.h>
16 #include <linux/bitfield.h>
17 #include <linux/blk-pm.h>
18 #include <linux/blkdev.h>
19 #include <linux/clk.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/module.h>
23 #include <linux/regulator/consumer.h>
24 #include <scsi/scsi_cmnd.h>
25 #include <scsi/scsi_dbg.h>
26 #include <scsi/scsi_driver.h>
27 #include <scsi/scsi_eh.h>
28 #include "ufshcd-priv.h"
29 #include <ufs/ufs_quirks.h>
30 #include <ufs/unipro.h>
31 #include "ufs-sysfs.h"
32 #include "ufs-debugfs.h"
33 #include "ufs-fault-injection.h"
35 #include "ufshcd-crypto.h"
37 #include <asm/unaligned.h>
39 #define CREATE_TRACE_POINTS
40 #include <trace/events/ufs.h>
42 #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
45 /* UIC command timeout, unit: ms */
46 #define UIC_CMD_TIMEOUT 500
48 /* NOP OUT retries waiting for NOP IN response */
49 #define NOP_OUT_RETRIES 10
50 /* Timeout after 50 msecs if NOP OUT hangs without response */
51 #define NOP_OUT_TIMEOUT 50 /* msecs */
53 /* Query request retries */
54 #define QUERY_REQ_RETRIES 3
55 /* Query request timeout */
56 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
58 /* Task management command timeout */
59 #define TM_CMD_TIMEOUT 100 /* msecs */
61 /* maximum number of retries for a general UIC command */
62 #define UFS_UIC_COMMAND_RETRIES 3
64 /* maximum number of link-startup retries */
65 #define DME_LINKSTARTUP_RETRIES 3
67 /* Maximum retries for Hibern8 enter */
68 #define UIC_HIBERN8_ENTER_RETRIES 3
70 /* maximum number of reset retries before giving up */
71 #define MAX_HOST_RESET_RETRIES 5
73 /* Maximum number of error handler retries before giving up */
74 #define MAX_ERR_HANDLER_RETRIES 5
76 /* Expose the flag value from utp_upiu_query.value */
77 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF
79 /* Interrupt aggregation default timeout, unit: 40us */
80 #define INT_AGGR_DEF_TO 0x02
82 /* default delay of autosuspend: 2000 ms */
83 #define RPM_AUTOSUSPEND_DELAY_MS 2000
85 /* Default delay of RPM device flush delayed work */
86 #define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000
88 /* Default value of wait time before gating device ref clock */
89 #define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */
91 /* Polling time to wait for fDeviceInit */
92 #define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */
94 #define ufshcd_toggle_vreg(_dev, _vreg, _on) \
98 _ret = ufshcd_enable_vreg(_dev, _vreg); \
100 _ret = ufshcd_disable_vreg(_dev, _vreg); \
104 #define ufshcd_hex_dump(prefix_str, buf, len) do { \
105 size_t __len = (len); \
106 print_hex_dump(KERN_ERR, prefix_str, \
107 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\
108 16, 4, buf, __len, false); \
111 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
117 if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */
120 regs = kzalloc(len, GFP_ATOMIC);
124 for (pos = 0; pos < len; pos += 4) {
126 pos >= REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER &&
127 pos <= REG_UIC_ERROR_CODE_DME)
129 regs[pos / 4] = ufshcd_readl(hba, offset + pos);
132 ufshcd_hex_dump(prefix, regs, len);
137 EXPORT_SYMBOL_GPL(ufshcd_dump_regs);
140 UFSHCD_MAX_CHANNEL = 0,
142 UFSHCD_NUM_RESERVED = 1,
143 UFSHCD_CMD_PER_LUN = 32 - UFSHCD_NUM_RESERVED,
144 UFSHCD_CAN_QUEUE = 32 - UFSHCD_NUM_RESERVED,
147 static const char *const ufshcd_state_name[] = {
148 [UFSHCD_STATE_RESET] = "reset",
149 [UFSHCD_STATE_OPERATIONAL] = "operational",
150 [UFSHCD_STATE_ERROR] = "error",
151 [UFSHCD_STATE_EH_SCHEDULED_FATAL] = "eh_fatal",
152 [UFSHCD_STATE_EH_SCHEDULED_NON_FATAL] = "eh_non_fatal",
155 /* UFSHCD error handling flags */
157 UFSHCD_EH_IN_PROGRESS = (1 << 0),
160 /* UFSHCD UIC layer error flags */
162 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */
163 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */
164 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */
165 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */
166 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */
167 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */
168 UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6), /* Generic PA error */
171 #define ufshcd_set_eh_in_progress(h) \
172 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS)
173 #define ufshcd_eh_in_progress(h) \
174 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS)
175 #define ufshcd_clear_eh_in_progress(h) \
176 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS)
178 struct ufs_pm_lvl_states ufs_pm_lvl_states[] = {
179 [UFS_PM_LVL_0] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE},
180 [UFS_PM_LVL_1] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE},
181 [UFS_PM_LVL_2] = {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE},
182 [UFS_PM_LVL_3] = {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE},
183 [UFS_PM_LVL_4] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE},
184 [UFS_PM_LVL_5] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE},
186 * For DeepSleep, the link is first put in hibern8 and then off.
187 * Leaving the link in hibern8 is not supported.
189 [UFS_PM_LVL_6] = {UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE},
192 static inline enum ufs_dev_pwr_mode
193 ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl)
195 return ufs_pm_lvl_states[lvl].dev_state;
198 static inline enum uic_link_state
199 ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl)
201 return ufs_pm_lvl_states[lvl].link_state;
204 static inline enum ufs_pm_level
205 ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state,
206 enum uic_link_state link_state)
208 enum ufs_pm_level lvl;
210 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) {
211 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) &&
212 (ufs_pm_lvl_states[lvl].link_state == link_state))
216 /* if no match found, return the level 0 */
220 static const struct ufs_dev_quirk ufs_fixups[] = {
221 /* UFS cards deviations table */
222 { .wmanufacturerid = UFS_VENDOR_MICRON,
223 .model = UFS_ANY_MODEL,
224 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
225 UFS_DEVICE_QUIRK_SWAP_L2P_ENTRY_FOR_HPB_READ },
226 { .wmanufacturerid = UFS_VENDOR_SAMSUNG,
227 .model = UFS_ANY_MODEL,
228 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM |
229 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE |
230 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS },
231 { .wmanufacturerid = UFS_VENDOR_SKHYNIX,
232 .model = UFS_ANY_MODEL,
233 .quirk = UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME },
234 { .wmanufacturerid = UFS_VENDOR_SKHYNIX,
235 .model = "hB8aL1" /*H28U62301AMR*/,
236 .quirk = UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME },
237 { .wmanufacturerid = UFS_VENDOR_TOSHIBA,
238 .model = UFS_ANY_MODEL,
239 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM },
240 { .wmanufacturerid = UFS_VENDOR_TOSHIBA,
241 .model = "THGLF2G9C8KBADG",
242 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE },
243 { .wmanufacturerid = UFS_VENDOR_TOSHIBA,
244 .model = "THGLF2G9D8KBADG",
245 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE },
249 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba);
250 static void ufshcd_async_scan(void *data, async_cookie_t cookie);
251 static int ufshcd_reset_and_restore(struct ufs_hba *hba);
252 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd);
253 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag);
254 static void ufshcd_hba_exit(struct ufs_hba *hba);
255 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params);
256 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on);
257 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba);
258 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba);
259 static void ufshcd_resume_clkscaling(struct ufs_hba *hba);
260 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba);
261 static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba);
262 static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up);
263 static irqreturn_t ufshcd_intr(int irq, void *__hba);
264 static int ufshcd_change_power_mode(struct ufs_hba *hba,
265 struct ufs_pa_layer_attr *pwr_mode);
266 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on);
267 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on);
268 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
269 struct ufs_vreg *vreg);
270 static int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag);
271 static void ufshcd_wb_toggle_flush_during_h8(struct ufs_hba *hba, bool set);
272 static inline void ufshcd_wb_toggle_flush(struct ufs_hba *hba, bool enable);
273 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba);
274 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba);
276 static inline void ufshcd_enable_irq(struct ufs_hba *hba)
278 if (!hba->is_irq_enabled) {
279 enable_irq(hba->irq);
280 hba->is_irq_enabled = true;
284 static inline void ufshcd_disable_irq(struct ufs_hba *hba)
286 if (hba->is_irq_enabled) {
287 disable_irq(hba->irq);
288 hba->is_irq_enabled = false;
292 static inline void ufshcd_wb_config(struct ufs_hba *hba)
294 if (!ufshcd_is_wb_allowed(hba))
297 ufshcd_wb_toggle(hba, true);
299 ufshcd_wb_toggle_flush_during_h8(hba, true);
300 if (!(hba->quirks & UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL))
301 ufshcd_wb_toggle_flush(hba, true);
304 static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba)
306 if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt))
307 scsi_unblock_requests(hba->host);
310 static void ufshcd_scsi_block_requests(struct ufs_hba *hba)
312 if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1)
313 scsi_block_requests(hba->host);
316 static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag,
317 enum ufs_trace_str_t str_t)
319 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr;
320 struct utp_upiu_header *header;
322 if (!trace_ufshcd_upiu_enabled())
325 if (str_t == UFS_CMD_SEND)
326 header = &rq->header;
328 header = &hba->lrb[tag].ucd_rsp_ptr->header;
330 trace_ufshcd_upiu(dev_name(hba->dev), str_t, header, &rq->sc.cdb,
334 static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba,
335 enum ufs_trace_str_t str_t,
336 struct utp_upiu_req *rq_rsp)
338 if (!trace_ufshcd_upiu_enabled())
341 trace_ufshcd_upiu(dev_name(hba->dev), str_t, &rq_rsp->header,
342 &rq_rsp->qr, UFS_TSF_OSF);
345 static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag,
346 enum ufs_trace_str_t str_t)
348 struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[tag];
350 if (!trace_ufshcd_upiu_enabled())
353 if (str_t == UFS_TM_SEND)
354 trace_ufshcd_upiu(dev_name(hba->dev), str_t,
355 &descp->upiu_req.req_header,
356 &descp->upiu_req.input_param1,
359 trace_ufshcd_upiu(dev_name(hba->dev), str_t,
360 &descp->upiu_rsp.rsp_header,
361 &descp->upiu_rsp.output_param1,
365 static void ufshcd_add_uic_command_trace(struct ufs_hba *hba,
366 struct uic_command *ucmd,
367 enum ufs_trace_str_t str_t)
371 if (!trace_ufshcd_uic_command_enabled())
374 if (str_t == UFS_CMD_SEND)
377 cmd = ufshcd_readl(hba, REG_UIC_COMMAND);
379 trace_ufshcd_uic_command(dev_name(hba->dev), str_t, cmd,
380 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1),
381 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2),
382 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3));
385 static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag,
386 enum ufs_trace_str_t str_t)
389 u8 opcode = 0, group_id = 0;
391 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
392 struct scsi_cmnd *cmd = lrbp->cmd;
393 struct request *rq = scsi_cmd_to_rq(cmd);
394 int transfer_len = -1;
399 /* trace UPIU also */
400 ufshcd_add_cmd_upiu_trace(hba, tag, str_t);
401 if (!trace_ufshcd_command_enabled())
404 opcode = cmd->cmnd[0];
406 if (opcode == READ_10 || opcode == WRITE_10) {
408 * Currently we only fully trace read(10) and write(10) commands
411 be32_to_cpu(lrbp->ucd_req_ptr->sc.exp_data_transfer_len);
412 lba = scsi_get_lba(cmd);
413 if (opcode == WRITE_10)
414 group_id = lrbp->cmd->cmnd[6];
415 } else if (opcode == UNMAP) {
417 * The number of Bytes to be unmapped beginning with the lba.
419 transfer_len = blk_rq_bytes(rq);
420 lba = scsi_get_lba(cmd);
423 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
424 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
425 trace_ufshcd_command(dev_name(hba->dev), str_t, tag,
426 doorbell, transfer_len, intr, lba, opcode, group_id);
429 static void ufshcd_print_clk_freqs(struct ufs_hba *hba)
431 struct ufs_clk_info *clki;
432 struct list_head *head = &hba->clk_list_head;
434 if (list_empty(head))
437 list_for_each_entry(clki, head, list) {
438 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq &&
440 dev_err(hba->dev, "clk: %s, rate: %u\n",
441 clki->name, clki->curr_freq);
445 static void ufshcd_print_evt(struct ufs_hba *hba, u32 id,
450 struct ufs_event_hist *e;
452 if (id >= UFS_EVT_CNT)
455 e = &hba->ufs_stats.event[id];
457 for (i = 0; i < UFS_EVENT_HIST_LENGTH; i++) {
458 int p = (i + e->pos) % UFS_EVENT_HIST_LENGTH;
460 if (e->tstamp[p] == 0)
462 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p,
463 e->val[p], ktime_to_us(e->tstamp[p]));
468 dev_err(hba->dev, "No record of %s\n", err_name);
470 dev_err(hba->dev, "%s: total cnt=%llu\n", err_name, e->cnt);
473 static void ufshcd_print_evt_hist(struct ufs_hba *hba)
475 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
477 ufshcd_print_evt(hba, UFS_EVT_PA_ERR, "pa_err");
478 ufshcd_print_evt(hba, UFS_EVT_DL_ERR, "dl_err");
479 ufshcd_print_evt(hba, UFS_EVT_NL_ERR, "nl_err");
480 ufshcd_print_evt(hba, UFS_EVT_TL_ERR, "tl_err");
481 ufshcd_print_evt(hba, UFS_EVT_DME_ERR, "dme_err");
482 ufshcd_print_evt(hba, UFS_EVT_AUTO_HIBERN8_ERR,
484 ufshcd_print_evt(hba, UFS_EVT_FATAL_ERR, "fatal_err");
485 ufshcd_print_evt(hba, UFS_EVT_LINK_STARTUP_FAIL,
486 "link_startup_fail");
487 ufshcd_print_evt(hba, UFS_EVT_RESUME_ERR, "resume_fail");
488 ufshcd_print_evt(hba, UFS_EVT_SUSPEND_ERR,
490 ufshcd_print_evt(hba, UFS_EVT_DEV_RESET, "dev_reset");
491 ufshcd_print_evt(hba, UFS_EVT_HOST_RESET, "host_reset");
492 ufshcd_print_evt(hba, UFS_EVT_ABORT, "task_abort");
494 ufshcd_vops_dbg_register_dump(hba);
498 void ufshcd_print_trs(struct ufs_hba *hba, unsigned long bitmap, bool pr_prdt)
500 struct ufshcd_lrb *lrbp;
504 for_each_set_bit(tag, &bitmap, hba->nutrs) {
505 lrbp = &hba->lrb[tag];
507 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n",
508 tag, ktime_to_us(lrbp->issue_time_stamp));
509 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n",
510 tag, ktime_to_us(lrbp->compl_time_stamp));
512 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n",
513 tag, (u64)lrbp->utrd_dma_addr);
515 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr,
516 sizeof(struct utp_transfer_req_desc));
517 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag,
518 (u64)lrbp->ucd_req_dma_addr);
519 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr,
520 sizeof(struct utp_upiu_req));
521 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag,
522 (u64)lrbp->ucd_rsp_dma_addr);
523 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr,
524 sizeof(struct utp_upiu_rsp));
526 prdt_length = le16_to_cpu(
527 lrbp->utr_descriptor_ptr->prd_table_length);
528 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
529 prdt_length /= sizeof(struct ufshcd_sg_entry);
532 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n",
534 (u64)lrbp->ucd_prdt_dma_addr);
537 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr,
538 sizeof(struct ufshcd_sg_entry) * prdt_length);
542 static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap)
546 for_each_set_bit(tag, &bitmap, hba->nutmrs) {
547 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag];
549 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag);
550 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp));
554 static void ufshcd_print_host_state(struct ufs_hba *hba)
556 struct scsi_device *sdev_ufs = hba->ufs_device_wlun;
558 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state);
559 dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n",
560 hba->outstanding_reqs, hba->outstanding_tasks);
561 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n",
562 hba->saved_err, hba->saved_uic_err);
563 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n",
564 hba->curr_dev_pwr_mode, hba->uic_link_state);
565 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n",
566 hba->pm_op_in_progress, hba->is_sys_suspended);
567 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n",
568 hba->auto_bkops_enabled, hba->host->host_self_blocked);
569 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state);
571 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n",
572 ktime_to_us(hba->ufs_stats.last_hibern8_exit_tstamp),
573 hba->ufs_stats.hibern8_exit_cnt);
574 dev_err(hba->dev, "last intr at %lld us, last intr status=0x%x\n",
575 ktime_to_us(hba->ufs_stats.last_intr_ts),
576 hba->ufs_stats.last_intr_status);
577 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n",
578 hba->eh_flags, hba->req_abort_count);
579 dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n",
580 hba->ufs_version, hba->capabilities, hba->caps);
581 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks,
584 dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n",
585 sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev);
587 ufshcd_print_clk_freqs(hba);
591 * ufshcd_print_pwr_info - print power params as saved in hba
593 * @hba: per-adapter instance
595 static void ufshcd_print_pwr_info(struct ufs_hba *hba)
597 static const char * const names[] = {
608 * Using dev_dbg to avoid messages during runtime PM to avoid
609 * never-ending cycles of messages written back to storage by user space
610 * causing runtime resume, causing more messages and so on.
612 dev_dbg(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
614 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
615 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
616 names[hba->pwr_info.pwr_rx],
617 names[hba->pwr_info.pwr_tx],
618 hba->pwr_info.hs_rate);
621 static void ufshcd_device_reset(struct ufs_hba *hba)
625 err = ufshcd_vops_device_reset(hba);
628 ufshcd_set_ufs_dev_active(hba);
629 if (ufshcd_is_wb_allowed(hba)) {
630 hba->dev_info.wb_enabled = false;
631 hba->dev_info.wb_buf_flush_enabled = false;
634 if (err != -EOPNOTSUPP)
635 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err);
638 void ufshcd_delay_us(unsigned long us, unsigned long tolerance)
646 usleep_range(us, us + tolerance);
648 EXPORT_SYMBOL_GPL(ufshcd_delay_us);
651 * ufshcd_wait_for_register - wait for register value to change
652 * @hba: per-adapter interface
653 * @reg: mmio register offset
654 * @mask: mask to apply to the read register value
655 * @val: value to wait for
656 * @interval_us: polling interval in microseconds
657 * @timeout_ms: timeout in milliseconds
660 * -ETIMEDOUT on error, zero on success.
662 static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
663 u32 val, unsigned long interval_us,
664 unsigned long timeout_ms)
667 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
669 /* ignore bits that we don't intend to wait on */
672 while ((ufshcd_readl(hba, reg) & mask) != val) {
673 usleep_range(interval_us, interval_us + 50);
674 if (time_after(jiffies, timeout)) {
675 if ((ufshcd_readl(hba, reg) & mask) != val)
685 * ufshcd_get_intr_mask - Get the interrupt bit mask
686 * @hba: Pointer to adapter instance
688 * Returns interrupt bit mask per version
690 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
692 if (hba->ufs_version == ufshci_version(1, 0))
693 return INTERRUPT_MASK_ALL_VER_10;
694 if (hba->ufs_version <= ufshci_version(2, 0))
695 return INTERRUPT_MASK_ALL_VER_11;
697 return INTERRUPT_MASK_ALL_VER_21;
701 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
702 * @hba: Pointer to adapter instance
704 * Returns UFSHCI version supported by the controller
706 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
710 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION)
711 ufshci_ver = ufshcd_vops_get_ufs_hci_version(hba);
713 ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION);
716 * UFSHCI v1.x uses a different version scheme, in order
717 * to allow the use of comparisons with the ufshci_version
718 * function, we convert it to the same scheme as ufs 2.0+.
720 if (ufshci_ver & 0x00010000)
721 return ufshci_version(1, ufshci_ver & 0x00000100);
727 * ufshcd_is_device_present - Check if any device connected to
728 * the host controller
729 * @hba: pointer to adapter instance
731 * Returns true if device present, false if no device detected
733 static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
735 return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & DEVICE_PRESENT;
739 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
740 * @lrbp: pointer to local command reference block
742 * This function is used to get the OCS field from UTRD
743 * Returns the OCS field in the UTRD
745 static enum utp_ocs ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
747 return le32_to_cpu(lrbp->utr_descriptor_ptr->header.dword_2) & MASK_OCS;
751 * ufshcd_utrl_clear() - Clear requests from the controller request list.
752 * @hba: per adapter instance
753 * @mask: mask with one bit set for each request to be cleared
755 static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 mask)
757 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
760 * From the UFSHCI specification: "UTP Transfer Request List CLear
761 * Register (UTRLCLR): This field is bit significant. Each bit
762 * corresponds to a slot in the UTP Transfer Request List, where bit 0
763 * corresponds to request slot 0. A bit in this field is set to ‘0’
764 * by host software to indicate to the host controller that a transfer
765 * request slot is cleared. The host controller
766 * shall free up any resources associated to the request slot
767 * immediately, and shall set the associated bit in UTRLDBR to ‘0’. The
768 * host software indicates no change to request slots by setting the
769 * associated bits in this field to ‘1’. Bits in this field shall only
770 * be set ‘1’ or ‘0’ by host software when UTRLRSR is set to ‘1’."
772 ufshcd_writel(hba, ~mask, REG_UTP_TRANSFER_REQ_LIST_CLEAR);
776 * ufshcd_utmrl_clear - Clear a bit in UTRMLCLR register
777 * @hba: per adapter instance
778 * @pos: position of the bit to be cleared
780 static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos)
782 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR)
783 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
785 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR);
789 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
790 * @reg: Register value of host controller status
792 * Returns integer, 0 on Success and positive value if failed
794 static inline int ufshcd_get_lists_status(u32 reg)
796 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
800 * ufshcd_get_uic_cmd_result - Get the UIC command result
801 * @hba: Pointer to adapter instance
803 * This function gets the result of UIC command completion
804 * Returns 0 on success, non zero value on error
806 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
808 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
809 MASK_UIC_COMMAND_RESULT;
813 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
814 * @hba: Pointer to adapter instance
816 * This function gets UIC command argument3
817 * Returns 0 on success, non zero value on error
819 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
821 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
825 * ufshcd_get_req_rsp - returns the TR response transaction type
826 * @ucd_rsp_ptr: pointer to response UPIU
829 ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
831 return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
835 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
836 * @ucd_rsp_ptr: pointer to response UPIU
838 * This function gets the response status and scsi_status from response UPIU
839 * Returns the response result code.
842 ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
844 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
848 * ufshcd_get_rsp_upiu_data_seg_len - Get the data segment length
850 * @ucd_rsp_ptr: pointer to response UPIU
852 * Return the data segment length.
854 static inline unsigned int
855 ufshcd_get_rsp_upiu_data_seg_len(struct utp_upiu_rsp *ucd_rsp_ptr)
857 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
858 MASK_RSP_UPIU_DATA_SEG_LEN;
862 * ufshcd_is_exception_event - Check if the device raised an exception event
863 * @ucd_rsp_ptr: pointer to response UPIU
865 * The function checks if the device raised an exception event indicated in
866 * the Device Information field of response UPIU.
868 * Returns true if exception is raised, false otherwise.
870 static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr)
872 return be32_to_cpu(ucd_rsp_ptr->header.dword_2) &
873 MASK_RSP_EXCEPTION_EVENT;
877 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values.
878 * @hba: per adapter instance
881 ufshcd_reset_intr_aggr(struct ufs_hba *hba)
883 ufshcd_writel(hba, INT_AGGR_ENABLE |
884 INT_AGGR_COUNTER_AND_TIMER_RESET,
885 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
889 * ufshcd_config_intr_aggr - Configure interrupt aggregation values.
890 * @hba: per adapter instance
891 * @cnt: Interrupt aggregation counter threshold
892 * @tmout: Interrupt aggregation timeout value
895 ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout)
897 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE |
898 INT_AGGR_COUNTER_THLD_VAL(cnt) |
899 INT_AGGR_TIMEOUT_VAL(tmout),
900 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
904 * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
905 * @hba: per adapter instance
907 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
909 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
913 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
914 * When run-stop registers are set to 1, it indicates the
915 * host controller that it can process the requests
916 * @hba: per adapter instance
918 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
920 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
921 REG_UTP_TASK_REQ_LIST_RUN_STOP);
922 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
923 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
927 * ufshcd_hba_start - Start controller initialization sequence
928 * @hba: per adapter instance
930 static inline void ufshcd_hba_start(struct ufs_hba *hba)
932 u32 val = CONTROLLER_ENABLE;
934 if (ufshcd_crypto_enable(hba))
935 val |= CRYPTO_GENERAL_ENABLE;
937 ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE);
941 * ufshcd_is_hba_active - Get controller state
942 * @hba: per adapter instance
944 * Returns true if and only if the controller is active.
946 static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
948 return ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE;
951 u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba)
953 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */
954 if (hba->ufs_version <= ufshci_version(1, 1))
955 return UFS_UNIPRO_VER_1_41;
957 return UFS_UNIPRO_VER_1_6;
959 EXPORT_SYMBOL(ufshcd_get_local_unipro_ver);
961 static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba)
964 * If both host and device support UniPro ver1.6 or later, PA layer
965 * parameters tuning happens during link startup itself.
967 * We can manually tune PA layer parameters if either host or device
968 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning
969 * logic simple, we will only do manual tuning if local unipro version
970 * doesn't support ver1.6 or later.
972 return ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6;
976 * ufshcd_set_clk_freq - set UFS controller clock frequencies
977 * @hba: per adapter instance
978 * @scale_up: If True, set max possible frequency othewise set low frequency
980 * Returns 0 if successful
981 * Returns < 0 for any other errors
983 static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up)
986 struct ufs_clk_info *clki;
987 struct list_head *head = &hba->clk_list_head;
989 if (list_empty(head))
992 list_for_each_entry(clki, head, list) {
993 if (!IS_ERR_OR_NULL(clki->clk)) {
994 if (scale_up && clki->max_freq) {
995 if (clki->curr_freq == clki->max_freq)
998 ret = clk_set_rate(clki->clk, clki->max_freq);
1000 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
1001 __func__, clki->name,
1002 clki->max_freq, ret);
1005 trace_ufshcd_clk_scaling(dev_name(hba->dev),
1006 "scaled up", clki->name,
1010 clki->curr_freq = clki->max_freq;
1012 } else if (!scale_up && clki->min_freq) {
1013 if (clki->curr_freq == clki->min_freq)
1016 ret = clk_set_rate(clki->clk, clki->min_freq);
1018 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
1019 __func__, clki->name,
1020 clki->min_freq, ret);
1023 trace_ufshcd_clk_scaling(dev_name(hba->dev),
1024 "scaled down", clki->name,
1027 clki->curr_freq = clki->min_freq;
1030 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__,
1031 clki->name, clk_get_rate(clki->clk));
1039 * ufshcd_scale_clks - scale up or scale down UFS controller clocks
1040 * @hba: per adapter instance
1041 * @scale_up: True if scaling up and false if scaling down
1043 * Returns 0 if successful
1044 * Returns < 0 for any other errors
1046 static int ufshcd_scale_clks(struct ufs_hba *hba, bool scale_up)
1049 ktime_t start = ktime_get();
1051 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE);
1055 ret = ufshcd_set_clk_freq(hba, scale_up);
1059 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE);
1061 ufshcd_set_clk_freq(hba, !scale_up);
1064 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1065 (scale_up ? "up" : "down"),
1066 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1071 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not
1072 * @hba: per adapter instance
1073 * @scale_up: True if scaling up and false if scaling down
1075 * Returns true if scaling is required, false otherwise.
1077 static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba,
1080 struct ufs_clk_info *clki;
1081 struct list_head *head = &hba->clk_list_head;
1083 if (list_empty(head))
1086 list_for_each_entry(clki, head, list) {
1087 if (!IS_ERR_OR_NULL(clki->clk)) {
1088 if (scale_up && clki->max_freq) {
1089 if (clki->curr_freq == clki->max_freq)
1092 } else if (!scale_up && clki->min_freq) {
1093 if (clki->curr_freq == clki->min_freq)
1104 * Determine the number of pending commands by counting the bits in the SCSI
1105 * device budget maps. This approach has been selected because a bit is set in
1106 * the budget map before scsi_host_queue_ready() checks the host_self_blocked
1107 * flag. The host_self_blocked flag can be modified by calling
1108 * scsi_block_requests() or scsi_unblock_requests().
1110 static u32 ufshcd_pending_cmds(struct ufs_hba *hba)
1112 struct scsi_device *sdev;
1115 lockdep_assert_held(hba->host->host_lock);
1116 __shost_for_each_device(sdev, hba->host)
1117 pending += sbitmap_weight(&sdev->budget_map);
1122 static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba,
1123 u64 wait_timeout_us)
1125 unsigned long flags;
1129 bool timeout = false, do_last_check = false;
1132 ufshcd_hold(hba, false);
1133 spin_lock_irqsave(hba->host->host_lock, flags);
1135 * Wait for all the outstanding tasks/transfer requests.
1136 * Verify by checking the doorbell registers are clear.
1138 start = ktime_get();
1140 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
1145 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
1146 tr_pending = ufshcd_pending_cmds(hba);
1147 if (!tm_doorbell && !tr_pending) {
1150 } else if (do_last_check) {
1154 spin_unlock_irqrestore(hba->host->host_lock, flags);
1156 if (ktime_to_us(ktime_sub(ktime_get(), start)) >
1160 * We might have scheduled out for long time so make
1161 * sure to check if doorbells are cleared by this time
1164 do_last_check = true;
1166 spin_lock_irqsave(hba->host->host_lock, flags);
1167 } while (tm_doorbell || tr_pending);
1171 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n",
1172 __func__, tm_doorbell, tr_pending);
1176 spin_unlock_irqrestore(hba->host->host_lock, flags);
1177 ufshcd_release(hba);
1182 * ufshcd_scale_gear - scale up/down UFS gear
1183 * @hba: per adapter instance
1184 * @scale_up: True for scaling up gear and false for scaling down
1186 * Returns 0 for success,
1187 * Returns -EBUSY if scaling can't happen at this time
1188 * Returns non-zero for any other errors
1190 static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up)
1193 struct ufs_pa_layer_attr new_pwr_info;
1196 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info.info,
1197 sizeof(struct ufs_pa_layer_attr));
1199 memcpy(&new_pwr_info, &hba->pwr_info,
1200 sizeof(struct ufs_pa_layer_attr));
1202 if (hba->pwr_info.gear_tx > hba->clk_scaling.min_gear ||
1203 hba->pwr_info.gear_rx > hba->clk_scaling.min_gear) {
1204 /* save the current power mode */
1205 memcpy(&hba->clk_scaling.saved_pwr_info.info,
1207 sizeof(struct ufs_pa_layer_attr));
1209 /* scale down gear */
1210 new_pwr_info.gear_tx = hba->clk_scaling.min_gear;
1211 new_pwr_info.gear_rx = hba->clk_scaling.min_gear;
1215 /* check if the power mode needs to be changed or not? */
1216 ret = ufshcd_config_pwr_mode(hba, &new_pwr_info);
1218 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)",
1220 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx,
1221 new_pwr_info.gear_tx, new_pwr_info.gear_rx);
1226 static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba)
1228 #define DOORBELL_CLR_TOUT_US (1000 * 1000) /* 1 sec */
1231 * make sure that there are no outstanding requests when
1232 * clock scaling is in progress
1234 ufshcd_scsi_block_requests(hba);
1235 down_write(&hba->clk_scaling_lock);
1237 if (!hba->clk_scaling.is_allowed ||
1238 ufshcd_wait_for_doorbell_clr(hba, DOORBELL_CLR_TOUT_US)) {
1240 up_write(&hba->clk_scaling_lock);
1241 ufshcd_scsi_unblock_requests(hba);
1245 /* let's not get into low power until clock scaling is completed */
1246 ufshcd_hold(hba, false);
1252 static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, bool writelock)
1255 up_write(&hba->clk_scaling_lock);
1257 up_read(&hba->clk_scaling_lock);
1258 ufshcd_scsi_unblock_requests(hba);
1259 ufshcd_release(hba);
1263 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear
1264 * @hba: per adapter instance
1265 * @scale_up: True for scaling up and false for scalin down
1267 * Returns 0 for success,
1268 * Returns -EBUSY if scaling can't happen at this time
1269 * Returns non-zero for any other errors
1271 static int ufshcd_devfreq_scale(struct ufs_hba *hba, bool scale_up)
1274 bool is_writelock = true;
1276 ret = ufshcd_clock_scaling_prepare(hba);
1280 /* scale down the gear before scaling down clocks */
1282 ret = ufshcd_scale_gear(hba, false);
1287 ret = ufshcd_scale_clks(hba, scale_up);
1290 ufshcd_scale_gear(hba, true);
1294 /* scale up the gear after scaling up clocks */
1296 ret = ufshcd_scale_gear(hba, true);
1298 ufshcd_scale_clks(hba, false);
1303 /* Enable Write Booster if we have scaled up else disable it */
1304 downgrade_write(&hba->clk_scaling_lock);
1305 is_writelock = false;
1306 ufshcd_wb_toggle(hba, scale_up);
1309 ufshcd_clock_scaling_unprepare(hba, is_writelock);
1313 static void ufshcd_clk_scaling_suspend_work(struct work_struct *work)
1315 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1316 clk_scaling.suspend_work);
1317 unsigned long irq_flags;
1319 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1320 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) {
1321 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1324 hba->clk_scaling.is_suspended = true;
1325 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1327 __ufshcd_suspend_clkscaling(hba);
1330 static void ufshcd_clk_scaling_resume_work(struct work_struct *work)
1332 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1333 clk_scaling.resume_work);
1334 unsigned long irq_flags;
1336 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1337 if (!hba->clk_scaling.is_suspended) {
1338 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1341 hba->clk_scaling.is_suspended = false;
1342 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1344 devfreq_resume_device(hba->devfreq);
1347 static int ufshcd_devfreq_target(struct device *dev,
1348 unsigned long *freq, u32 flags)
1351 struct ufs_hba *hba = dev_get_drvdata(dev);
1353 bool scale_up, sched_clk_scaling_suspend_work = false;
1354 struct list_head *clk_list = &hba->clk_list_head;
1355 struct ufs_clk_info *clki;
1356 unsigned long irq_flags;
1358 if (!ufshcd_is_clkscaling_supported(hba))
1361 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, list);
1362 /* Override with the closest supported frequency */
1363 *freq = (unsigned long) clk_round_rate(clki->clk, *freq);
1364 spin_lock_irqsave(hba->host->host_lock, irq_flags);
1365 if (ufshcd_eh_in_progress(hba)) {
1366 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1370 if (!hba->clk_scaling.active_reqs)
1371 sched_clk_scaling_suspend_work = true;
1373 if (list_empty(clk_list)) {
1374 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1378 /* Decide based on the rounded-off frequency and update */
1379 scale_up = *freq == clki->max_freq;
1381 *freq = clki->min_freq;
1382 /* Update the frequency */
1383 if (!ufshcd_is_devfreq_scaling_required(hba, scale_up)) {
1384 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1386 goto out; /* no state change required */
1388 spin_unlock_irqrestore(hba->host->host_lock, irq_flags);
1390 start = ktime_get();
1391 ret = ufshcd_devfreq_scale(hba, scale_up);
1393 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev),
1394 (scale_up ? "up" : "down"),
1395 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
1398 if (sched_clk_scaling_suspend_work)
1399 queue_work(hba->clk_scaling.workq,
1400 &hba->clk_scaling.suspend_work);
1405 static int ufshcd_devfreq_get_dev_status(struct device *dev,
1406 struct devfreq_dev_status *stat)
1408 struct ufs_hba *hba = dev_get_drvdata(dev);
1409 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
1410 unsigned long flags;
1411 struct list_head *clk_list = &hba->clk_list_head;
1412 struct ufs_clk_info *clki;
1415 if (!ufshcd_is_clkscaling_supported(hba))
1418 memset(stat, 0, sizeof(*stat));
1420 spin_lock_irqsave(hba->host->host_lock, flags);
1421 curr_t = ktime_get();
1422 if (!scaling->window_start_t)
1425 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1427 * If current frequency is 0, then the ondemand governor considers
1428 * there's no initial frequency set. And it always requests to set
1429 * to max. frequency.
1431 stat->current_frequency = clki->curr_freq;
1432 if (scaling->is_busy_started)
1433 scaling->tot_busy_t += ktime_us_delta(curr_t,
1434 scaling->busy_start_t);
1436 stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t);
1437 stat->busy_time = scaling->tot_busy_t;
1439 scaling->window_start_t = curr_t;
1440 scaling->tot_busy_t = 0;
1442 if (hba->outstanding_reqs) {
1443 scaling->busy_start_t = curr_t;
1444 scaling->is_busy_started = true;
1446 scaling->busy_start_t = 0;
1447 scaling->is_busy_started = false;
1449 spin_unlock_irqrestore(hba->host->host_lock, flags);
1453 static int ufshcd_devfreq_init(struct ufs_hba *hba)
1455 struct list_head *clk_list = &hba->clk_list_head;
1456 struct ufs_clk_info *clki;
1457 struct devfreq *devfreq;
1460 /* Skip devfreq if we don't have any clocks in the list */
1461 if (list_empty(clk_list))
1464 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1465 dev_pm_opp_add(hba->dev, clki->min_freq, 0);
1466 dev_pm_opp_add(hba->dev, clki->max_freq, 0);
1468 ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile,
1469 &hba->vps->ondemand_data);
1470 devfreq = devfreq_add_device(hba->dev,
1471 &hba->vps->devfreq_profile,
1472 DEVFREQ_GOV_SIMPLE_ONDEMAND,
1473 &hba->vps->ondemand_data);
1474 if (IS_ERR(devfreq)) {
1475 ret = PTR_ERR(devfreq);
1476 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret);
1478 dev_pm_opp_remove(hba->dev, clki->min_freq);
1479 dev_pm_opp_remove(hba->dev, clki->max_freq);
1483 hba->devfreq = devfreq;
1488 static void ufshcd_devfreq_remove(struct ufs_hba *hba)
1490 struct list_head *clk_list = &hba->clk_list_head;
1491 struct ufs_clk_info *clki;
1496 devfreq_remove_device(hba->devfreq);
1497 hba->devfreq = NULL;
1499 clki = list_first_entry(clk_list, struct ufs_clk_info, list);
1500 dev_pm_opp_remove(hba->dev, clki->min_freq);
1501 dev_pm_opp_remove(hba->dev, clki->max_freq);
1504 static void __ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1506 unsigned long flags;
1508 devfreq_suspend_device(hba->devfreq);
1509 spin_lock_irqsave(hba->host->host_lock, flags);
1510 hba->clk_scaling.window_start_t = 0;
1511 spin_unlock_irqrestore(hba->host->host_lock, flags);
1514 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba)
1516 unsigned long flags;
1517 bool suspend = false;
1519 cancel_work_sync(&hba->clk_scaling.suspend_work);
1520 cancel_work_sync(&hba->clk_scaling.resume_work);
1522 spin_lock_irqsave(hba->host->host_lock, flags);
1523 if (!hba->clk_scaling.is_suspended) {
1525 hba->clk_scaling.is_suspended = true;
1527 spin_unlock_irqrestore(hba->host->host_lock, flags);
1530 __ufshcd_suspend_clkscaling(hba);
1533 static void ufshcd_resume_clkscaling(struct ufs_hba *hba)
1535 unsigned long flags;
1536 bool resume = false;
1538 spin_lock_irqsave(hba->host->host_lock, flags);
1539 if (hba->clk_scaling.is_suspended) {
1541 hba->clk_scaling.is_suspended = false;
1543 spin_unlock_irqrestore(hba->host->host_lock, flags);
1546 devfreq_resume_device(hba->devfreq);
1549 static ssize_t ufshcd_clkscale_enable_show(struct device *dev,
1550 struct device_attribute *attr, char *buf)
1552 struct ufs_hba *hba = dev_get_drvdata(dev);
1554 return sysfs_emit(buf, "%d\n", hba->clk_scaling.is_enabled);
1557 static ssize_t ufshcd_clkscale_enable_store(struct device *dev,
1558 struct device_attribute *attr, const char *buf, size_t count)
1560 struct ufs_hba *hba = dev_get_drvdata(dev);
1564 if (kstrtou32(buf, 0, &value))
1567 down(&hba->host_sem);
1568 if (!ufshcd_is_user_access_allowed(hba)) {
1574 if (value == hba->clk_scaling.is_enabled)
1577 ufshcd_rpm_get_sync(hba);
1578 ufshcd_hold(hba, false);
1580 hba->clk_scaling.is_enabled = value;
1583 ufshcd_resume_clkscaling(hba);
1585 ufshcd_suspend_clkscaling(hba);
1586 err = ufshcd_devfreq_scale(hba, true);
1588 dev_err(hba->dev, "%s: failed to scale clocks up %d\n",
1592 ufshcd_release(hba);
1593 ufshcd_rpm_put_sync(hba);
1596 return err ? err : count;
1599 static void ufshcd_init_clk_scaling_sysfs(struct ufs_hba *hba)
1601 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show;
1602 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store;
1603 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr);
1604 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable";
1605 hba->clk_scaling.enable_attr.attr.mode = 0644;
1606 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr))
1607 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n");
1610 static void ufshcd_remove_clk_scaling_sysfs(struct ufs_hba *hba)
1612 if (hba->clk_scaling.enable_attr.attr.name)
1613 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr);
1616 static void ufshcd_init_clk_scaling(struct ufs_hba *hba)
1618 char wq_name[sizeof("ufs_clkscaling_00")];
1620 if (!ufshcd_is_clkscaling_supported(hba))
1623 if (!hba->clk_scaling.min_gear)
1624 hba->clk_scaling.min_gear = UFS_HS_G1;
1626 INIT_WORK(&hba->clk_scaling.suspend_work,
1627 ufshcd_clk_scaling_suspend_work);
1628 INIT_WORK(&hba->clk_scaling.resume_work,
1629 ufshcd_clk_scaling_resume_work);
1631 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d",
1632 hba->host->host_no);
1633 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name);
1635 hba->clk_scaling.is_initialized = true;
1638 static void ufshcd_exit_clk_scaling(struct ufs_hba *hba)
1640 if (!hba->clk_scaling.is_initialized)
1643 ufshcd_remove_clk_scaling_sysfs(hba);
1644 destroy_workqueue(hba->clk_scaling.workq);
1645 ufshcd_devfreq_remove(hba);
1646 hba->clk_scaling.is_initialized = false;
1649 static void ufshcd_ungate_work(struct work_struct *work)
1652 unsigned long flags;
1653 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1654 clk_gating.ungate_work);
1656 cancel_delayed_work_sync(&hba->clk_gating.gate_work);
1658 spin_lock_irqsave(hba->host->host_lock, flags);
1659 if (hba->clk_gating.state == CLKS_ON) {
1660 spin_unlock_irqrestore(hba->host->host_lock, flags);
1664 spin_unlock_irqrestore(hba->host->host_lock, flags);
1665 ufshcd_hba_vreg_set_hpm(hba);
1666 ufshcd_setup_clocks(hba, true);
1668 ufshcd_enable_irq(hba);
1670 /* Exit from hibern8 */
1671 if (ufshcd_can_hibern8_during_gating(hba)) {
1672 /* Prevent gating in this path */
1673 hba->clk_gating.is_suspended = true;
1674 if (ufshcd_is_link_hibern8(hba)) {
1675 ret = ufshcd_uic_hibern8_exit(hba);
1677 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
1680 ufshcd_set_link_active(hba);
1682 hba->clk_gating.is_suspended = false;
1685 ufshcd_scsi_unblock_requests(hba);
1689 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release.
1690 * Also, exit from hibern8 mode and set the link as active.
1691 * @hba: per adapter instance
1692 * @async: This indicates whether caller should ungate clocks asynchronously.
1694 int ufshcd_hold(struct ufs_hba *hba, bool async)
1698 unsigned long flags;
1700 if (!ufshcd_is_clkgating_allowed(hba) ||
1701 !hba->clk_gating.is_initialized)
1703 spin_lock_irqsave(hba->host->host_lock, flags);
1704 hba->clk_gating.active_reqs++;
1707 switch (hba->clk_gating.state) {
1710 * Wait for the ungate work to complete if in progress.
1711 * Though the clocks may be in ON state, the link could
1712 * still be in hibner8 state if hibern8 is allowed
1713 * during clock gating.
1714 * Make sure we exit hibern8 state also in addition to
1717 if (ufshcd_can_hibern8_during_gating(hba) &&
1718 ufshcd_is_link_hibern8(hba)) {
1721 hba->clk_gating.active_reqs--;
1724 spin_unlock_irqrestore(hba->host->host_lock, flags);
1725 flush_result = flush_work(&hba->clk_gating.ungate_work);
1726 if (hba->clk_gating.is_suspended && !flush_result)
1728 spin_lock_irqsave(hba->host->host_lock, flags);
1733 if (cancel_delayed_work(&hba->clk_gating.gate_work)) {
1734 hba->clk_gating.state = CLKS_ON;
1735 trace_ufshcd_clk_gating(dev_name(hba->dev),
1736 hba->clk_gating.state);
1740 * If we are here, it means gating work is either done or
1741 * currently running. Hence, fall through to cancel gating
1742 * work and to enable clocks.
1746 hba->clk_gating.state = REQ_CLKS_ON;
1747 trace_ufshcd_clk_gating(dev_name(hba->dev),
1748 hba->clk_gating.state);
1749 if (queue_work(hba->clk_gating.clk_gating_workq,
1750 &hba->clk_gating.ungate_work))
1751 ufshcd_scsi_block_requests(hba);
1753 * fall through to check if we should wait for this
1754 * work to be done or not.
1760 hba->clk_gating.active_reqs--;
1764 spin_unlock_irqrestore(hba->host->host_lock, flags);
1765 flush_work(&hba->clk_gating.ungate_work);
1766 /* Make sure state is CLKS_ON before returning */
1767 spin_lock_irqsave(hba->host->host_lock, flags);
1770 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n",
1771 __func__, hba->clk_gating.state);
1774 spin_unlock_irqrestore(hba->host->host_lock, flags);
1778 EXPORT_SYMBOL_GPL(ufshcd_hold);
1780 static void ufshcd_gate_work(struct work_struct *work)
1782 struct ufs_hba *hba = container_of(work, struct ufs_hba,
1783 clk_gating.gate_work.work);
1784 unsigned long flags;
1787 spin_lock_irqsave(hba->host->host_lock, flags);
1789 * In case you are here to cancel this work the gating state
1790 * would be marked as REQ_CLKS_ON. In this case save time by
1791 * skipping the gating work and exit after changing the clock
1794 if (hba->clk_gating.is_suspended ||
1795 (hba->clk_gating.state != REQ_CLKS_OFF)) {
1796 hba->clk_gating.state = CLKS_ON;
1797 trace_ufshcd_clk_gating(dev_name(hba->dev),
1798 hba->clk_gating.state);
1802 if (hba->clk_gating.active_reqs
1803 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL
1804 || hba->outstanding_reqs || hba->outstanding_tasks
1805 || hba->active_uic_cmd || hba->uic_async_done)
1808 spin_unlock_irqrestore(hba->host->host_lock, flags);
1810 /* put the link into hibern8 mode before turning off clocks */
1811 if (ufshcd_can_hibern8_during_gating(hba)) {
1812 ret = ufshcd_uic_hibern8_enter(hba);
1814 hba->clk_gating.state = CLKS_ON;
1815 dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
1817 trace_ufshcd_clk_gating(dev_name(hba->dev),
1818 hba->clk_gating.state);
1821 ufshcd_set_link_hibern8(hba);
1824 ufshcd_disable_irq(hba);
1826 ufshcd_setup_clocks(hba, false);
1828 /* Put the host controller in low power mode if possible */
1829 ufshcd_hba_vreg_set_lpm(hba);
1831 * In case you are here to cancel this work the gating state
1832 * would be marked as REQ_CLKS_ON. In this case keep the state
1833 * as REQ_CLKS_ON which would anyway imply that clocks are off
1834 * and a request to turn them on is pending. By doing this way,
1835 * we keep the state machine in tact and this would ultimately
1836 * prevent from doing cancel work multiple times when there are
1837 * new requests arriving before the current cancel work is done.
1839 spin_lock_irqsave(hba->host->host_lock, flags);
1840 if (hba->clk_gating.state == REQ_CLKS_OFF) {
1841 hba->clk_gating.state = CLKS_OFF;
1842 trace_ufshcd_clk_gating(dev_name(hba->dev),
1843 hba->clk_gating.state);
1846 spin_unlock_irqrestore(hba->host->host_lock, flags);
1851 /* host lock must be held before calling this variant */
1852 static void __ufshcd_release(struct ufs_hba *hba)
1854 if (!ufshcd_is_clkgating_allowed(hba))
1857 hba->clk_gating.active_reqs--;
1859 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended ||
1860 hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL ||
1861 hba->outstanding_tasks || !hba->clk_gating.is_initialized ||
1862 hba->active_uic_cmd || hba->uic_async_done ||
1863 hba->clk_gating.state == CLKS_OFF)
1866 hba->clk_gating.state = REQ_CLKS_OFF;
1867 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state);
1868 queue_delayed_work(hba->clk_gating.clk_gating_workq,
1869 &hba->clk_gating.gate_work,
1870 msecs_to_jiffies(hba->clk_gating.delay_ms));
1873 void ufshcd_release(struct ufs_hba *hba)
1875 unsigned long flags;
1877 spin_lock_irqsave(hba->host->host_lock, flags);
1878 __ufshcd_release(hba);
1879 spin_unlock_irqrestore(hba->host->host_lock, flags);
1881 EXPORT_SYMBOL_GPL(ufshcd_release);
1883 static ssize_t ufshcd_clkgate_delay_show(struct device *dev,
1884 struct device_attribute *attr, char *buf)
1886 struct ufs_hba *hba = dev_get_drvdata(dev);
1888 return sysfs_emit(buf, "%lu\n", hba->clk_gating.delay_ms);
1891 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value)
1893 struct ufs_hba *hba = dev_get_drvdata(dev);
1894 unsigned long flags;
1896 spin_lock_irqsave(hba->host->host_lock, flags);
1897 hba->clk_gating.delay_ms = value;
1898 spin_unlock_irqrestore(hba->host->host_lock, flags);
1900 EXPORT_SYMBOL_GPL(ufshcd_clkgate_delay_set);
1902 static ssize_t ufshcd_clkgate_delay_store(struct device *dev,
1903 struct device_attribute *attr, const char *buf, size_t count)
1905 unsigned long value;
1907 if (kstrtoul(buf, 0, &value))
1910 ufshcd_clkgate_delay_set(dev, value);
1914 static ssize_t ufshcd_clkgate_enable_show(struct device *dev,
1915 struct device_attribute *attr, char *buf)
1917 struct ufs_hba *hba = dev_get_drvdata(dev);
1919 return sysfs_emit(buf, "%d\n", hba->clk_gating.is_enabled);
1922 static ssize_t ufshcd_clkgate_enable_store(struct device *dev,
1923 struct device_attribute *attr, const char *buf, size_t count)
1925 struct ufs_hba *hba = dev_get_drvdata(dev);
1926 unsigned long flags;
1929 if (kstrtou32(buf, 0, &value))
1934 spin_lock_irqsave(hba->host->host_lock, flags);
1935 if (value == hba->clk_gating.is_enabled)
1939 __ufshcd_release(hba);
1941 hba->clk_gating.active_reqs++;
1943 hba->clk_gating.is_enabled = value;
1945 spin_unlock_irqrestore(hba->host->host_lock, flags);
1949 static void ufshcd_init_clk_gating_sysfs(struct ufs_hba *hba)
1951 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show;
1952 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store;
1953 sysfs_attr_init(&hba->clk_gating.delay_attr.attr);
1954 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms";
1955 hba->clk_gating.delay_attr.attr.mode = 0644;
1956 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr))
1957 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n");
1959 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show;
1960 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store;
1961 sysfs_attr_init(&hba->clk_gating.enable_attr.attr);
1962 hba->clk_gating.enable_attr.attr.name = "clkgate_enable";
1963 hba->clk_gating.enable_attr.attr.mode = 0644;
1964 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr))
1965 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n");
1968 static void ufshcd_remove_clk_gating_sysfs(struct ufs_hba *hba)
1970 if (hba->clk_gating.delay_attr.attr.name)
1971 device_remove_file(hba->dev, &hba->clk_gating.delay_attr);
1972 if (hba->clk_gating.enable_attr.attr.name)
1973 device_remove_file(hba->dev, &hba->clk_gating.enable_attr);
1976 static void ufshcd_init_clk_gating(struct ufs_hba *hba)
1978 char wq_name[sizeof("ufs_clk_gating_00")];
1980 if (!ufshcd_is_clkgating_allowed(hba))
1983 hba->clk_gating.state = CLKS_ON;
1985 hba->clk_gating.delay_ms = 150;
1986 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work);
1987 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work);
1989 snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d",
1990 hba->host->host_no);
1991 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name,
1992 WQ_MEM_RECLAIM | WQ_HIGHPRI);
1994 ufshcd_init_clk_gating_sysfs(hba);
1996 hba->clk_gating.is_enabled = true;
1997 hba->clk_gating.is_initialized = true;
2000 static void ufshcd_exit_clk_gating(struct ufs_hba *hba)
2002 if (!hba->clk_gating.is_initialized)
2005 ufshcd_remove_clk_gating_sysfs(hba);
2007 /* Ungate the clock if necessary. */
2008 ufshcd_hold(hba, false);
2009 hba->clk_gating.is_initialized = false;
2010 ufshcd_release(hba);
2012 destroy_workqueue(hba->clk_gating.clk_gating_workq);
2015 /* Must be called with host lock acquired */
2016 static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba)
2018 bool queue_resume_work = false;
2019 ktime_t curr_t = ktime_get();
2020 unsigned long flags;
2022 if (!ufshcd_is_clkscaling_supported(hba))
2025 spin_lock_irqsave(hba->host->host_lock, flags);
2026 if (!hba->clk_scaling.active_reqs++)
2027 queue_resume_work = true;
2029 if (!hba->clk_scaling.is_enabled || hba->pm_op_in_progress) {
2030 spin_unlock_irqrestore(hba->host->host_lock, flags);
2034 if (queue_resume_work)
2035 queue_work(hba->clk_scaling.workq,
2036 &hba->clk_scaling.resume_work);
2038 if (!hba->clk_scaling.window_start_t) {
2039 hba->clk_scaling.window_start_t = curr_t;
2040 hba->clk_scaling.tot_busy_t = 0;
2041 hba->clk_scaling.is_busy_started = false;
2044 if (!hba->clk_scaling.is_busy_started) {
2045 hba->clk_scaling.busy_start_t = curr_t;
2046 hba->clk_scaling.is_busy_started = true;
2048 spin_unlock_irqrestore(hba->host->host_lock, flags);
2051 static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba)
2053 struct ufs_clk_scaling *scaling = &hba->clk_scaling;
2054 unsigned long flags;
2056 if (!ufshcd_is_clkscaling_supported(hba))
2059 spin_lock_irqsave(hba->host->host_lock, flags);
2060 hba->clk_scaling.active_reqs--;
2061 if (!hba->outstanding_reqs && scaling->is_busy_started) {
2062 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(),
2063 scaling->busy_start_t));
2064 scaling->busy_start_t = 0;
2065 scaling->is_busy_started = false;
2067 spin_unlock_irqrestore(hba->host->host_lock, flags);
2070 static inline int ufshcd_monitor_opcode2dir(u8 opcode)
2072 if (opcode == READ_6 || opcode == READ_10 || opcode == READ_16)
2074 else if (opcode == WRITE_6 || opcode == WRITE_10 || opcode == WRITE_16)
2080 static inline bool ufshcd_should_inform_monitor(struct ufs_hba *hba,
2081 struct ufshcd_lrb *lrbp)
2083 struct ufs_hba_monitor *m = &hba->monitor;
2085 return (m->enabled && lrbp && lrbp->cmd &&
2086 (!m->chunk_size || m->chunk_size == lrbp->cmd->sdb.length) &&
2087 ktime_before(hba->monitor.enabled_ts, lrbp->issue_time_stamp));
2090 static void ufshcd_start_monitor(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2092 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
2093 unsigned long flags;
2095 spin_lock_irqsave(hba->host->host_lock, flags);
2096 if (dir >= 0 && hba->monitor.nr_queued[dir]++ == 0)
2097 hba->monitor.busy_start_ts[dir] = ktime_get();
2098 spin_unlock_irqrestore(hba->host->host_lock, flags);
2101 static void ufshcd_update_monitor(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2103 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd);
2104 unsigned long flags;
2106 spin_lock_irqsave(hba->host->host_lock, flags);
2107 if (dir >= 0 && hba->monitor.nr_queued[dir] > 0) {
2108 struct request *req = scsi_cmd_to_rq(lrbp->cmd);
2109 struct ufs_hba_monitor *m = &hba->monitor;
2110 ktime_t now, inc, lat;
2112 now = lrbp->compl_time_stamp;
2113 inc = ktime_sub(now, m->busy_start_ts[dir]);
2114 m->total_busy[dir] = ktime_add(m->total_busy[dir], inc);
2115 m->nr_sec_rw[dir] += blk_rq_sectors(req);
2117 /* Update latencies */
2119 lat = ktime_sub(now, lrbp->issue_time_stamp);
2120 m->lat_sum[dir] += lat;
2121 if (m->lat_max[dir] < lat || !m->lat_max[dir])
2122 m->lat_max[dir] = lat;
2123 if (m->lat_min[dir] > lat || !m->lat_min[dir])
2124 m->lat_min[dir] = lat;
2126 m->nr_queued[dir]--;
2127 /* Push forward the busy start of monitor */
2128 m->busy_start_ts[dir] = now;
2130 spin_unlock_irqrestore(hba->host->host_lock, flags);
2134 * ufshcd_send_command - Send SCSI or device management commands
2135 * @hba: per adapter instance
2136 * @task_tag: Task tag of the command
2139 void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
2141 struct ufshcd_lrb *lrbp = &hba->lrb[task_tag];
2142 unsigned long flags;
2144 lrbp->issue_time_stamp = ktime_get();
2145 lrbp->compl_time_stamp = ktime_set(0, 0);
2146 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_SEND);
2147 ufshcd_clk_scaling_start_busy(hba);
2148 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
2149 ufshcd_start_monitor(hba, lrbp);
2151 spin_lock_irqsave(&hba->outstanding_lock, flags);
2152 if (hba->vops && hba->vops->setup_xfer_req)
2153 hba->vops->setup_xfer_req(hba, task_tag, !!lrbp->cmd);
2154 __set_bit(task_tag, &hba->outstanding_reqs);
2155 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
2156 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
2160 * ufshcd_copy_sense_data - Copy sense data in case of check condition
2161 * @lrbp: pointer to local reference block
2163 static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
2165 u8 *const sense_buffer = lrbp->cmd->sense_buffer;
2169 ufshcd_get_rsp_upiu_data_seg_len(lrbp->ucd_rsp_ptr)) {
2172 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len);
2173 len_to_copy = min_t(int, UFS_SENSE_SIZE, len);
2175 memcpy(sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data,
2181 * ufshcd_copy_query_response() - Copy the Query Response and the data
2183 * @hba: per adapter instance
2184 * @lrbp: pointer to local reference block
2187 int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2189 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2191 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
2193 /* Get the descriptor */
2194 if (hba->dev_cmd.query.descriptor &&
2195 lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
2196 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr +
2197 GENERAL_UPIU_REQUEST_SIZE;
2201 /* data segment length */
2202 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
2203 MASK_QUERY_DATA_SEG_LEN;
2204 buf_len = be16_to_cpu(
2205 hba->dev_cmd.query.request.upiu_req.length);
2206 if (likely(buf_len >= resp_len)) {
2207 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
2210 "%s: rsp size %d is bigger than buffer size %d",
2211 __func__, resp_len, buf_len);
2220 * ufshcd_hba_capabilities - Read controller capabilities
2221 * @hba: per adapter instance
2223 * Return: 0 on success, negative on error.
2225 static inline int ufshcd_hba_capabilities(struct ufs_hba *hba)
2229 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
2231 /* nutrs and nutmrs are 0 based values */
2232 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
2234 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
2235 hba->reserved_slot = hba->nutrs - 1;
2237 /* Read crypto capabilities */
2238 err = ufshcd_hba_init_crypto_capabilities(hba);
2240 dev_err(hba->dev, "crypto setup failed\n");
2246 * ufshcd_ready_for_uic_cmd - Check if controller is ready
2247 * to accept UIC commands
2248 * @hba: per adapter instance
2249 * Return true on success, else false
2251 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
2253 return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY;
2257 * ufshcd_get_upmcrs - Get the power mode change request status
2258 * @hba: Pointer to adapter instance
2260 * This function gets the UPMCRS field of HCS register
2261 * Returns value of UPMCRS field
2263 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
2265 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
2269 * ufshcd_dispatch_uic_cmd - Dispatch an UIC command to the Unipro layer
2270 * @hba: per adapter instance
2271 * @uic_cmd: UIC command
2274 ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2276 lockdep_assert_held(&hba->uic_cmd_mutex);
2278 WARN_ON(hba->active_uic_cmd);
2280 hba->active_uic_cmd = uic_cmd;
2283 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
2284 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
2285 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
2287 ufshcd_add_uic_command_trace(hba, uic_cmd, UFS_CMD_SEND);
2290 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
2295 * ufshcd_wait_for_uic_cmd - Wait for completion of an UIC command
2296 * @hba: per adapter instance
2297 * @uic_cmd: UIC command
2299 * Returns 0 only if success.
2302 ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2305 unsigned long flags;
2307 lockdep_assert_held(&hba->uic_cmd_mutex);
2309 if (wait_for_completion_timeout(&uic_cmd->done,
2310 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
2311 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2315 "uic cmd 0x%x with arg3 0x%x completion timeout\n",
2316 uic_cmd->command, uic_cmd->argument3);
2318 if (!uic_cmd->cmd_active) {
2319 dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n",
2321 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT;
2325 spin_lock_irqsave(hba->host->host_lock, flags);
2326 hba->active_uic_cmd = NULL;
2327 spin_unlock_irqrestore(hba->host->host_lock, flags);
2333 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2334 * @hba: per adapter instance
2335 * @uic_cmd: UIC command
2336 * @completion: initialize the completion only if this is set to true
2338 * Returns 0 only if success.
2341 __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd,
2344 lockdep_assert_held(&hba->uic_cmd_mutex);
2345 lockdep_assert_held(hba->host->host_lock);
2347 if (!ufshcd_ready_for_uic_cmd(hba)) {
2349 "Controller not ready to accept UIC commands\n");
2354 init_completion(&uic_cmd->done);
2356 uic_cmd->cmd_active = 1;
2357 ufshcd_dispatch_uic_cmd(hba, uic_cmd);
2363 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result
2364 * @hba: per adapter instance
2365 * @uic_cmd: UIC command
2367 * Returns 0 only if success.
2369 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
2372 unsigned long flags;
2374 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD)
2377 ufshcd_hold(hba, false);
2378 mutex_lock(&hba->uic_cmd_mutex);
2379 ufshcd_add_delay_before_dme_cmd(hba);
2381 spin_lock_irqsave(hba->host->host_lock, flags);
2382 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true);
2383 spin_unlock_irqrestore(hba->host->host_lock, flags);
2385 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd);
2387 mutex_unlock(&hba->uic_cmd_mutex);
2389 ufshcd_release(hba);
2394 * ufshcd_map_sg - Map scatter-gather list to prdt
2395 * @hba: per adapter instance
2396 * @lrbp: pointer to local reference block
2398 * Returns 0 in case of success, non-zero value in case of failure
2400 static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2402 struct ufshcd_sg_entry *prd_table;
2403 struct scatterlist *sg;
2404 struct scsi_cmnd *cmd;
2409 sg_segments = scsi_dma_map(cmd);
2410 if (sg_segments < 0)
2415 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN)
2416 lrbp->utr_descriptor_ptr->prd_table_length =
2417 cpu_to_le16((sg_segments *
2418 sizeof(struct ufshcd_sg_entry)));
2420 lrbp->utr_descriptor_ptr->prd_table_length =
2421 cpu_to_le16(sg_segments);
2423 prd_table = lrbp->ucd_prdt_ptr;
2425 scsi_for_each_sg(cmd, sg, sg_segments, i) {
2426 const unsigned int len = sg_dma_len(sg);
2429 * From the UFSHCI spec: "Data Byte Count (DBC): A '0'
2430 * based value that indicates the length, in bytes, of
2431 * the data block. A maximum of length of 256KB may
2432 * exist for any entry. Bits 1:0 of this field shall be
2433 * 11b to indicate Dword granularity. A value of '3'
2434 * indicates 4 bytes, '7' indicates 8 bytes, etc."
2436 WARN_ONCE(len > 256 * 1024, "len = %#x\n", len);
2437 prd_table[i].size = cpu_to_le32(len - 1);
2438 prd_table[i].addr = cpu_to_le64(sg->dma_address);
2439 prd_table[i].reserved = 0;
2442 lrbp->utr_descriptor_ptr->prd_table_length = 0;
2449 * ufshcd_enable_intr - enable interrupts
2450 * @hba: per adapter instance
2451 * @intrs: interrupt bits
2453 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
2455 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2457 if (hba->ufs_version == ufshci_version(1, 0)) {
2459 rw = set & INTERRUPT_MASK_RW_VER_10;
2460 set = rw | ((set ^ intrs) & intrs);
2465 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2469 * ufshcd_disable_intr - disable interrupts
2470 * @hba: per adapter instance
2471 * @intrs: interrupt bits
2473 static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs)
2475 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
2477 if (hba->ufs_version == ufshci_version(1, 0)) {
2479 rw = (set & INTERRUPT_MASK_RW_VER_10) &
2480 ~(intrs & INTERRUPT_MASK_RW_VER_10);
2481 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10);
2487 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
2491 * ufshcd_prepare_req_desc_hdr() - Fills the requests header
2492 * descriptor according to request
2493 * @lrbp: pointer to local reference block
2494 * @upiu_flags: flags required in the header
2495 * @cmd_dir: requests data direction
2497 static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp,
2498 u8 *upiu_flags, enum dma_data_direction cmd_dir)
2500 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr;
2506 if (cmd_dir == DMA_FROM_DEVICE) {
2507 data_direction = UTP_DEVICE_TO_HOST;
2508 *upiu_flags = UPIU_CMD_FLAGS_READ;
2509 } else if (cmd_dir == DMA_TO_DEVICE) {
2510 data_direction = UTP_HOST_TO_DEVICE;
2511 *upiu_flags = UPIU_CMD_FLAGS_WRITE;
2513 data_direction = UTP_NO_DATA_TRANSFER;
2514 *upiu_flags = UPIU_CMD_FLAGS_NONE;
2517 dword_0 = data_direction | (lrbp->command_type
2518 << UPIU_COMMAND_TYPE_OFFSET);
2520 dword_0 |= UTP_REQ_DESC_INT_CMD;
2522 /* Prepare crypto related dwords */
2523 ufshcd_prepare_req_desc_hdr_crypto(lrbp, &dword_0, &dword_1, &dword_3);
2525 /* Transfer request descriptor header fields */
2526 req_desc->header.dword_0 = cpu_to_le32(dword_0);
2527 req_desc->header.dword_1 = cpu_to_le32(dword_1);
2529 * assigning invalid value for command status. Controller
2530 * updates OCS on command completion, with the command
2533 req_desc->header.dword_2 =
2534 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
2535 req_desc->header.dword_3 = cpu_to_le32(dword_3);
2537 req_desc->prd_table_length = 0;
2541 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc,
2543 * @lrbp: local reference block pointer
2544 * @upiu_flags: flags
2547 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8 upiu_flags)
2549 struct scsi_cmnd *cmd = lrbp->cmd;
2550 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2551 unsigned short cdb_len;
2553 /* command descriptor fields */
2554 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2555 UPIU_TRANSACTION_COMMAND, upiu_flags,
2556 lrbp->lun, lrbp->task_tag);
2557 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2558 UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
2560 /* Total EHS length and Data segment length will be zero */
2561 ucd_req_ptr->header.dword_2 = 0;
2563 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length);
2565 cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE);
2566 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE);
2567 memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len);
2569 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2573 * ufshcd_prepare_utp_query_req_upiu() - fills the utp_transfer_req_desc,
2576 * @lrbp: local reference block pointer
2577 * @upiu_flags: flags
2579 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
2580 struct ufshcd_lrb *lrbp, u8 upiu_flags)
2582 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2583 struct ufs_query *query = &hba->dev_cmd.query;
2584 u16 len = be16_to_cpu(query->request.upiu_req.length);
2586 /* Query request header */
2587 ucd_req_ptr->header.dword_0 = UPIU_HEADER_DWORD(
2588 UPIU_TRANSACTION_QUERY_REQ, upiu_flags,
2589 lrbp->lun, lrbp->task_tag);
2590 ucd_req_ptr->header.dword_1 = UPIU_HEADER_DWORD(
2591 0, query->request.query_func, 0, 0);
2593 /* Data segment length only need for WRITE_DESC */
2594 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2595 ucd_req_ptr->header.dword_2 =
2596 UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
2598 ucd_req_ptr->header.dword_2 = 0;
2600 /* Copy the Query Request buffer as is */
2601 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req,
2604 /* Copy the Descriptor */
2605 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
2606 memcpy(ucd_req_ptr + 1, query->descriptor, len);
2608 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2611 static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp)
2613 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr;
2615 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
2617 /* command descriptor fields */
2618 ucd_req_ptr->header.dword_0 =
2620 UPIU_TRANSACTION_NOP_OUT, 0, 0, lrbp->task_tag);
2621 /* clear rest of the fields of basic header */
2622 ucd_req_ptr->header.dword_1 = 0;
2623 ucd_req_ptr->header.dword_2 = 0;
2625 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
2629 * ufshcd_compose_devman_upiu - UFS Protocol Information Unit(UPIU)
2630 * for Device Management Purposes
2631 * @hba: per adapter instance
2632 * @lrbp: pointer to local reference block
2634 static int ufshcd_compose_devman_upiu(struct ufs_hba *hba,
2635 struct ufshcd_lrb *lrbp)
2640 if (hba->ufs_version <= ufshci_version(1, 1))
2641 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
2643 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2645 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
2646 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY)
2647 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags);
2648 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP)
2649 ufshcd_prepare_utp_nop_upiu(lrbp);
2657 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU)
2659 * @hba: per adapter instance
2660 * @lrbp: pointer to local reference block
2662 static int ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2667 if (hba->ufs_version <= ufshci_version(1, 1))
2668 lrbp->command_type = UTP_CMD_TYPE_SCSI;
2670 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
2672 if (likely(lrbp->cmd)) {
2673 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags,
2674 lrbp->cmd->sc_data_direction);
2675 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags);
2684 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID
2685 * @upiu_wlun_id: UPIU W-LUN id
2687 * Returns SCSI W-LUN id
2689 static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id)
2691 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE;
2694 static inline bool is_device_wlun(struct scsi_device *sdev)
2697 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN);
2701 * Associate the UFS controller queue with the default and poll HCTX types.
2702 * Initialize the mq_map[] arrays.
2704 static int ufshcd_map_queues(struct Scsi_Host *shost)
2708 for (i = 0; i < shost->nr_maps; i++) {
2709 struct blk_mq_queue_map *map = &shost->tag_set.map[i];
2712 case HCTX_TYPE_DEFAULT:
2713 case HCTX_TYPE_POLL:
2716 case HCTX_TYPE_READ:
2722 map->queue_offset = 0;
2723 ret = blk_mq_map_queues(map);
2730 static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i)
2732 struct utp_transfer_cmd_desc *cmd_descp = hba->ucdl_base_addr;
2733 struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr;
2734 dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr +
2735 i * sizeof(struct utp_transfer_cmd_desc);
2736 u16 response_offset = offsetof(struct utp_transfer_cmd_desc,
2738 u16 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table);
2740 lrb->utr_descriptor_ptr = utrdlp + i;
2741 lrb->utrd_dma_addr = hba->utrdl_dma_addr +
2742 i * sizeof(struct utp_transfer_req_desc);
2743 lrb->ucd_req_ptr = (struct utp_upiu_req *)(cmd_descp + i);
2744 lrb->ucd_req_dma_addr = cmd_desc_element_addr;
2745 lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
2746 lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset;
2747 lrb->ucd_prdt_ptr = cmd_descp[i].prd_table;
2748 lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset;
2752 * ufshcd_queuecommand - main entry point for SCSI requests
2753 * @host: SCSI host pointer
2754 * @cmd: command from SCSI Midlayer
2756 * Returns 0 for success, non-zero in case of failure
2758 static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
2760 struct ufs_hba *hba = shost_priv(host);
2761 int tag = scsi_cmd_to_rq(cmd)->tag;
2762 struct ufshcd_lrb *lrbp;
2765 WARN_ONCE(tag < 0 || tag >= hba->nutrs, "Invalid tag %d\n", tag);
2768 * Allows the UFS error handler to wait for prior ufshcd_queuecommand()
2773 switch (hba->ufshcd_state) {
2774 case UFSHCD_STATE_OPERATIONAL:
2776 case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL:
2778 * SCSI error handler can call ->queuecommand() while UFS error
2779 * handler is in progress. Error interrupts could change the
2780 * state from UFSHCD_STATE_RESET to
2781 * UFSHCD_STATE_EH_SCHEDULED_NON_FATAL. Prevent requests
2782 * being issued in that case.
2784 if (ufshcd_eh_in_progress(hba)) {
2785 err = SCSI_MLQUEUE_HOST_BUSY;
2789 case UFSHCD_STATE_EH_SCHEDULED_FATAL:
2791 * pm_runtime_get_sync() is used at error handling preparation
2792 * stage. If a scsi cmd, e.g. the SSU cmd, is sent from hba's
2793 * PM ops, it can never be finished if we let SCSI layer keep
2794 * retrying it, which gets err handler stuck forever. Neither
2795 * can we let the scsi cmd pass through, because UFS is in bad
2796 * state, the scsi cmd may eventually time out, which will get
2797 * err handler blocked for too long. So, just fail the scsi cmd
2798 * sent from PM ops, err handler can recover PM error anyways.
2800 if (hba->pm_op_in_progress) {
2801 hba->force_reset = true;
2802 set_host_byte(cmd, DID_BAD_TARGET);
2807 case UFSHCD_STATE_RESET:
2808 err = SCSI_MLQUEUE_HOST_BUSY;
2810 case UFSHCD_STATE_ERROR:
2811 set_host_byte(cmd, DID_ERROR);
2816 hba->req_abort_count = 0;
2818 err = ufshcd_hold(hba, true);
2820 err = SCSI_MLQUEUE_HOST_BUSY;
2823 WARN_ON(ufshcd_is_clkgating_allowed(hba) &&
2824 (hba->clk_gating.state != CLKS_ON));
2826 lrbp = &hba->lrb[tag];
2829 lrbp->task_tag = tag;
2830 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
2831 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba);
2833 ufshcd_prepare_lrbp_crypto(scsi_cmd_to_rq(cmd), lrbp);
2835 lrbp->req_abort_skip = false;
2837 ufshpb_prep(hba, lrbp);
2839 ufshcd_comp_scsi_upiu(hba, lrbp);
2841 err = ufshcd_map_sg(hba, lrbp);
2844 ufshcd_release(hba);
2848 ufshcd_send_command(hba, tag);
2853 if (ufs_trigger_eh()) {
2854 unsigned long flags;
2856 spin_lock_irqsave(hba->host->host_lock, flags);
2857 ufshcd_schedule_eh_work(hba);
2858 spin_unlock_irqrestore(hba->host->host_lock, flags);
2864 static int ufshcd_compose_dev_cmd(struct ufs_hba *hba,
2865 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag)
2868 lrbp->task_tag = tag;
2869 lrbp->lun = 0; /* device management cmd is not specific to any LUN */
2870 lrbp->intr_cmd = true; /* No interrupt aggregation */
2871 ufshcd_prepare_lrbp_crypto(NULL, lrbp);
2872 hba->dev_cmd.type = cmd_type;
2874 return ufshcd_compose_devman_upiu(hba, lrbp);
2878 * Clear all the requests from the controller for which a bit has been set in
2879 * @mask and wait until the controller confirms that these requests have been
2882 static int ufshcd_clear_cmds(struct ufs_hba *hba, u32 mask)
2884 unsigned long flags;
2886 /* clear outstanding transaction before retry */
2887 spin_lock_irqsave(hba->host->host_lock, flags);
2888 ufshcd_utrl_clear(hba, mask);
2889 spin_unlock_irqrestore(hba->host->host_lock, flags);
2892 * wait for h/w to clear corresponding bit in door-bell.
2893 * max. wait is 1 sec.
2895 return ufshcd_wait_for_register(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL,
2896 mask, ~mask, 1000, 1000);
2900 ufshcd_check_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2902 struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
2904 /* Get the UPIU response */
2905 query_res->response = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr) >>
2906 UPIU_RSP_CODE_OFFSET;
2907 return query_res->response;
2911 * ufshcd_dev_cmd_completion() - handles device management command responses
2912 * @hba: per adapter instance
2913 * @lrbp: pointer to local reference block
2916 ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
2921 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
2922 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
2925 case UPIU_TRANSACTION_NOP_IN:
2926 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) {
2928 dev_err(hba->dev, "%s: unexpected response %x\n",
2932 case UPIU_TRANSACTION_QUERY_RSP:
2933 err = ufshcd_check_query_response(hba, lrbp);
2935 err = ufshcd_copy_query_response(hba, lrbp);
2937 case UPIU_TRANSACTION_REJECT_UPIU:
2938 /* TODO: handle Reject UPIU Response */
2940 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
2945 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
2953 static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba,
2954 struct ufshcd_lrb *lrbp, int max_timeout)
2956 unsigned long time_left = msecs_to_jiffies(max_timeout);
2957 unsigned long flags;
2962 time_left = wait_for_completion_timeout(hba->dev_cmd.complete,
2965 if (likely(time_left)) {
2967 * The completion handler called complete() and the caller of
2968 * this function still owns the @lrbp tag so the code below does
2969 * not trigger any race conditions.
2971 hba->dev_cmd.complete = NULL;
2972 err = ufshcd_get_tr_ocs(lrbp);
2974 err = ufshcd_dev_cmd_completion(hba, lrbp);
2977 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n",
2978 __func__, lrbp->task_tag);
2979 if (ufshcd_clear_cmds(hba, 1U << lrbp->task_tag) == 0) {
2980 /* successfully cleared the command, retry if needed */
2983 * Since clearing the command succeeded we also need to
2984 * clear the task tag bit from the outstanding_reqs
2987 spin_lock_irqsave(&hba->outstanding_lock, flags);
2988 pending = test_bit(lrbp->task_tag,
2989 &hba->outstanding_reqs);
2991 hba->dev_cmd.complete = NULL;
2992 __clear_bit(lrbp->task_tag,
2993 &hba->outstanding_reqs);
2995 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
2999 * The completion handler ran while we tried to
3000 * clear the command.
3006 dev_err(hba->dev, "%s: failed to clear tag %d\n",
3007 __func__, lrbp->task_tag);
3015 * ufshcd_exec_dev_cmd - API for sending device management requests
3017 * @cmd_type: specifies the type (NOP, Query...)
3018 * @timeout: timeout in milliseconds
3020 * NOTE: Since there is only one available tag for device management commands,
3021 * it is expected you hold the hba->dev_cmd.lock mutex.
3023 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba,
3024 enum dev_cmd_type cmd_type, int timeout)
3026 DECLARE_COMPLETION_ONSTACK(wait);
3027 const u32 tag = hba->reserved_slot;
3028 struct ufshcd_lrb *lrbp;
3031 /* Protects use of hba->reserved_slot. */
3032 lockdep_assert_held(&hba->dev_cmd.lock);
3034 down_read(&hba->clk_scaling_lock);
3036 lrbp = &hba->lrb[tag];
3038 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag);
3042 hba->dev_cmd.complete = &wait;
3044 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr);
3046 ufshcd_send_command(hba, tag);
3047 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout);
3048 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP,
3049 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
3052 up_read(&hba->clk_scaling_lock);
3057 * ufshcd_init_query() - init the query response and request parameters
3058 * @hba: per-adapter instance
3059 * @request: address of the request pointer to be initialized
3060 * @response: address of the response pointer to be initialized
3061 * @opcode: operation to perform
3062 * @idn: flag idn to access
3063 * @index: LU number to access
3064 * @selector: query/flag/descriptor further identification
3066 static inline void ufshcd_init_query(struct ufs_hba *hba,
3067 struct ufs_query_req **request, struct ufs_query_res **response,
3068 enum query_opcode opcode, u8 idn, u8 index, u8 selector)
3070 *request = &hba->dev_cmd.query.request;
3071 *response = &hba->dev_cmd.query.response;
3072 memset(*request, 0, sizeof(struct ufs_query_req));
3073 memset(*response, 0, sizeof(struct ufs_query_res));
3074 (*request)->upiu_req.opcode = opcode;
3075 (*request)->upiu_req.idn = idn;
3076 (*request)->upiu_req.index = index;
3077 (*request)->upiu_req.selector = selector;
3080 static int ufshcd_query_flag_retry(struct ufs_hba *hba,
3081 enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res)
3086 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
3087 ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res);
3090 "%s: failed with error %d, retries %d\n",
3091 __func__, ret, retries);
3098 "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
3099 __func__, opcode, idn, ret, retries);
3104 * ufshcd_query_flag() - API function for sending flag query requests
3105 * @hba: per-adapter instance
3106 * @opcode: flag query to perform
3107 * @idn: flag idn to access
3108 * @index: flag index to access
3109 * @flag_res: the flag value after the query request completes
3111 * Returns 0 for success, non-zero in case of failure
3113 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
3114 enum flag_idn idn, u8 index, bool *flag_res)
3116 struct ufs_query_req *request = NULL;
3117 struct ufs_query_res *response = NULL;
3118 int err, selector = 0;
3119 int timeout = QUERY_REQ_TIMEOUT;
3123 ufshcd_hold(hba, false);
3124 mutex_lock(&hba->dev_cmd.lock);
3125 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3129 case UPIU_QUERY_OPCODE_SET_FLAG:
3130 case UPIU_QUERY_OPCODE_CLEAR_FLAG:
3131 case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
3132 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3134 case UPIU_QUERY_OPCODE_READ_FLAG:
3135 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3137 /* No dummy reads */
3138 dev_err(hba->dev, "%s: Invalid argument for read request\n",
3146 "%s: Expected query flag opcode but got = %d\n",
3152 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
3156 "%s: Sending flag query for idn %d failed, err = %d\n",
3157 __func__, idn, err);
3162 *flag_res = (be32_to_cpu(response->upiu_res.value) &
3163 MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
3166 mutex_unlock(&hba->dev_cmd.lock);
3167 ufshcd_release(hba);
3172 * ufshcd_query_attr - API function for sending attribute requests
3173 * @hba: per-adapter instance
3174 * @opcode: attribute opcode
3175 * @idn: attribute idn to access
3176 * @index: index field
3177 * @selector: selector field
3178 * @attr_val: the attribute value after the query request completes
3180 * Returns 0 for success, non-zero in case of failure
3182 int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode,
3183 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val)
3185 struct ufs_query_req *request = NULL;
3186 struct ufs_query_res *response = NULL;
3192 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n",
3197 ufshcd_hold(hba, false);
3199 mutex_lock(&hba->dev_cmd.lock);
3200 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3204 case UPIU_QUERY_OPCODE_WRITE_ATTR:
3205 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3206 request->upiu_req.value = cpu_to_be32(*attr_val);
3208 case UPIU_QUERY_OPCODE_READ_ATTR:
3209 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3212 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n",
3218 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
3221 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3222 __func__, opcode, idn, index, err);
3226 *attr_val = be32_to_cpu(response->upiu_res.value);
3229 mutex_unlock(&hba->dev_cmd.lock);
3230 ufshcd_release(hba);
3235 * ufshcd_query_attr_retry() - API function for sending query
3236 * attribute with retries
3237 * @hba: per-adapter instance
3238 * @opcode: attribute opcode
3239 * @idn: attribute idn to access
3240 * @index: index field
3241 * @selector: selector field
3242 * @attr_val: the attribute value after the query request
3245 * Returns 0 for success, non-zero in case of failure
3247 int ufshcd_query_attr_retry(struct ufs_hba *hba,
3248 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector,
3254 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3255 ret = ufshcd_query_attr(hba, opcode, idn, index,
3256 selector, attr_val);
3258 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n",
3259 __func__, ret, retries);
3266 "%s: query attribute, idn %d, failed with error %d after %d retires\n",
3267 __func__, idn, ret, QUERY_REQ_RETRIES);
3271 static int __ufshcd_query_descriptor(struct ufs_hba *hba,
3272 enum query_opcode opcode, enum desc_idn idn, u8 index,
3273 u8 selector, u8 *desc_buf, int *buf_len)
3275 struct ufs_query_req *request = NULL;
3276 struct ufs_query_res *response = NULL;
3282 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
3287 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
3288 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
3289 __func__, *buf_len);
3293 ufshcd_hold(hba, false);
3295 mutex_lock(&hba->dev_cmd.lock);
3296 ufshcd_init_query(hba, &request, &response, opcode, idn, index,
3298 hba->dev_cmd.query.descriptor = desc_buf;
3299 request->upiu_req.length = cpu_to_be16(*buf_len);
3302 case UPIU_QUERY_OPCODE_WRITE_DESC:
3303 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
3305 case UPIU_QUERY_OPCODE_READ_DESC:
3306 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
3310 "%s: Expected query descriptor opcode but got = 0x%.2x\n",
3316 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
3319 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
3320 __func__, opcode, idn, index, err);
3324 *buf_len = be16_to_cpu(response->upiu_res.length);
3327 hba->dev_cmd.query.descriptor = NULL;
3328 mutex_unlock(&hba->dev_cmd.lock);
3329 ufshcd_release(hba);
3334 * ufshcd_query_descriptor_retry - API function for sending descriptor requests
3335 * @hba: per-adapter instance
3336 * @opcode: attribute opcode
3337 * @idn: attribute idn to access
3338 * @index: index field
3339 * @selector: selector field
3340 * @desc_buf: the buffer that contains the descriptor
3341 * @buf_len: length parameter passed to the device
3343 * Returns 0 for success, non-zero in case of failure.
3344 * The buf_len parameter will contain, on return, the length parameter
3345 * received on the response.
3347 int ufshcd_query_descriptor_retry(struct ufs_hba *hba,
3348 enum query_opcode opcode,
3349 enum desc_idn idn, u8 index,
3351 u8 *desc_buf, int *buf_len)
3356 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
3357 err = __ufshcd_query_descriptor(hba, opcode, idn, index,
3358 selector, desc_buf, buf_len);
3359 if (!err || err == -EINVAL)
3367 * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
3368 * @hba: Pointer to adapter instance
3369 * @desc_id: descriptor idn value
3370 * @desc_len: mapped desc length (out)
3372 void ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id,
3375 if (desc_id >= QUERY_DESC_IDN_MAX || desc_id == QUERY_DESC_IDN_RFU_0 ||
3376 desc_id == QUERY_DESC_IDN_RFU_1)
3379 *desc_len = hba->desc_size[desc_id];
3381 EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
3383 static void ufshcd_update_desc_length(struct ufs_hba *hba,
3384 enum desc_idn desc_id, int desc_index,
3385 unsigned char desc_len)
3387 if (hba->desc_size[desc_id] == QUERY_DESC_MAX_SIZE &&
3388 desc_id != QUERY_DESC_IDN_STRING && desc_index != UFS_RPMB_UNIT)
3389 /* For UFS 3.1, the normal unit descriptor is 10 bytes larger
3390 * than the RPMB unit, however, both descriptors share the same
3391 * desc_idn, to cover both unit descriptors with one length, we
3392 * choose the normal unit descriptor length by desc_index.
3394 hba->desc_size[desc_id] = desc_len;
3398 * ufshcd_read_desc_param - read the specified descriptor parameter
3399 * @hba: Pointer to adapter instance
3400 * @desc_id: descriptor idn value
3401 * @desc_index: descriptor index
3402 * @param_offset: offset of the parameter to read
3403 * @param_read_buf: pointer to buffer where parameter would be read
3404 * @param_size: sizeof(param_read_buf)
3406 * Return 0 in case of success, non-zero otherwise
3408 int ufshcd_read_desc_param(struct ufs_hba *hba,
3409 enum desc_idn desc_id,
3418 bool is_kmalloc = true;
3421 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
3424 /* Get the length of descriptor */
3425 ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
3427 dev_err(hba->dev, "%s: Failed to get desc length\n", __func__);
3431 if (param_offset >= buff_len) {
3432 dev_err(hba->dev, "%s: Invalid offset 0x%x in descriptor IDN 0x%x, length 0x%x\n",
3433 __func__, param_offset, desc_id, buff_len);
3437 /* Check whether we need temp memory */
3438 if (param_offset != 0 || param_size < buff_len) {
3439 desc_buf = kzalloc(buff_len, GFP_KERNEL);
3443 desc_buf = param_read_buf;
3447 /* Request for full descriptor */
3448 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
3449 desc_id, desc_index, 0,
3450 desc_buf, &buff_len);
3453 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n",
3454 __func__, desc_id, desc_index, param_offset, ret);
3459 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
3460 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n",
3461 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
3466 /* Update descriptor length */
3467 buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET];
3468 ufshcd_update_desc_length(hba, desc_id, desc_index, buff_len);
3471 /* Make sure we don't copy more data than available */
3472 if (param_offset >= buff_len)
3475 memcpy(param_read_buf, &desc_buf[param_offset],
3476 min_t(u32, param_size, buff_len - param_offset));
3485 * struct uc_string_id - unicode string
3487 * @len: size of this descriptor inclusive
3488 * @type: descriptor type
3489 * @uc: unicode string character
3491 struct uc_string_id {
3497 /* replace non-printable or non-ASCII characters with spaces */
3498 static inline char ufshcd_remove_non_printable(u8 ch)
3500 return (ch >= 0x20 && ch <= 0x7e) ? ch : ' ';
3504 * ufshcd_read_string_desc - read string descriptor
3505 * @hba: pointer to adapter instance
3506 * @desc_index: descriptor index
3507 * @buf: pointer to buffer where descriptor would be read,
3508 * the caller should free the memory.
3509 * @ascii: if true convert from unicode to ascii characters
3510 * null terminated string.
3513 * * string size on success.
3514 * * -ENOMEM: on allocation failure
3515 * * -EINVAL: on a wrong parameter
3517 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
3518 u8 **buf, bool ascii)
3520 struct uc_string_id *uc_str;
3527 uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
3531 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0,
3532 (u8 *)uc_str, QUERY_DESC_MAX_SIZE);
3534 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n",
3535 QUERY_REQ_RETRIES, ret);
3540 if (uc_str->len <= QUERY_DESC_HDR_SIZE) {
3541 dev_dbg(hba->dev, "String Desc is of zero length\n");
3550 /* remove header and divide by 2 to move from UTF16 to UTF8 */
3551 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1;
3552 str = kzalloc(ascii_len, GFP_KERNEL);
3559 * the descriptor contains string in UTF16 format
3560 * we need to convert to utf-8 so it can be displayed
3562 ret = utf16s_to_utf8s(uc_str->uc,
3563 uc_str->len - QUERY_DESC_HDR_SIZE,
3564 UTF16_BIG_ENDIAN, str, ascii_len);
3566 /* replace non-printable or non-ASCII characters with spaces */
3567 for (i = 0; i < ret; i++)
3568 str[i] = ufshcd_remove_non_printable(str[i]);
3573 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL);
3587 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter
3588 * @hba: Pointer to adapter instance
3590 * @param_offset: offset of the parameter to read
3591 * @param_read_buf: pointer to buffer where parameter would be read
3592 * @param_size: sizeof(param_read_buf)
3594 * Return 0 in case of success, non-zero otherwise
3596 static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba,
3598 enum unit_desc_param param_offset,
3603 * Unit descriptors are only available for general purpose LUs (LUN id
3604 * from 0 to 7) and RPMB Well known LU.
3606 if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun, param_offset))
3609 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun,
3610 param_offset, param_read_buf, param_size);
3613 static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba)
3616 u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3618 if (hba->dev_info.wspecversion >= 0x300) {
3619 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
3620 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0,
3623 dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n",
3626 if (gating_wait == 0) {
3627 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US;
3628 dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n",
3632 hba->dev_info.clk_gating_wait_us = gating_wait;
3639 * ufshcd_memory_alloc - allocate memory for host memory space data structures
3640 * @hba: per adapter instance
3642 * 1. Allocate DMA memory for Command Descriptor array
3643 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
3644 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
3645 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
3647 * 4. Allocate memory for local reference block(lrb).
3649 * Returns 0 for success, non-zero in case of failure
3651 static int ufshcd_memory_alloc(struct ufs_hba *hba)
3653 size_t utmrdl_size, utrdl_size, ucdl_size;
3655 /* Allocate memory for UTP command descriptors */
3656 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
3657 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev,
3659 &hba->ucdl_dma_addr,
3663 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
3664 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
3665 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
3666 * be aligned to 128 bytes as well
3668 if (!hba->ucdl_base_addr ||
3669 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
3671 "Command Descriptor Memory allocation failed\n");
3676 * Allocate memory for UTP Transfer descriptors
3677 * UFSHCI requires 1024 byte alignment of UTRD
3679 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
3680 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev,
3682 &hba->utrdl_dma_addr,
3684 if (!hba->utrdl_base_addr ||
3685 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
3687 "Transfer Descriptor Memory allocation failed\n");
3692 * Allocate memory for UTP Task Management descriptors
3693 * UFSHCI requires 1024 byte alignment of UTMRD
3695 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
3696 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev,
3698 &hba->utmrdl_dma_addr,
3700 if (!hba->utmrdl_base_addr ||
3701 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
3703 "Task Management Descriptor Memory allocation failed\n");
3707 /* Allocate memory for local reference block */
3708 hba->lrb = devm_kcalloc(hba->dev,
3709 hba->nutrs, sizeof(struct ufshcd_lrb),
3712 dev_err(hba->dev, "LRB Memory allocation failed\n");
3721 * ufshcd_host_memory_configure - configure local reference block with
3723 * @hba: per adapter instance
3725 * Configure Host memory space
3726 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
3728 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
3730 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
3731 * into local reference block.
3733 static void ufshcd_host_memory_configure(struct ufs_hba *hba)
3735 struct utp_transfer_req_desc *utrdlp;
3736 dma_addr_t cmd_desc_dma_addr;
3737 dma_addr_t cmd_desc_element_addr;
3738 u16 response_offset;
3743 utrdlp = hba->utrdl_base_addr;
3746 offsetof(struct utp_transfer_cmd_desc, response_upiu);
3748 offsetof(struct utp_transfer_cmd_desc, prd_table);
3750 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
3751 cmd_desc_dma_addr = hba->ucdl_dma_addr;
3753 for (i = 0; i < hba->nutrs; i++) {
3754 /* Configure UTRD with command descriptor base address */
3755 cmd_desc_element_addr =
3756 (cmd_desc_dma_addr + (cmd_desc_size * i));
3757 utrdlp[i].command_desc_base_addr_lo =
3758 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
3759 utrdlp[i].command_desc_base_addr_hi =
3760 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
3762 /* Response upiu and prdt offset should be in double words */
3763 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) {
3764 utrdlp[i].response_upiu_offset =
3765 cpu_to_le16(response_offset);
3766 utrdlp[i].prd_table_offset =
3767 cpu_to_le16(prdt_offset);
3768 utrdlp[i].response_upiu_length =
3769 cpu_to_le16(ALIGNED_UPIU_SIZE);
3771 utrdlp[i].response_upiu_offset =
3772 cpu_to_le16(response_offset >> 2);
3773 utrdlp[i].prd_table_offset =
3774 cpu_to_le16(prdt_offset >> 2);
3775 utrdlp[i].response_upiu_length =
3776 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
3779 ufshcd_init_lrb(hba, &hba->lrb[i], i);
3784 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
3785 * @hba: per adapter instance
3787 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
3788 * in order to initialize the Unipro link startup procedure.
3789 * Once the Unipro links are up, the device connected to the controller
3792 * Returns 0 on success, non-zero value on failure
3794 static int ufshcd_dme_link_startup(struct ufs_hba *hba)
3796 struct uic_command uic_cmd = {0};
3799 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
3801 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3804 "dme-link-startup: error code %d\n", ret);
3808 * ufshcd_dme_reset - UIC command for DME_RESET
3809 * @hba: per adapter instance
3811 * DME_RESET command is issued in order to reset UniPro stack.
3812 * This function now deals with cold reset.
3814 * Returns 0 on success, non-zero value on failure
3816 static int ufshcd_dme_reset(struct ufs_hba *hba)
3818 struct uic_command uic_cmd = {0};
3821 uic_cmd.command = UIC_CMD_DME_RESET;
3823 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3826 "dme-reset: error code %d\n", ret);
3831 int ufshcd_dme_configure_adapt(struct ufs_hba *hba,
3837 if (agreed_gear != UFS_HS_G4)
3838 adapt_val = PA_NO_ADAPT;
3840 ret = ufshcd_dme_set(hba,
3841 UIC_ARG_MIB(PA_TXHSADAPTTYPE),
3845 EXPORT_SYMBOL_GPL(ufshcd_dme_configure_adapt);
3848 * ufshcd_dme_enable - UIC command for DME_ENABLE
3849 * @hba: per adapter instance
3851 * DME_ENABLE command is issued in order to enable UniPro stack.
3853 * Returns 0 on success, non-zero value on failure
3855 static int ufshcd_dme_enable(struct ufs_hba *hba)
3857 struct uic_command uic_cmd = {0};
3860 uic_cmd.command = UIC_CMD_DME_ENABLE;
3862 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3865 "dme-enable: error code %d\n", ret);
3870 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
3872 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000
3873 unsigned long min_sleep_time_us;
3875 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS))
3879 * last_dme_cmd_tstamp will be 0 only for 1st call to
3882 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) {
3883 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US;
3885 unsigned long delta =
3886 (unsigned long) ktime_to_us(
3887 ktime_sub(ktime_get(),
3888 hba->last_dme_cmd_tstamp));
3890 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US)
3892 MIN_DELAY_BEFORE_DME_CMDS_US - delta;
3894 return; /* no more delay required */
3897 /* allow sleep for extra 50us if needed */
3898 usleep_range(min_sleep_time_us, min_sleep_time_us + 50);
3902 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
3903 * @hba: per adapter instance
3904 * @attr_sel: uic command argument1
3905 * @attr_set: attribute set type as uic command argument2
3906 * @mib_val: setting value as uic command argument3
3907 * @peer: indicate whether peer or local
3909 * Returns 0 on success, non-zero value on failure
3911 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
3912 u8 attr_set, u32 mib_val, u8 peer)
3914 struct uic_command uic_cmd = {0};
3915 static const char *const action[] = {
3919 const char *set = action[!!peer];
3921 int retries = UFS_UIC_COMMAND_RETRIES;
3923 uic_cmd.command = peer ?
3924 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
3925 uic_cmd.argument1 = attr_sel;
3926 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
3927 uic_cmd.argument3 = mib_val;
3930 /* for peer attributes we retry upon failure */
3931 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
3933 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
3934 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
3935 } while (ret && peer && --retries);
3938 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
3939 set, UIC_GET_ATTR_ID(attr_sel), mib_val,
3940 UFS_UIC_COMMAND_RETRIES - retries);
3944 EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr);
3947 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
3948 * @hba: per adapter instance
3949 * @attr_sel: uic command argument1
3950 * @mib_val: the value of the attribute as returned by the UIC command
3951 * @peer: indicate whether peer or local
3953 * Returns 0 on success, non-zero value on failure
3955 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
3956 u32 *mib_val, u8 peer)
3958 struct uic_command uic_cmd = {0};
3959 static const char *const action[] = {
3963 const char *get = action[!!peer];
3965 int retries = UFS_UIC_COMMAND_RETRIES;
3966 struct ufs_pa_layer_attr orig_pwr_info;
3967 struct ufs_pa_layer_attr temp_pwr_info;
3968 bool pwr_mode_change = false;
3970 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) {
3971 orig_pwr_info = hba->pwr_info;
3972 temp_pwr_info = orig_pwr_info;
3974 if (orig_pwr_info.pwr_tx == FAST_MODE ||
3975 orig_pwr_info.pwr_rx == FAST_MODE) {
3976 temp_pwr_info.pwr_tx = FASTAUTO_MODE;
3977 temp_pwr_info.pwr_rx = FASTAUTO_MODE;
3978 pwr_mode_change = true;
3979 } else if (orig_pwr_info.pwr_tx == SLOW_MODE ||
3980 orig_pwr_info.pwr_rx == SLOW_MODE) {
3981 temp_pwr_info.pwr_tx = SLOWAUTO_MODE;
3982 temp_pwr_info.pwr_rx = SLOWAUTO_MODE;
3983 pwr_mode_change = true;
3985 if (pwr_mode_change) {
3986 ret = ufshcd_change_power_mode(hba, &temp_pwr_info);
3992 uic_cmd.command = peer ?
3993 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
3994 uic_cmd.argument1 = attr_sel;
3997 /* for peer attributes we retry upon failure */
3998 ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
4000 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
4001 get, UIC_GET_ATTR_ID(attr_sel), ret);
4002 } while (ret && peer && --retries);
4005 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
4006 get, UIC_GET_ATTR_ID(attr_sel),
4007 UFS_UIC_COMMAND_RETRIES - retries);
4009 if (mib_val && !ret)
4010 *mib_val = uic_cmd.argument3;
4012 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)
4014 ufshcd_change_power_mode(hba, &orig_pwr_info);
4018 EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr);
4021 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
4022 * state) and waits for it to take effect.
4024 * @hba: per adapter instance
4025 * @cmd: UIC command to execute
4027 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER &
4028 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host
4029 * and device UniPro link and hence it's final completion would be indicated by
4030 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in
4031 * addition to normal UIC command completion Status (UCCS). This function only
4032 * returns after the relevant status bits indicate the completion.
4034 * Returns 0 on success, non-zero value on failure
4036 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
4038 DECLARE_COMPLETION_ONSTACK(uic_async_done);
4039 unsigned long flags;
4042 bool reenable_intr = false;
4044 mutex_lock(&hba->uic_cmd_mutex);
4045 ufshcd_add_delay_before_dme_cmd(hba);
4047 spin_lock_irqsave(hba->host->host_lock, flags);
4048 if (ufshcd_is_link_broken(hba)) {
4052 hba->uic_async_done = &uic_async_done;
4053 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) {
4054 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL);
4056 * Make sure UIC command completion interrupt is disabled before
4057 * issuing UIC command.
4060 reenable_intr = true;
4062 ret = __ufshcd_send_uic_cmd(hba, cmd, false);
4063 spin_unlock_irqrestore(hba->host->host_lock, flags);
4066 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
4067 cmd->command, cmd->argument3, ret);
4071 if (!wait_for_completion_timeout(hba->uic_async_done,
4072 msecs_to_jiffies(UIC_CMD_TIMEOUT))) {
4074 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
4075 cmd->command, cmd->argument3);
4077 if (!cmd->cmd_active) {
4078 dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n",
4088 status = ufshcd_get_upmcrs(hba);
4089 if (status != PWR_LOCAL) {
4091 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
4092 cmd->command, status);
4093 ret = (status != PWR_OK) ? status : -1;
4097 ufshcd_print_host_state(hba);
4098 ufshcd_print_pwr_info(hba);
4099 ufshcd_print_evt_hist(hba);
4102 spin_lock_irqsave(hba->host->host_lock, flags);
4103 hba->active_uic_cmd = NULL;
4104 hba->uic_async_done = NULL;
4106 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL);
4108 ufshcd_set_link_broken(hba);
4109 ufshcd_schedule_eh_work(hba);
4112 spin_unlock_irqrestore(hba->host->host_lock, flags);
4113 mutex_unlock(&hba->uic_cmd_mutex);
4119 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage
4120 * using DME_SET primitives.
4121 * @hba: per adapter instance
4122 * @mode: powr mode value
4124 * Returns 0 on success, non-zero value on failure
4126 static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
4128 struct uic_command uic_cmd = {0};
4131 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) {
4132 ret = ufshcd_dme_set(hba,
4133 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1);
4135 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n",
4141 uic_cmd.command = UIC_CMD_DME_SET;
4142 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
4143 uic_cmd.argument3 = mode;
4144 ufshcd_hold(hba, false);
4145 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4146 ufshcd_release(hba);
4152 int ufshcd_link_recovery(struct ufs_hba *hba)
4155 unsigned long flags;
4157 spin_lock_irqsave(hba->host->host_lock, flags);
4158 hba->ufshcd_state = UFSHCD_STATE_RESET;
4159 ufshcd_set_eh_in_progress(hba);
4160 spin_unlock_irqrestore(hba->host->host_lock, flags);
4162 /* Reset the attached device */
4163 ufshcd_device_reset(hba);
4165 ret = ufshcd_host_reset_and_restore(hba);
4167 spin_lock_irqsave(hba->host->host_lock, flags);
4169 hba->ufshcd_state = UFSHCD_STATE_ERROR;
4170 ufshcd_clear_eh_in_progress(hba);
4171 spin_unlock_irqrestore(hba->host->host_lock, flags);
4174 dev_err(hba->dev, "%s: link recovery failed, err %d",
4179 EXPORT_SYMBOL_GPL(ufshcd_link_recovery);
4181 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba)
4184 struct uic_command uic_cmd = {0};
4185 ktime_t start = ktime_get();
4187 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE);
4189 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER;
4190 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4191 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter",
4192 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
4195 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n",
4198 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER,
4203 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_enter);
4205 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
4207 struct uic_command uic_cmd = {0};
4209 ktime_t start = ktime_get();
4211 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE);
4213 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT;
4214 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
4215 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit",
4216 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
4219 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n",
4222 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT,
4224 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_get();
4225 hba->ufs_stats.hibern8_exit_cnt++;
4230 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit);
4232 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit)
4234 unsigned long flags;
4235 bool update = false;
4237 if (!ufshcd_is_auto_hibern8_supported(hba))
4240 spin_lock_irqsave(hba->host->host_lock, flags);
4241 if (hba->ahit != ahit) {
4245 spin_unlock_irqrestore(hba->host->host_lock, flags);
4248 !pm_runtime_suspended(&hba->ufs_device_wlun->sdev_gendev)) {
4249 ufshcd_rpm_get_sync(hba);
4250 ufshcd_hold(hba, false);
4251 ufshcd_auto_hibern8_enable(hba);
4252 ufshcd_release(hba);
4253 ufshcd_rpm_put_sync(hba);
4256 EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update);
4258 void ufshcd_auto_hibern8_enable(struct ufs_hba *hba)
4260 if (!ufshcd_is_auto_hibern8_supported(hba))
4263 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
4267 * ufshcd_init_pwr_info - setting the POR (power on reset)
4268 * values in hba power info
4269 * @hba: per-adapter instance
4271 static void ufshcd_init_pwr_info(struct ufs_hba *hba)
4273 hba->pwr_info.gear_rx = UFS_PWM_G1;
4274 hba->pwr_info.gear_tx = UFS_PWM_G1;
4275 hba->pwr_info.lane_rx = 1;
4276 hba->pwr_info.lane_tx = 1;
4277 hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
4278 hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
4279 hba->pwr_info.hs_rate = 0;
4283 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
4284 * @hba: per-adapter instance
4286 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
4288 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
4290 if (hba->max_pwr_info.is_valid)
4293 pwr_info->pwr_tx = FAST_MODE;
4294 pwr_info->pwr_rx = FAST_MODE;
4295 pwr_info->hs_rate = PA_HS_MODE_B;
4297 /* Get the connected lane count */
4298 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
4299 &pwr_info->lane_rx);
4300 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4301 &pwr_info->lane_tx);
4303 if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
4304 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
4312 * First, get the maximum gears of HS speed.
4313 * If a zero value, it means there is no HSGEAR capability.
4314 * Then, get the maximum gears of PWM speed.
4316 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
4317 if (!pwr_info->gear_rx) {
4318 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4319 &pwr_info->gear_rx);
4320 if (!pwr_info->gear_rx) {
4321 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
4322 __func__, pwr_info->gear_rx);
4325 pwr_info->pwr_rx = SLOW_MODE;
4328 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
4329 &pwr_info->gear_tx);
4330 if (!pwr_info->gear_tx) {
4331 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
4332 &pwr_info->gear_tx);
4333 if (!pwr_info->gear_tx) {
4334 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
4335 __func__, pwr_info->gear_tx);
4338 pwr_info->pwr_tx = SLOW_MODE;
4341 hba->max_pwr_info.is_valid = true;
4345 static int ufshcd_change_power_mode(struct ufs_hba *hba,
4346 struct ufs_pa_layer_attr *pwr_mode)
4350 /* if already configured to the requested pwr_mode */
4351 if (!hba->force_pmc &&
4352 pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
4353 pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
4354 pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
4355 pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
4356 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
4357 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
4358 pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
4359 dev_dbg(hba->dev, "%s: power already configured\n", __func__);
4364 * Configure attributes for power mode change with below.
4365 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
4366 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
4369 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
4370 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
4372 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4373 pwr_mode->pwr_rx == FAST_MODE)
4374 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), true);
4376 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), false);
4378 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
4379 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
4381 if (pwr_mode->pwr_tx == FASTAUTO_MODE ||
4382 pwr_mode->pwr_tx == FAST_MODE)
4383 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true);
4385 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), false);
4387 if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
4388 pwr_mode->pwr_tx == FASTAUTO_MODE ||
4389 pwr_mode->pwr_rx == FAST_MODE ||
4390 pwr_mode->pwr_tx == FAST_MODE)
4391 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
4394 if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) {
4395 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0),
4396 DL_FC0ProtectionTimeOutVal_Default);
4397 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1),
4398 DL_TC0ReplayTimeOutVal_Default);
4399 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2),
4400 DL_AFC0ReqTimeOutVal_Default);
4401 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3),
4402 DL_FC1ProtectionTimeOutVal_Default);
4403 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4),
4404 DL_TC1ReplayTimeOutVal_Default);
4405 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5),
4406 DL_AFC1ReqTimeOutVal_Default);
4408 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal),
4409 DL_FC0ProtectionTimeOutVal_Default);
4410 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal),
4411 DL_TC0ReplayTimeOutVal_Default);
4412 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal),
4413 DL_AFC0ReqTimeOutVal_Default);
4416 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4
4417 | pwr_mode->pwr_tx);
4421 "%s: power mode change failed %d\n", __func__, ret);
4423 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL,
4426 memcpy(&hba->pwr_info, pwr_mode,
4427 sizeof(struct ufs_pa_layer_attr));
4434 * ufshcd_config_pwr_mode - configure a new power mode
4435 * @hba: per-adapter instance
4436 * @desired_pwr_mode: desired power configuration
4438 int ufshcd_config_pwr_mode(struct ufs_hba *hba,
4439 struct ufs_pa_layer_attr *desired_pwr_mode)
4441 struct ufs_pa_layer_attr final_params = { 0 };
4444 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE,
4445 desired_pwr_mode, &final_params);
4448 memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
4450 ret = ufshcd_change_power_mode(hba, &final_params);
4454 EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
4457 * ufshcd_complete_dev_init() - checks device readiness
4458 * @hba: per-adapter instance
4460 * Set fDeviceInit flag and poll until device toggles it.
4462 static int ufshcd_complete_dev_init(struct ufs_hba *hba)
4465 bool flag_res = true;
4468 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
4469 QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL);
4472 "%s setting fDeviceInit flag failed with error %d\n",
4477 /* Poll fDeviceInit flag to be cleared */
4478 timeout = ktime_add_ms(ktime_get(), FDEVICEINIT_COMPL_TIMEOUT);
4480 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG,
4481 QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res);
4484 usleep_range(500, 1000);
4485 } while (ktime_before(ktime_get(), timeout));
4489 "%s reading fDeviceInit flag failed with error %d\n",
4491 } else if (flag_res) {
4493 "%s fDeviceInit was not cleared by the device\n",
4502 * ufshcd_make_hba_operational - Make UFS controller operational
4503 * @hba: per adapter instance
4505 * To bring UFS host controller to operational state,
4506 * 1. Enable required interrupts
4507 * 2. Configure interrupt aggregation
4508 * 3. Program UTRL and UTMRL base address
4509 * 4. Configure run-stop-registers
4511 * Returns 0 on success, non-zero value on failure
4513 int ufshcd_make_hba_operational(struct ufs_hba *hba)
4518 /* Enable required interrupts */
4519 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
4521 /* Configure interrupt aggregation */
4522 if (ufshcd_is_intr_aggr_allowed(hba))
4523 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO);
4525 ufshcd_disable_intr_aggr(hba);
4527 /* Configure UTRL and UTMRL base address registers */
4528 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr),
4529 REG_UTP_TRANSFER_REQ_LIST_BASE_L);
4530 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr),
4531 REG_UTP_TRANSFER_REQ_LIST_BASE_H);
4532 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr),
4533 REG_UTP_TASK_REQ_LIST_BASE_L);
4534 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr),
4535 REG_UTP_TASK_REQ_LIST_BASE_H);
4538 * Make sure base address and interrupt setup are updated before
4539 * enabling the run/stop registers below.
4544 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
4546 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
4547 if (!(ufshcd_get_lists_status(reg))) {
4548 ufshcd_enable_run_stop_reg(hba);
4551 "Host controller not ready to process requests");
4557 EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational);
4560 * ufshcd_hba_stop - Send controller to reset state
4561 * @hba: per adapter instance
4563 void ufshcd_hba_stop(struct ufs_hba *hba)
4565 unsigned long flags;
4569 * Obtain the host lock to prevent that the controller is disabled
4570 * while the UFS interrupt handler is active on another CPU.
4572 spin_lock_irqsave(hba->host->host_lock, flags);
4573 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
4574 spin_unlock_irqrestore(hba->host->host_lock, flags);
4576 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
4577 CONTROLLER_ENABLE, CONTROLLER_DISABLE,
4580 dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
4582 EXPORT_SYMBOL_GPL(ufshcd_hba_stop);
4585 * ufshcd_hba_execute_hce - initialize the controller
4586 * @hba: per adapter instance
4588 * The controller resets itself and controller firmware initialization
4589 * sequence kicks off. When controller is ready it will set
4590 * the Host Controller Enable bit to 1.
4592 * Returns 0 on success, non-zero value on failure
4594 static int ufshcd_hba_execute_hce(struct ufs_hba *hba)
4596 int retry_outer = 3;
4600 if (ufshcd_is_hba_active(hba))
4601 /* change controller state to "reset state" */
4602 ufshcd_hba_stop(hba);
4604 /* UniPro link is disabled at this point */
4605 ufshcd_set_link_off(hba);
4607 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4609 /* start controller initialization sequence */
4610 ufshcd_hba_start(hba);
4613 * To initialize a UFS host controller HCE bit must be set to 1.
4614 * During initialization the HCE bit value changes from 1->0->1.
4615 * When the host controller completes initialization sequence
4616 * it sets the value of HCE bit to 1. The same HCE bit is read back
4617 * to check if the controller has completed initialization sequence.
4618 * So without this delay the value HCE = 1, set in the previous
4619 * instruction might be read back.
4620 * This delay can be changed based on the controller.
4622 ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100);
4624 /* wait for the host controller to complete initialization */
4626 while (!ufshcd_is_hba_active(hba)) {
4631 "Controller enable failed\n");
4638 usleep_range(1000, 1100);
4641 /* enable UIC related interrupts */
4642 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4644 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4649 int ufshcd_hba_enable(struct ufs_hba *hba)
4653 if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) {
4654 ufshcd_set_link_off(hba);
4655 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE);
4657 /* enable UIC related interrupts */
4658 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
4659 ret = ufshcd_dme_reset(hba);
4661 ret = ufshcd_dme_enable(hba);
4663 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE);
4666 "Host controller enable failed with non-hce\n");
4669 ret = ufshcd_hba_execute_hce(hba);
4674 EXPORT_SYMBOL_GPL(ufshcd_hba_enable);
4676 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
4678 int tx_lanes = 0, i, err = 0;
4681 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4684 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
4686 for (i = 0; i < tx_lanes; i++) {
4688 err = ufshcd_dme_set(hba,
4689 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4690 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4693 err = ufshcd_dme_peer_set(hba,
4694 UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
4695 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
4698 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
4699 __func__, peer, i, err);
4707 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
4709 return ufshcd_disable_tx_lcc(hba, true);
4712 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val)
4714 struct ufs_event_hist *e;
4716 if (id >= UFS_EVT_CNT)
4719 e = &hba->ufs_stats.event[id];
4720 e->val[e->pos] = val;
4721 e->tstamp[e->pos] = ktime_get();
4723 e->pos = (e->pos + 1) % UFS_EVENT_HIST_LENGTH;
4725 ufshcd_vops_event_notify(hba, id, &val);
4727 EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist);
4730 * ufshcd_link_startup - Initialize unipro link startup
4731 * @hba: per adapter instance
4733 * Returns 0 for success, non-zero in case of failure
4735 static int ufshcd_link_startup(struct ufs_hba *hba)
4738 int retries = DME_LINKSTARTUP_RETRIES;
4739 bool link_startup_again = false;
4742 * If UFS device isn't active then we will have to issue link startup
4743 * 2 times to make sure the device state move to active.
4745 if (!ufshcd_is_ufs_dev_active(hba))
4746 link_startup_again = true;
4750 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE);
4752 ret = ufshcd_dme_link_startup(hba);
4754 /* check if device is detected by inter-connect layer */
4755 if (!ret && !ufshcd_is_device_present(hba)) {
4756 ufshcd_update_evt_hist(hba,
4757 UFS_EVT_LINK_STARTUP_FAIL,
4759 dev_err(hba->dev, "%s: Device not present\n", __func__);
4765 * DME link lost indication is only received when link is up,
4766 * but we can't be sure if the link is up until link startup
4767 * succeeds. So reset the local Uni-Pro and try again.
4769 if (ret && ufshcd_hba_enable(hba)) {
4770 ufshcd_update_evt_hist(hba,
4771 UFS_EVT_LINK_STARTUP_FAIL,
4775 } while (ret && retries--);
4778 /* failed to get the link up... retire */
4779 ufshcd_update_evt_hist(hba,
4780 UFS_EVT_LINK_STARTUP_FAIL,
4785 if (link_startup_again) {
4786 link_startup_again = false;
4787 retries = DME_LINKSTARTUP_RETRIES;
4791 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
4792 ufshcd_init_pwr_info(hba);
4793 ufshcd_print_pwr_info(hba);
4795 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
4796 ret = ufshcd_disable_device_tx_lcc(hba);
4801 /* Include any host controller configuration via UIC commands */
4802 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE);
4806 /* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */
4807 ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
4808 ret = ufshcd_make_hba_operational(hba);
4811 dev_err(hba->dev, "link startup failed %d\n", ret);
4812 ufshcd_print_host_state(hba);
4813 ufshcd_print_pwr_info(hba);
4814 ufshcd_print_evt_hist(hba);
4820 * ufshcd_verify_dev_init() - Verify device initialization
4821 * @hba: per-adapter instance
4823 * Send NOP OUT UPIU and wait for NOP IN response to check whether the
4824 * device Transport Protocol (UTP) layer is ready after a reset.
4825 * If the UTP layer at the device side is not initialized, it may
4826 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT
4827 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations.
4829 static int ufshcd_verify_dev_init(struct ufs_hba *hba)
4834 ufshcd_hold(hba, false);
4835 mutex_lock(&hba->dev_cmd.lock);
4836 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
4837 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
4838 hba->nop_out_timeout);
4840 if (!err || err == -ETIMEDOUT)
4843 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
4845 mutex_unlock(&hba->dev_cmd.lock);
4846 ufshcd_release(hba);
4849 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
4854 * ufshcd_set_queue_depth - set lun queue depth
4855 * @sdev: pointer to SCSI device
4857 * Read bLUQueueDepth value and activate scsi tagged command
4858 * queueing. For WLUN, queue depth is set to 1. For best-effort
4859 * cases (bLUQueueDepth = 0) the queue depth is set to a maximum
4860 * value that host can queue.
4862 static void ufshcd_set_queue_depth(struct scsi_device *sdev)
4866 struct ufs_hba *hba;
4868 hba = shost_priv(sdev->host);
4870 lun_qdepth = hba->nutrs;
4871 ret = ufshcd_read_unit_desc_param(hba,
4872 ufshcd_scsi_to_upiu_lun(sdev->lun),
4873 UNIT_DESC_PARAM_LU_Q_DEPTH,
4875 sizeof(lun_qdepth));
4877 /* Some WLUN doesn't support unit descriptor */
4878 if (ret == -EOPNOTSUPP)
4880 else if (!lun_qdepth)
4881 /* eventually, we can figure out the real queue depth */
4882 lun_qdepth = hba->nutrs;
4884 lun_qdepth = min_t(int, lun_qdepth, hba->nutrs);
4886 dev_dbg(hba->dev, "%s: activate tcq with queue depth %d\n",
4887 __func__, lun_qdepth);
4888 scsi_change_queue_depth(sdev, lun_qdepth);
4892 * ufshcd_get_lu_wp - returns the "b_lu_write_protect" from UNIT DESCRIPTOR
4893 * @hba: per-adapter instance
4894 * @lun: UFS device lun id
4895 * @b_lu_write_protect: pointer to buffer to hold the LU's write protect info
4897 * Returns 0 in case of success and b_lu_write_protect status would be returned
4898 * @b_lu_write_protect parameter.
4899 * Returns -ENOTSUPP if reading b_lu_write_protect is not supported.
4900 * Returns -EINVAL in case of invalid parameters passed to this function.
4902 static int ufshcd_get_lu_wp(struct ufs_hba *hba,
4904 u8 *b_lu_write_protect)
4908 if (!b_lu_write_protect)
4911 * According to UFS device spec, RPMB LU can't be write
4912 * protected so skip reading bLUWriteProtect parameter for
4913 * it. For other W-LUs, UNIT DESCRIPTOR is not available.
4915 else if (lun >= hba->dev_info.max_lu_supported)
4918 ret = ufshcd_read_unit_desc_param(hba,
4920 UNIT_DESC_PARAM_LU_WR_PROTECT,
4922 sizeof(*b_lu_write_protect));
4927 * ufshcd_get_lu_power_on_wp_status - get LU's power on write protect
4929 * @hba: per-adapter instance
4930 * @sdev: pointer to SCSI device
4933 static inline void ufshcd_get_lu_power_on_wp_status(struct ufs_hba *hba,
4934 struct scsi_device *sdev)
4936 if (hba->dev_info.f_power_on_wp_en &&
4937 !hba->dev_info.is_lu_power_on_wp) {
4938 u8 b_lu_write_protect;
4940 if (!ufshcd_get_lu_wp(hba, ufshcd_scsi_to_upiu_lun(sdev->lun),
4941 &b_lu_write_protect) &&
4942 (b_lu_write_protect == UFS_LU_POWER_ON_WP))
4943 hba->dev_info.is_lu_power_on_wp = true;
4948 * ufshcd_setup_links - associate link b/w device wlun and other luns
4949 * @sdev: pointer to SCSI device
4950 * @hba: pointer to ufs hba
4952 static void ufshcd_setup_links(struct ufs_hba *hba, struct scsi_device *sdev)
4954 struct device_link *link;
4957 * Device wlun is the supplier & rest of the luns are consumers.
4958 * This ensures that device wlun suspends after all other luns.
4960 if (hba->ufs_device_wlun) {
4961 link = device_link_add(&sdev->sdev_gendev,
4962 &hba->ufs_device_wlun->sdev_gendev,
4963 DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE);
4965 dev_err(&sdev->sdev_gendev, "Failed establishing link - %s\n",
4966 dev_name(&hba->ufs_device_wlun->sdev_gendev));
4970 /* Ignore REPORT_LUN wlun probing */
4971 if (hba->luns_avail == 1) {
4972 ufshcd_rpm_put(hba);
4977 * Device wlun is probed. The assumption is that WLUNs are
4978 * scanned before other LUNs.
4985 * ufshcd_slave_alloc - handle initial SCSI device configurations
4986 * @sdev: pointer to SCSI device
4990 static int ufshcd_slave_alloc(struct scsi_device *sdev)
4992 struct ufs_hba *hba;
4994 hba = shost_priv(sdev->host);
4996 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
4997 sdev->use_10_for_ms = 1;
4999 /* DBD field should be set to 1 in mode sense(10) */
5000 sdev->set_dbd_for_ms = 1;
5002 /* allow SCSI layer to restart the device in case of errors */
5003 sdev->allow_restart = 1;
5005 /* REPORT SUPPORTED OPERATION CODES is not supported */
5006 sdev->no_report_opcodes = 1;
5008 /* WRITE_SAME command is not supported */
5009 sdev->no_write_same = 1;
5011 ufshcd_set_queue_depth(sdev);
5013 ufshcd_get_lu_power_on_wp_status(hba, sdev);
5015 ufshcd_setup_links(hba, sdev);
5021 * ufshcd_change_queue_depth - change queue depth
5022 * @sdev: pointer to SCSI device
5023 * @depth: required depth to set
5025 * Change queue depth and make sure the max. limits are not crossed.
5027 static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth)
5029 return scsi_change_queue_depth(sdev, min(depth, sdev->host->can_queue));
5032 static void ufshcd_hpb_destroy(struct ufs_hba *hba, struct scsi_device *sdev)
5034 /* skip well-known LU */
5035 if ((sdev->lun >= UFS_UPIU_MAX_UNIT_NUM_ID) ||
5036 !(hba->dev_info.hpb_enabled) || !ufshpb_is_allowed(hba))
5039 ufshpb_destroy_lu(hba, sdev);
5042 static void ufshcd_hpb_configure(struct ufs_hba *hba, struct scsi_device *sdev)
5044 /* skip well-known LU */
5045 if ((sdev->lun >= UFS_UPIU_MAX_UNIT_NUM_ID) ||
5046 !(hba->dev_info.hpb_enabled) || !ufshpb_is_allowed(hba))
5049 ufshpb_init_hpb_lu(hba, sdev);
5053 * ufshcd_slave_configure - adjust SCSI device configurations
5054 * @sdev: pointer to SCSI device
5056 static int ufshcd_slave_configure(struct scsi_device *sdev)
5058 struct ufs_hba *hba = shost_priv(sdev->host);
5059 struct request_queue *q = sdev->request_queue;
5061 ufshcd_hpb_configure(hba, sdev);
5063 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1);
5064 if (hba->quirks & UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE)
5065 blk_queue_update_dma_alignment(q, PAGE_SIZE - 1);
5067 * Block runtime-pm until all consumers are added.
5068 * Refer ufshcd_setup_links().
5070 if (is_device_wlun(sdev))
5071 pm_runtime_get_noresume(&sdev->sdev_gendev);
5072 else if (ufshcd_is_rpm_autosuspend_allowed(hba))
5073 sdev->rpm_autosuspend = 1;
5075 * Do not print messages during runtime PM to avoid never-ending cycles
5076 * of messages written back to storage by user space causing runtime
5077 * resume, causing more messages and so on.
5079 sdev->silence_suspend = 1;
5081 ufshcd_crypto_register(hba, q);
5087 * ufshcd_slave_destroy - remove SCSI device configurations
5088 * @sdev: pointer to SCSI device
5090 static void ufshcd_slave_destroy(struct scsi_device *sdev)
5092 struct ufs_hba *hba;
5093 unsigned long flags;
5095 hba = shost_priv(sdev->host);
5097 ufshcd_hpb_destroy(hba, sdev);
5099 /* Drop the reference as it won't be needed anymore */
5100 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) {
5101 spin_lock_irqsave(hba->host->host_lock, flags);
5102 hba->ufs_device_wlun = NULL;
5103 spin_unlock_irqrestore(hba->host->host_lock, flags);
5104 } else if (hba->ufs_device_wlun) {
5105 struct device *supplier = NULL;
5107 /* Ensure UFS Device WLUN exists and does not disappear */
5108 spin_lock_irqsave(hba->host->host_lock, flags);
5109 if (hba->ufs_device_wlun) {
5110 supplier = &hba->ufs_device_wlun->sdev_gendev;
5111 get_device(supplier);
5113 spin_unlock_irqrestore(hba->host->host_lock, flags);
5117 * If a LUN fails to probe (e.g. absent BOOT WLUN), the
5118 * device will not have been registered but can still
5119 * have a device link holding a reference to the device.
5121 device_link_remove(&sdev->sdev_gendev, supplier);
5122 put_device(supplier);
5128 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
5129 * @lrbp: pointer to local reference block of completed command
5130 * @scsi_status: SCSI command status
5132 * Returns value base on SCSI command status
5135 ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
5139 switch (scsi_status) {
5140 case SAM_STAT_CHECK_CONDITION:
5141 ufshcd_copy_sense_data(lrbp);
5144 result |= DID_OK << 16 | scsi_status;
5146 case SAM_STAT_TASK_SET_FULL:
5148 case SAM_STAT_TASK_ABORTED:
5149 ufshcd_copy_sense_data(lrbp);
5150 result |= scsi_status;
5153 result |= DID_ERROR << 16;
5155 } /* end of switch */
5161 * ufshcd_transfer_rsp_status - Get overall status of the response
5162 * @hba: per adapter instance
5163 * @lrbp: pointer to local reference block of completed command
5165 * Returns result of the command to notify SCSI midlayer
5168 ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
5174 /* overall command status of utrd */
5175 ocs = ufshcd_get_tr_ocs(lrbp);
5177 if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) {
5178 if (be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_1) &
5179 MASK_RSP_UPIU_RESULT)
5185 result = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr);
5186 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
5188 case UPIU_TRANSACTION_RESPONSE:
5190 * get the response UPIU result to extract
5191 * the SCSI command status
5193 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
5196 * get the result based on SCSI status response
5197 * to notify the SCSI midlayer of the command status
5199 scsi_status = result & MASK_SCSI_STATUS;
5200 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
5203 * Currently we are only supporting BKOPs exception
5204 * events hence we can ignore BKOPs exception event
5205 * during power management callbacks. BKOPs exception
5206 * event is not expected to be raised in runtime suspend
5207 * callback as it allows the urgent bkops.
5208 * During system suspend, we are anyway forcefully
5209 * disabling the bkops and if urgent bkops is needed
5210 * it will be enabled on system resume. Long term
5211 * solution could be to abort the system suspend if
5212 * UFS device needs urgent BKOPs.
5214 if (!hba->pm_op_in_progress &&
5215 !ufshcd_eh_in_progress(hba) &&
5216 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr))
5217 /* Flushed in suspend */
5218 schedule_work(&hba->eeh_work);
5220 if (scsi_status == SAM_STAT_GOOD)
5221 ufshpb_rsp_upiu(hba, lrbp);
5223 case UPIU_TRANSACTION_REJECT_UPIU:
5224 /* TODO: handle Reject UPIU Response */
5225 result = DID_ERROR << 16;
5227 "Reject UPIU not fully implemented\n");
5231 "Unexpected request response code = %x\n",
5233 result = DID_ERROR << 16;
5238 result |= DID_ABORT << 16;
5240 case OCS_INVALID_COMMAND_STATUS:
5241 result |= DID_REQUEUE << 16;
5243 case OCS_INVALID_CMD_TABLE_ATTR:
5244 case OCS_INVALID_PRDT_ATTR:
5245 case OCS_MISMATCH_DATA_BUF_SIZE:
5246 case OCS_MISMATCH_RESP_UPIU_SIZE:
5247 case OCS_PEER_COMM_FAILURE:
5248 case OCS_FATAL_ERROR:
5249 case OCS_DEVICE_FATAL_ERROR:
5250 case OCS_INVALID_CRYPTO_CONFIG:
5251 case OCS_GENERAL_CRYPTO_ERROR:
5253 result |= DID_ERROR << 16;
5255 "OCS error from controller = %x for tag %d\n",
5256 ocs, lrbp->task_tag);
5257 ufshcd_print_evt_hist(hba);
5258 ufshcd_print_host_state(hba);
5260 } /* end of switch */
5262 if ((host_byte(result) != DID_OK) &&
5263 (host_byte(result) != DID_REQUEUE) && !hba->silence_err_logs)
5264 ufshcd_print_trs(hba, 1 << lrbp->task_tag, true);
5268 static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba,
5271 if (!ufshcd_is_auto_hibern8_supported(hba) ||
5272 !ufshcd_is_auto_hibern8_enabled(hba))
5275 if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK))
5278 if (hba->active_uic_cmd &&
5279 (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER ||
5280 hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT))
5287 * ufshcd_uic_cmd_compl - handle completion of uic command
5288 * @hba: per adapter instance
5289 * @intr_status: interrupt status generated by the controller
5292 * IRQ_HANDLED - If interrupt is valid
5293 * IRQ_NONE - If invalid interrupt
5295 static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status)
5297 irqreturn_t retval = IRQ_NONE;
5299 spin_lock(hba->host->host_lock);
5300 if (ufshcd_is_auto_hibern8_error(hba, intr_status))
5301 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status);
5303 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) {
5304 hba->active_uic_cmd->argument2 |=
5305 ufshcd_get_uic_cmd_result(hba);
5306 hba->active_uic_cmd->argument3 =
5307 ufshcd_get_dme_attr_val(hba);
5308 if (!hba->uic_async_done)
5309 hba->active_uic_cmd->cmd_active = 0;
5310 complete(&hba->active_uic_cmd->done);
5311 retval = IRQ_HANDLED;
5314 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) {
5315 hba->active_uic_cmd->cmd_active = 0;
5316 complete(hba->uic_async_done);
5317 retval = IRQ_HANDLED;
5320 if (retval == IRQ_HANDLED)
5321 ufshcd_add_uic_command_trace(hba, hba->active_uic_cmd,
5323 spin_unlock(hba->host->host_lock);
5327 /* Release the resources allocated for processing a SCSI command. */
5328 static void ufshcd_release_scsi_cmd(struct ufs_hba *hba,
5329 struct ufshcd_lrb *lrbp)
5331 struct scsi_cmnd *cmd = lrbp->cmd;
5333 scsi_dma_unmap(cmd);
5334 lrbp->cmd = NULL; /* Mark the command as completed. */
5335 ufshcd_release(hba);
5336 ufshcd_clk_scaling_update_busy(hba);
5340 * __ufshcd_transfer_req_compl - handle SCSI and query command completion
5341 * @hba: per adapter instance
5342 * @completed_reqs: bitmask that indicates which requests to complete
5344 static void __ufshcd_transfer_req_compl(struct ufs_hba *hba,
5345 unsigned long completed_reqs)
5347 struct ufshcd_lrb *lrbp;
5348 struct scsi_cmnd *cmd;
5351 for_each_set_bit(index, &completed_reqs, hba->nutrs) {
5352 lrbp = &hba->lrb[index];
5353 lrbp->compl_time_stamp = ktime_get();
5356 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp)))
5357 ufshcd_update_monitor(hba, lrbp);
5358 ufshcd_add_command_trace(hba, index, UFS_CMD_COMP);
5359 cmd->result = ufshcd_transfer_rsp_status(hba, lrbp);
5360 ufshcd_release_scsi_cmd(hba, lrbp);
5361 /* Do not touch lrbp after scsi done */
5363 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE ||
5364 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) {
5365 if (hba->dev_cmd.complete) {
5366 ufshcd_add_command_trace(hba, index,
5368 complete(hba->dev_cmd.complete);
5369 ufshcd_clk_scaling_update_busy(hba);
5376 * Returns > 0 if one or more commands have been completed or 0 if no
5377 * requests have been completed.
5379 static int ufshcd_poll(struct Scsi_Host *shost, unsigned int queue_num)
5381 struct ufs_hba *hba = shost_priv(shost);
5382 unsigned long completed_reqs, flags;
5385 spin_lock_irqsave(&hba->outstanding_lock, flags);
5386 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
5387 completed_reqs = ~tr_doorbell & hba->outstanding_reqs;
5388 WARN_ONCE(completed_reqs & ~hba->outstanding_reqs,
5389 "completed: %#lx; outstanding: %#lx\n", completed_reqs,
5390 hba->outstanding_reqs);
5391 hba->outstanding_reqs &= ~completed_reqs;
5392 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
5395 __ufshcd_transfer_req_compl(hba, completed_reqs);
5397 return completed_reqs;
5401 * ufshcd_transfer_req_compl - handle SCSI and query command completion
5402 * @hba: per adapter instance
5405 * IRQ_HANDLED - If interrupt is valid
5406 * IRQ_NONE - If invalid interrupt
5408 static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba)
5410 /* Resetting interrupt aggregation counters first and reading the
5411 * DOOR_BELL afterward allows us to handle all the completed requests.
5412 * In order to prevent other interrupts starvation the DB is read once
5413 * after reset. The down side of this solution is the possibility of
5414 * false interrupt if device completes another request after resetting
5415 * aggregation and before reading the DB.
5417 if (ufshcd_is_intr_aggr_allowed(hba) &&
5418 !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
5419 ufshcd_reset_intr_aggr(hba);
5421 if (ufs_fail_completion())
5425 * Ignore the ufshcd_poll() return value and return IRQ_HANDLED since we
5426 * do not want polling to trigger spurious interrupt complaints.
5428 ufshcd_poll(hba->host, 0);
5433 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask)
5435 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
5436 QUERY_ATTR_IDN_EE_CONTROL, 0, 0,
5440 int ufshcd_write_ee_control(struct ufs_hba *hba)
5444 mutex_lock(&hba->ee_ctrl_mutex);
5445 err = __ufshcd_write_ee_control(hba, hba->ee_ctrl_mask);
5446 mutex_unlock(&hba->ee_ctrl_mutex);
5448 dev_err(hba->dev, "%s: failed to write ee control %d\n",
5453 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, u16 *other_mask,
5456 u16 new_mask, ee_ctrl_mask;
5459 mutex_lock(&hba->ee_ctrl_mutex);
5460 new_mask = (*mask & ~clr) | set;
5461 ee_ctrl_mask = new_mask | *other_mask;
5462 if (ee_ctrl_mask != hba->ee_ctrl_mask)
5463 err = __ufshcd_write_ee_control(hba, ee_ctrl_mask);
5464 /* Still need to update 'mask' even if 'ee_ctrl_mask' was unchanged */
5466 hba->ee_ctrl_mask = ee_ctrl_mask;
5469 mutex_unlock(&hba->ee_ctrl_mutex);
5474 * ufshcd_disable_ee - disable exception event
5475 * @hba: per-adapter instance
5476 * @mask: exception event to disable
5478 * Disables exception event in the device so that the EVENT_ALERT
5481 * Returns zero on success, non-zero error value on failure.
5483 static inline int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask)
5485 return ufshcd_update_ee_drv_mask(hba, 0, mask);
5489 * ufshcd_enable_ee - enable exception event
5490 * @hba: per-adapter instance
5491 * @mask: exception event to enable
5493 * Enable corresponding exception event in the device to allow
5494 * device to alert host in critical scenarios.
5496 * Returns zero on success, non-zero error value on failure.
5498 static inline int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask)
5500 return ufshcd_update_ee_drv_mask(hba, mask, 0);
5504 * ufshcd_enable_auto_bkops - Allow device managed BKOPS
5505 * @hba: per-adapter instance
5507 * Allow device to manage background operations on its own. Enabling
5508 * this might lead to inconsistent latencies during normal data transfers
5509 * as the device is allowed to manage its own way of handling background
5512 * Returns zero on success, non-zero on failure.
5514 static int ufshcd_enable_auto_bkops(struct ufs_hba *hba)
5518 if (hba->auto_bkops_enabled)
5521 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
5522 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
5524 dev_err(hba->dev, "%s: failed to enable bkops %d\n",
5529 hba->auto_bkops_enabled = true;
5530 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled");
5532 /* No need of URGENT_BKOPS exception from the device */
5533 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5535 dev_err(hba->dev, "%s: failed to disable exception event %d\n",
5542 * ufshcd_disable_auto_bkops - block device in doing background operations
5543 * @hba: per-adapter instance
5545 * Disabling background operations improves command response latency but
5546 * has drawback of device moving into critical state where the device is
5547 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the
5548 * host is idle so that BKOPS are managed effectively without any negative
5551 * Returns zero on success, non-zero on failure.
5553 static int ufshcd_disable_auto_bkops(struct ufs_hba *hba)
5557 if (!hba->auto_bkops_enabled)
5561 * If host assisted BKOPs is to be enabled, make sure
5562 * urgent bkops exception is allowed.
5564 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS);
5566 dev_err(hba->dev, "%s: failed to enable exception event %d\n",
5571 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG,
5572 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL);
5574 dev_err(hba->dev, "%s: failed to disable bkops %d\n",
5576 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS);
5580 hba->auto_bkops_enabled = false;
5581 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled");
5582 hba->is_urgent_bkops_lvl_checked = false;
5588 * ufshcd_force_reset_auto_bkops - force reset auto bkops state
5589 * @hba: per adapter instance
5591 * After a device reset the device may toggle the BKOPS_EN flag
5592 * to default value. The s/w tracking variables should be updated
5593 * as well. This function would change the auto-bkops state based on
5594 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND.
5596 static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba)
5598 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) {
5599 hba->auto_bkops_enabled = false;
5600 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS;
5601 ufshcd_enable_auto_bkops(hba);
5603 hba->auto_bkops_enabled = true;
5604 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS;
5605 ufshcd_disable_auto_bkops(hba);
5607 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT;
5608 hba->is_urgent_bkops_lvl_checked = false;
5611 static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status)
5613 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5614 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status);
5618 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status
5619 * @hba: per-adapter instance
5620 * @status: bkops_status value
5622 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn
5623 * flag in the device to permit background operations if the device
5624 * bkops_status is greater than or equal to "status" argument passed to
5625 * this function, disable otherwise.
5627 * Returns 0 for success, non-zero in case of failure.
5629 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag
5630 * to know whether auto bkops is enabled or disabled after this function
5631 * returns control to it.
5633 static int ufshcd_bkops_ctrl(struct ufs_hba *hba,
5634 enum bkops_status status)
5637 u32 curr_status = 0;
5639 err = ufshcd_get_bkops_status(hba, &curr_status);
5641 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5644 } else if (curr_status > BKOPS_STATUS_MAX) {
5645 dev_err(hba->dev, "%s: invalid BKOPS status %d\n",
5646 __func__, curr_status);
5651 if (curr_status >= status)
5652 err = ufshcd_enable_auto_bkops(hba);
5654 err = ufshcd_disable_auto_bkops(hba);
5660 * ufshcd_urgent_bkops - handle urgent bkops exception event
5661 * @hba: per-adapter instance
5663 * Enable fBackgroundOpsEn flag in the device to permit background
5666 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled
5667 * and negative error value for any other failure.
5669 static int ufshcd_urgent_bkops(struct ufs_hba *hba)
5671 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl);
5674 static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status)
5676 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5677 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status);
5680 static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba)
5683 u32 curr_status = 0;
5685 if (hba->is_urgent_bkops_lvl_checked)
5686 goto enable_auto_bkops;
5688 err = ufshcd_get_bkops_status(hba, &curr_status);
5690 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n",
5696 * We are seeing that some devices are raising the urgent bkops
5697 * exception events even when BKOPS status doesn't indicate performace
5698 * impacted or critical. Handle these device by determining their urgent
5699 * bkops status at runtime.
5701 if (curr_status < BKOPS_STATUS_PERF_IMPACT) {
5702 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n",
5703 __func__, curr_status);
5704 /* update the current status as the urgent bkops level */
5705 hba->urgent_bkops_lvl = curr_status;
5706 hba->is_urgent_bkops_lvl_checked = true;
5710 err = ufshcd_enable_auto_bkops(hba);
5713 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n",
5717 static void ufshcd_temp_exception_event_handler(struct ufs_hba *hba, u16 status)
5721 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5722 QUERY_ATTR_IDN_CASE_ROUGH_TEMP, 0, 0, &value))
5725 dev_info(hba->dev, "exception Tcase %d\n", value - 80);
5727 ufs_hwmon_notify_event(hba, status & MASK_EE_URGENT_TEMP);
5730 * A placeholder for the platform vendors to add whatever additional
5735 static int __ufshcd_wb_toggle(struct ufs_hba *hba, bool set, enum flag_idn idn)
5738 enum query_opcode opcode = set ? UPIU_QUERY_OPCODE_SET_FLAG :
5739 UPIU_QUERY_OPCODE_CLEAR_FLAG;
5741 index = ufshcd_wb_get_query_index(hba);
5742 return ufshcd_query_flag_retry(hba, opcode, idn, index, NULL);
5745 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable)
5749 if (!ufshcd_is_wb_allowed(hba))
5752 if (!(enable ^ hba->dev_info.wb_enabled))
5755 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_EN);
5757 dev_err(hba->dev, "%s Write Booster %s failed %d\n",
5758 __func__, enable ? "enable" : "disable", ret);
5762 hba->dev_info.wb_enabled = enable;
5763 dev_dbg(hba->dev, "%s Write Booster %s\n",
5764 __func__, enable ? "enabled" : "disabled");
5769 static void ufshcd_wb_toggle_flush_during_h8(struct ufs_hba *hba, bool set)
5773 ret = __ufshcd_wb_toggle(hba, set,
5774 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8);
5776 dev_err(hba->dev, "%s: WB-Buf Flush during H8 %s failed: %d\n",
5777 __func__, set ? "enable" : "disable", ret);
5780 dev_dbg(hba->dev, "%s WB-Buf Flush during H8 %s\n",
5781 __func__, set ? "enabled" : "disabled");
5784 static inline void ufshcd_wb_toggle_flush(struct ufs_hba *hba, bool enable)
5788 if (!ufshcd_is_wb_allowed(hba) ||
5789 hba->dev_info.wb_buf_flush_enabled == enable)
5792 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN);
5794 dev_err(hba->dev, "%s WB-Buf Flush %s failed %d\n", __func__,
5795 enable ? "enable" : "disable", ret);
5799 hba->dev_info.wb_buf_flush_enabled = enable;
5801 dev_dbg(hba->dev, "%s WB-Buf Flush %s\n",
5802 __func__, enable ? "enabled" : "disabled");
5805 static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba,
5812 index = ufshcd_wb_get_query_index(hba);
5813 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5814 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE,
5815 index, 0, &cur_buf);
5817 dev_err(hba->dev, "%s dCurWriteBoosterBufferSize read failed %d\n",
5823 dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n",
5827 /* Let it continue to flush when available buffer exceeds threshold */
5828 return avail_buf < hba->vps->wb_flush_threshold;
5831 static void ufshcd_wb_force_disable(struct ufs_hba *hba)
5833 if (!(hba->quirks & UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL))
5834 ufshcd_wb_toggle_flush(hba, false);
5836 ufshcd_wb_toggle_flush_during_h8(hba, false);
5837 ufshcd_wb_toggle(hba, false);
5838 hba->caps &= ~UFSHCD_CAP_WB_EN;
5840 dev_info(hba->dev, "%s: WB force disabled\n", __func__);
5843 static bool ufshcd_is_wb_buf_lifetime_available(struct ufs_hba *hba)
5849 index = ufshcd_wb_get_query_index(hba);
5850 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5851 QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST,
5852 index, 0, &lifetime);
5855 "%s: bWriteBoosterBufferLifeTimeEst read failed %d\n",
5860 if (lifetime == UFS_WB_EXCEED_LIFETIME) {
5861 dev_err(hba->dev, "%s: WB buf lifetime is exhausted 0x%02X\n",
5862 __func__, lifetime);
5866 dev_dbg(hba->dev, "%s: WB buf lifetime is 0x%02X\n",
5867 __func__, lifetime);
5872 static bool ufshcd_wb_need_flush(struct ufs_hba *hba)
5878 if (!ufshcd_is_wb_allowed(hba))
5881 if (!ufshcd_is_wb_buf_lifetime_available(hba)) {
5882 ufshcd_wb_force_disable(hba);
5887 * The ufs device needs the vcc to be ON to flush.
5888 * With user-space reduction enabled, it's enough to enable flush
5889 * by checking only the available buffer. The threshold
5890 * defined here is > 90% full.
5891 * With user-space preserved enabled, the current-buffer
5892 * should be checked too because the wb buffer size can reduce
5893 * when disk tends to be full. This info is provided by current
5894 * buffer (dCurrentWriteBoosterBufferSize). There's no point in
5895 * keeping vcc on when current buffer is empty.
5897 index = ufshcd_wb_get_query_index(hba);
5898 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
5899 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE,
5900 index, 0, &avail_buf);
5902 dev_warn(hba->dev, "%s dAvailableWriteBoosterBufferSize read failed %d\n",
5907 if (!hba->dev_info.b_presrv_uspc_en)
5908 return avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10);
5910 return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf);
5913 static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work)
5915 struct ufs_hba *hba = container_of(to_delayed_work(work),
5917 rpm_dev_flush_recheck_work);
5919 * To prevent unnecessary VCC power drain after device finishes
5920 * WriteBooster buffer flush or Auto BKOPs, force runtime resume
5921 * after a certain delay to recheck the threshold by next runtime
5924 ufshcd_rpm_get_sync(hba);
5925 ufshcd_rpm_put_sync(hba);
5929 * ufshcd_exception_event_handler - handle exceptions raised by device
5930 * @work: pointer to work data
5932 * Read bExceptionEventStatus attribute from the device and handle the
5933 * exception event accordingly.
5935 static void ufshcd_exception_event_handler(struct work_struct *work)
5937 struct ufs_hba *hba;
5940 hba = container_of(work, struct ufs_hba, eeh_work);
5942 ufshcd_scsi_block_requests(hba);
5943 err = ufshcd_get_ee_status(hba, &status);
5945 dev_err(hba->dev, "%s: failed to get exception status %d\n",
5950 trace_ufshcd_exception_event(dev_name(hba->dev), status);
5952 if (status & hba->ee_drv_mask & MASK_EE_URGENT_BKOPS)
5953 ufshcd_bkops_exception_event_handler(hba);
5955 if (status & hba->ee_drv_mask & MASK_EE_URGENT_TEMP)
5956 ufshcd_temp_exception_event_handler(hba, status);
5958 ufs_debugfs_exception_event(hba, status);
5960 ufshcd_scsi_unblock_requests(hba);
5963 /* Complete requests that have door-bell cleared */
5964 static void ufshcd_complete_requests(struct ufs_hba *hba)
5966 ufshcd_transfer_req_compl(hba);
5967 ufshcd_tmc_handler(hba);
5971 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is
5972 * to recover from the DL NAC errors or not.
5973 * @hba: per-adapter instance
5975 * Returns true if error handling is required, false otherwise
5977 static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba)
5979 unsigned long flags;
5980 bool err_handling = true;
5982 spin_lock_irqsave(hba->host->host_lock, flags);
5984 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the
5985 * device fatal error and/or DL NAC & REPLAY timeout errors.
5987 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR))
5990 if ((hba->saved_err & DEVICE_FATAL_ERROR) ||
5991 ((hba->saved_err & UIC_ERROR) &&
5992 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))
5995 if ((hba->saved_err & UIC_ERROR) &&
5996 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) {
5999 * wait for 50ms to see if we can get any other errors or not.
6001 spin_unlock_irqrestore(hba->host->host_lock, flags);
6003 spin_lock_irqsave(hba->host->host_lock, flags);
6006 * now check if we have got any other severe errors other than
6009 if ((hba->saved_err & INT_FATAL_ERRORS) ||
6010 ((hba->saved_err & UIC_ERROR) &&
6011 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)))
6015 * As DL NAC is the only error received so far, send out NOP
6016 * command to confirm if link is still active or not.
6017 * - If we don't get any response then do error recovery.
6018 * - If we get response then clear the DL NAC error bit.
6021 spin_unlock_irqrestore(hba->host->host_lock, flags);
6022 err = ufshcd_verify_dev_init(hba);
6023 spin_lock_irqsave(hba->host->host_lock, flags);
6028 /* Link seems to be alive hence ignore the DL NAC errors */
6029 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)
6030 hba->saved_err &= ~UIC_ERROR;
6031 /* clear NAC error */
6032 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
6033 if (!hba->saved_uic_err)
6034 err_handling = false;
6037 spin_unlock_irqrestore(hba->host->host_lock, flags);
6038 return err_handling;
6041 /* host lock must be held before calling this func */
6042 static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba)
6044 return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) ||
6045 (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK));
6048 void ufshcd_schedule_eh_work(struct ufs_hba *hba)
6050 lockdep_assert_held(hba->host->host_lock);
6052 /* handle fatal errors only when link is not in error state */
6053 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) {
6054 if (hba->force_reset || ufshcd_is_link_broken(hba) ||
6055 ufshcd_is_saved_err_fatal(hba))
6056 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL;
6058 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL;
6059 queue_work(hba->eh_wq, &hba->eh_work);
6063 static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow)
6065 down_write(&hba->clk_scaling_lock);
6066 hba->clk_scaling.is_allowed = allow;
6067 up_write(&hba->clk_scaling_lock);
6070 static void ufshcd_clk_scaling_suspend(struct ufs_hba *hba, bool suspend)
6073 if (hba->clk_scaling.is_enabled)
6074 ufshcd_suspend_clkscaling(hba);
6075 ufshcd_clk_scaling_allow(hba, false);
6077 ufshcd_clk_scaling_allow(hba, true);
6078 if (hba->clk_scaling.is_enabled)
6079 ufshcd_resume_clkscaling(hba);
6083 static void ufshcd_err_handling_prepare(struct ufs_hba *hba)
6085 ufshcd_rpm_get_sync(hba);
6086 if (pm_runtime_status_suspended(&hba->ufs_device_wlun->sdev_gendev) ||
6087 hba->is_sys_suspended) {
6088 enum ufs_pm_op pm_op;
6091 * Don't assume anything of resume, if
6092 * resume fails, irq and clocks can be OFF, and powers
6093 * can be OFF or in LPM.
6095 ufshcd_setup_hba_vreg(hba, true);
6096 ufshcd_enable_irq(hba);
6097 ufshcd_setup_vreg(hba, true);
6098 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
6099 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
6100 ufshcd_hold(hba, false);
6101 if (!ufshcd_is_clkgating_allowed(hba))
6102 ufshcd_setup_clocks(hba, true);
6103 ufshcd_release(hba);
6104 pm_op = hba->is_sys_suspended ? UFS_SYSTEM_PM : UFS_RUNTIME_PM;
6105 ufshcd_vops_resume(hba, pm_op);
6107 ufshcd_hold(hba, false);
6108 if (ufshcd_is_clkscaling_supported(hba) &&
6109 hba->clk_scaling.is_enabled)
6110 ufshcd_suspend_clkscaling(hba);
6111 ufshcd_clk_scaling_allow(hba, false);
6113 ufshcd_scsi_block_requests(hba);
6114 /* Drain ufshcd_queuecommand() */
6116 cancel_work_sync(&hba->eeh_work);
6119 static void ufshcd_err_handling_unprepare(struct ufs_hba *hba)
6121 ufshcd_scsi_unblock_requests(hba);
6122 ufshcd_release(hba);
6123 if (ufshcd_is_clkscaling_supported(hba))
6124 ufshcd_clk_scaling_suspend(hba, false);
6125 ufshcd_rpm_put(hba);
6128 static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba)
6130 return (!hba->is_powered || hba->shutting_down ||
6131 !hba->ufs_device_wlun ||
6132 hba->ufshcd_state == UFSHCD_STATE_ERROR ||
6133 (!(hba->saved_err || hba->saved_uic_err || hba->force_reset ||
6134 ufshcd_is_link_broken(hba))));
6138 static void ufshcd_recover_pm_error(struct ufs_hba *hba)
6140 struct Scsi_Host *shost = hba->host;
6141 struct scsi_device *sdev;
6142 struct request_queue *q;
6145 hba->is_sys_suspended = false;
6147 * Set RPM status of wlun device to RPM_ACTIVE,
6148 * this also clears its runtime error.
6150 ret = pm_runtime_set_active(&hba->ufs_device_wlun->sdev_gendev);
6152 /* hba device might have a runtime error otherwise */
6154 ret = pm_runtime_set_active(hba->dev);
6156 * If wlun device had runtime error, we also need to resume those
6157 * consumer scsi devices in case any of them has failed to be
6158 * resumed due to supplier runtime resume failure. This is to unblock
6159 * blk_queue_enter in case there are bios waiting inside it.
6162 shost_for_each_device(sdev, shost) {
6163 q = sdev->request_queue;
6164 if (q->dev && (q->rpm_status == RPM_SUSPENDED ||
6165 q->rpm_status == RPM_SUSPENDING))
6166 pm_request_resume(q->dev);
6171 static inline void ufshcd_recover_pm_error(struct ufs_hba *hba)
6176 static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba)
6178 struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info;
6181 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode);
6183 if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK))
6186 if (pwr_info->pwr_tx != (mode & PWRMODE_MASK))
6193 * ufshcd_err_handler - handle UFS errors that require s/w attention
6194 * @work: pointer to work structure
6196 static void ufshcd_err_handler(struct work_struct *work)
6198 int retries = MAX_ERR_HANDLER_RETRIES;
6199 struct ufs_hba *hba;
6200 unsigned long flags;
6208 hba = container_of(work, struct ufs_hba, eh_work);
6211 "%s started; HBA state %s; powered %d; shutting down %d; saved_err = %d; saved_uic_err = %d; force_reset = %d%s\n",
6212 __func__, ufshcd_state_name[hba->ufshcd_state],
6213 hba->is_powered, hba->shutting_down, hba->saved_err,
6214 hba->saved_uic_err, hba->force_reset,
6215 ufshcd_is_link_broken(hba) ? "; link is broken" : "");
6217 down(&hba->host_sem);
6218 spin_lock_irqsave(hba->host->host_lock, flags);
6219 if (ufshcd_err_handling_should_stop(hba)) {
6220 if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
6221 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6222 spin_unlock_irqrestore(hba->host->host_lock, flags);
6226 ufshcd_set_eh_in_progress(hba);
6227 spin_unlock_irqrestore(hba->host->host_lock, flags);
6228 ufshcd_err_handling_prepare(hba);
6229 /* Complete requests that have door-bell cleared by h/w */
6230 ufshcd_complete_requests(hba);
6231 spin_lock_irqsave(hba->host->host_lock, flags);
6233 needs_restore = false;
6234 needs_reset = false;
6238 if (hba->ufshcd_state != UFSHCD_STATE_ERROR)
6239 hba->ufshcd_state = UFSHCD_STATE_RESET;
6241 * A full reset and restore might have happened after preparation
6242 * is finished, double check whether we should stop.
6244 if (ufshcd_err_handling_should_stop(hba))
6245 goto skip_err_handling;
6247 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
6250 spin_unlock_irqrestore(hba->host->host_lock, flags);
6251 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */
6252 ret = ufshcd_quirk_dl_nac_errors(hba);
6253 spin_lock_irqsave(hba->host->host_lock, flags);
6254 if (!ret && ufshcd_err_handling_should_stop(hba))
6255 goto skip_err_handling;
6258 if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
6259 (hba->saved_uic_err &&
6260 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
6261 bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR);
6263 spin_unlock_irqrestore(hba->host->host_lock, flags);
6264 ufshcd_print_host_state(hba);
6265 ufshcd_print_pwr_info(hba);
6266 ufshcd_print_evt_hist(hba);
6267 ufshcd_print_tmrs(hba, hba->outstanding_tasks);
6268 ufshcd_print_trs(hba, hba->outstanding_reqs, pr_prdt);
6269 spin_lock_irqsave(hba->host->host_lock, flags);
6273 * if host reset is required then skip clearing the pending
6274 * transfers forcefully because they will get cleared during
6275 * host reset and restore
6277 if (hba->force_reset || ufshcd_is_link_broken(hba) ||
6278 ufshcd_is_saved_err_fatal(hba) ||
6279 ((hba->saved_err & UIC_ERROR) &&
6280 (hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR |
6281 UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) {
6287 * If LINERESET was caught, UFS might have been put to PWM mode,
6288 * check if power mode restore is needed.
6290 if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) {
6291 hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6292 if (!hba->saved_uic_err)
6293 hba->saved_err &= ~UIC_ERROR;
6294 spin_unlock_irqrestore(hba->host->host_lock, flags);
6295 if (ufshcd_is_pwr_mode_restore_needed(hba))
6296 needs_restore = true;
6297 spin_lock_irqsave(hba->host->host_lock, flags);
6298 if (!hba->saved_err && !needs_restore)
6299 goto skip_err_handling;
6302 hba->silence_err_logs = true;
6303 /* release lock as clear command might sleep */
6304 spin_unlock_irqrestore(hba->host->host_lock, flags);
6305 /* Clear pending transfer requests */
6306 for_each_set_bit(tag, &hba->outstanding_reqs, hba->nutrs) {
6307 if (ufshcd_try_to_abort_task(hba, tag)) {
6309 goto lock_skip_pending_xfer_clear;
6311 dev_err(hba->dev, "Aborted tag %d / CDB %#02x\n", tag,
6312 hba->lrb[tag].cmd ? hba->lrb[tag].cmd->cmnd[0] : -1);
6315 /* Clear pending task management requests */
6316 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) {
6317 if (ufshcd_clear_tm_cmd(hba, tag)) {
6319 goto lock_skip_pending_xfer_clear;
6323 lock_skip_pending_xfer_clear:
6324 /* Complete the requests that are cleared by s/w */
6325 ufshcd_complete_requests(hba);
6327 spin_lock_irqsave(hba->host->host_lock, flags);
6328 hba->silence_err_logs = false;
6329 if (err_xfer || err_tm) {
6335 * After all reqs and tasks are cleared from doorbell,
6336 * now it is safe to retore power mode.
6338 if (needs_restore) {
6339 spin_unlock_irqrestore(hba->host->host_lock, flags);
6341 * Hold the scaling lock just in case dev cmds
6342 * are sent via bsg and/or sysfs.
6344 down_write(&hba->clk_scaling_lock);
6345 hba->force_pmc = true;
6346 pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info));
6349 dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n",
6352 hba->force_pmc = false;
6353 ufshcd_print_pwr_info(hba);
6354 up_write(&hba->clk_scaling_lock);
6355 spin_lock_irqsave(hba->host->host_lock, flags);
6359 /* Fatal errors need reset */
6363 hba->force_reset = false;
6364 spin_unlock_irqrestore(hba->host->host_lock, flags);
6365 err = ufshcd_reset_and_restore(hba);
6367 dev_err(hba->dev, "%s: reset and restore failed with err %d\n",
6370 ufshcd_recover_pm_error(hba);
6371 spin_lock_irqsave(hba->host->host_lock, flags);
6376 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
6377 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
6378 if (hba->saved_err || hba->saved_uic_err)
6379 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x",
6380 __func__, hba->saved_err, hba->saved_uic_err);
6382 /* Exit in an operational state or dead */
6383 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL &&
6384 hba->ufshcd_state != UFSHCD_STATE_ERROR) {
6387 hba->ufshcd_state = UFSHCD_STATE_ERROR;
6389 ufshcd_clear_eh_in_progress(hba);
6390 spin_unlock_irqrestore(hba->host->host_lock, flags);
6391 ufshcd_err_handling_unprepare(hba);
6394 dev_info(hba->dev, "%s finished; HBA state %s\n", __func__,
6395 ufshcd_state_name[hba->ufshcd_state]);
6399 * ufshcd_update_uic_error - check and set fatal UIC error flags.
6400 * @hba: per-adapter instance
6403 * IRQ_HANDLED - If interrupt is valid
6404 * IRQ_NONE - If invalid interrupt
6406 static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba)
6409 irqreturn_t retval = IRQ_NONE;
6411 /* PHY layer error */
6412 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
6413 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) &&
6414 (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) {
6415 ufshcd_update_evt_hist(hba, UFS_EVT_PA_ERR, reg);
6417 * To know whether this error is fatal or not, DB timeout
6418 * must be checked but this error is handled separately.
6420 if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK)
6421 dev_dbg(hba->dev, "%s: UIC Lane error reported\n",
6424 /* Got a LINERESET indication. */
6425 if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) {
6426 struct uic_command *cmd = NULL;
6428 hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR;
6429 if (hba->uic_async_done && hba->active_uic_cmd)
6430 cmd = hba->active_uic_cmd;
6432 * Ignore the LINERESET during power mode change
6433 * operation via DME_SET command.
6435 if (cmd && (cmd->command == UIC_CMD_DME_SET))
6436 hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR;
6438 retval |= IRQ_HANDLED;
6441 /* PA_INIT_ERROR is fatal and needs UIC reset */
6442 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER);
6443 if ((reg & UIC_DATA_LINK_LAYER_ERROR) &&
6444 (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) {
6445 ufshcd_update_evt_hist(hba, UFS_EVT_DL_ERR, reg);
6447 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
6448 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR;
6449 else if (hba->dev_quirks &
6450 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) {
6451 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED)
6453 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR;
6454 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT)
6455 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR;
6457 retval |= IRQ_HANDLED;
6460 /* UIC NL/TL/DME errors needs software retry */
6461 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER);
6462 if ((reg & UIC_NETWORK_LAYER_ERROR) &&
6463 (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) {
6464 ufshcd_update_evt_hist(hba, UFS_EVT_NL_ERR, reg);
6465 hba->uic_error |= UFSHCD_UIC_NL_ERROR;
6466 retval |= IRQ_HANDLED;
6469 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER);
6470 if ((reg & UIC_TRANSPORT_LAYER_ERROR) &&
6471 (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) {
6472 ufshcd_update_evt_hist(hba, UFS_EVT_TL_ERR, reg);
6473 hba->uic_error |= UFSHCD_UIC_TL_ERROR;
6474 retval |= IRQ_HANDLED;
6477 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME);
6478 if ((reg & UIC_DME_ERROR) &&
6479 (reg & UIC_DME_ERROR_CODE_MASK)) {
6480 ufshcd_update_evt_hist(hba, UFS_EVT_DME_ERR, reg);
6481 hba->uic_error |= UFSHCD_UIC_DME_ERROR;
6482 retval |= IRQ_HANDLED;
6485 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n",
6486 __func__, hba->uic_error);
6491 * ufshcd_check_errors - Check for errors that need s/w attention
6492 * @hba: per-adapter instance
6493 * @intr_status: interrupt status generated by the controller
6496 * IRQ_HANDLED - If interrupt is valid
6497 * IRQ_NONE - If invalid interrupt
6499 static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status)
6501 bool queue_eh_work = false;
6502 irqreturn_t retval = IRQ_NONE;
6504 spin_lock(hba->host->host_lock);
6505 hba->errors |= UFSHCD_ERROR_MASK & intr_status;
6507 if (hba->errors & INT_FATAL_ERRORS) {
6508 ufshcd_update_evt_hist(hba, UFS_EVT_FATAL_ERR,
6510 queue_eh_work = true;
6513 if (hba->errors & UIC_ERROR) {
6515 retval = ufshcd_update_uic_error(hba);
6517 queue_eh_work = true;
6520 if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) {
6522 "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n",
6523 __func__, (hba->errors & UIC_HIBERNATE_ENTER) ?
6525 hba->errors, ufshcd_get_upmcrs(hba));
6526 ufshcd_update_evt_hist(hba, UFS_EVT_AUTO_HIBERN8_ERR,
6528 ufshcd_set_link_broken(hba);
6529 queue_eh_work = true;
6532 if (queue_eh_work) {
6534 * update the transfer error masks to sticky bits, let's do this
6535 * irrespective of current ufshcd_state.
6537 hba->saved_err |= hba->errors;
6538 hba->saved_uic_err |= hba->uic_error;
6540 /* dump controller state before resetting */
6541 if ((hba->saved_err &
6542 (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) ||
6543 (hba->saved_uic_err &&
6544 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) {
6545 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n",
6546 __func__, hba->saved_err,
6547 hba->saved_uic_err);
6548 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE,
6550 ufshcd_print_pwr_info(hba);
6552 ufshcd_schedule_eh_work(hba);
6553 retval |= IRQ_HANDLED;
6556 * if (!queue_eh_work) -
6557 * Other errors are either non-fatal where host recovers
6558 * itself without s/w intervention or errors that will be
6559 * handled by the SCSI core layer.
6563 spin_unlock(hba->host->host_lock);
6568 * ufshcd_tmc_handler - handle task management function completion
6569 * @hba: per adapter instance
6572 * IRQ_HANDLED - If interrupt is valid
6573 * IRQ_NONE - If invalid interrupt
6575 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba)
6577 unsigned long flags, pending, issued;
6578 irqreturn_t ret = IRQ_NONE;
6581 spin_lock_irqsave(hba->host->host_lock, flags);
6582 pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL);
6583 issued = hba->outstanding_tasks & ~pending;
6584 for_each_set_bit(tag, &issued, hba->nutmrs) {
6585 struct request *req = hba->tmf_rqs[tag];
6586 struct completion *c = req->end_io_data;
6591 spin_unlock_irqrestore(hba->host->host_lock, flags);
6597 * ufshcd_sl_intr - Interrupt service routine
6598 * @hba: per adapter instance
6599 * @intr_status: contains interrupts generated by the controller
6602 * IRQ_HANDLED - If interrupt is valid
6603 * IRQ_NONE - If invalid interrupt
6605 static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
6607 irqreturn_t retval = IRQ_NONE;
6609 if (intr_status & UFSHCD_UIC_MASK)
6610 retval |= ufshcd_uic_cmd_compl(hba, intr_status);
6612 if (intr_status & UFSHCD_ERROR_MASK || hba->errors)
6613 retval |= ufshcd_check_errors(hba, intr_status);
6615 if (intr_status & UTP_TASK_REQ_COMPL)
6616 retval |= ufshcd_tmc_handler(hba);
6618 if (intr_status & UTP_TRANSFER_REQ_COMPL)
6619 retval |= ufshcd_transfer_req_compl(hba);
6625 * ufshcd_intr - Main interrupt service routine
6627 * @__hba: pointer to adapter instance
6630 * IRQ_HANDLED - If interrupt is valid
6631 * IRQ_NONE - If invalid interrupt
6633 static irqreturn_t ufshcd_intr(int irq, void *__hba)
6635 u32 intr_status, enabled_intr_status = 0;
6636 irqreturn_t retval = IRQ_NONE;
6637 struct ufs_hba *hba = __hba;
6638 int retries = hba->nutrs;
6640 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
6641 hba->ufs_stats.last_intr_status = intr_status;
6642 hba->ufs_stats.last_intr_ts = ktime_get();
6645 * There could be max of hba->nutrs reqs in flight and in worst case
6646 * if the reqs get finished 1 by 1 after the interrupt status is
6647 * read, make sure we handle them by checking the interrupt status
6648 * again in a loop until we process all of the reqs before returning.
6650 while (intr_status && retries--) {
6651 enabled_intr_status =
6652 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
6653 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
6654 if (enabled_intr_status)
6655 retval |= ufshcd_sl_intr(hba, enabled_intr_status);
6657 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
6660 if (enabled_intr_status && retval == IRQ_NONE &&
6661 (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL) ||
6662 hba->outstanding_reqs) && !ufshcd_eh_in_progress(hba)) {
6663 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x (0x%08x, 0x%08x)\n",
6666 hba->ufs_stats.last_intr_status,
6667 enabled_intr_status);
6668 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: ");
6674 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag)
6677 u32 mask = 1 << tag;
6678 unsigned long flags;
6680 if (!test_bit(tag, &hba->outstanding_tasks))
6683 spin_lock_irqsave(hba->host->host_lock, flags);
6684 ufshcd_utmrl_clear(hba, tag);
6685 spin_unlock_irqrestore(hba->host->host_lock, flags);
6687 /* poll for max. 1 sec to clear door bell register by h/w */
6688 err = ufshcd_wait_for_register(hba,
6689 REG_UTP_TASK_REQ_DOOR_BELL,
6690 mask, 0, 1000, 1000);
6692 dev_err(hba->dev, "Clearing task management function with tag %d %s\n",
6693 tag, err ? "succeeded" : "failed");
6699 static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba,
6700 struct utp_task_req_desc *treq, u8 tm_function)
6702 struct request_queue *q = hba->tmf_queue;
6703 struct Scsi_Host *host = hba->host;
6704 DECLARE_COMPLETION_ONSTACK(wait);
6705 struct request *req;
6706 unsigned long flags;
6710 * blk_mq_alloc_request() is used here only to get a free tag.
6712 req = blk_mq_alloc_request(q, REQ_OP_DRV_OUT, 0);
6714 return PTR_ERR(req);
6716 req->end_io_data = &wait;
6717 ufshcd_hold(hba, false);
6719 spin_lock_irqsave(host->host_lock, flags);
6721 task_tag = req->tag;
6722 WARN_ONCE(task_tag < 0 || task_tag >= hba->nutmrs, "Invalid tag %d\n",
6724 hba->tmf_rqs[req->tag] = req;
6725 treq->upiu_req.req_header.dword_0 |= cpu_to_be32(task_tag);
6727 memcpy(hba->utmrdl_base_addr + task_tag, treq, sizeof(*treq));
6728 ufshcd_vops_setup_task_mgmt(hba, task_tag, tm_function);
6730 /* send command to the controller */
6731 __set_bit(task_tag, &hba->outstanding_tasks);
6733 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL);
6734 /* Make sure that doorbell is committed immediately */
6737 spin_unlock_irqrestore(host->host_lock, flags);
6739 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_SEND);
6741 /* wait until the task management command is completed */
6742 err = wait_for_completion_io_timeout(&wait,
6743 msecs_to_jiffies(TM_CMD_TIMEOUT));
6745 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_ERR);
6746 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n",
6747 __func__, tm_function);
6748 if (ufshcd_clear_tm_cmd(hba, task_tag))
6749 dev_WARN(hba->dev, "%s: unable to clear tm cmd (slot %d) after timeout\n",
6750 __func__, task_tag);
6754 memcpy(treq, hba->utmrdl_base_addr + task_tag, sizeof(*treq));
6756 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_COMP);
6759 spin_lock_irqsave(hba->host->host_lock, flags);
6760 hba->tmf_rqs[req->tag] = NULL;
6761 __clear_bit(task_tag, &hba->outstanding_tasks);
6762 spin_unlock_irqrestore(hba->host->host_lock, flags);
6764 ufshcd_release(hba);
6765 blk_mq_free_request(req);
6771 * ufshcd_issue_tm_cmd - issues task management commands to controller
6772 * @hba: per adapter instance
6773 * @lun_id: LUN ID to which TM command is sent
6774 * @task_id: task ID to which the TM command is applicable
6775 * @tm_function: task management function opcode
6776 * @tm_response: task management service response return value
6778 * Returns non-zero value on error, zero on success.
6780 static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id,
6781 u8 tm_function, u8 *tm_response)
6783 struct utp_task_req_desc treq = { { 0 }, };
6784 enum utp_ocs ocs_value;
6787 /* Configure task request descriptor */
6788 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
6789 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
6791 /* Configure task request UPIU */
6792 treq.upiu_req.req_header.dword_0 = cpu_to_be32(lun_id << 8) |
6793 cpu_to_be32(UPIU_TRANSACTION_TASK_REQ << 24);
6794 treq.upiu_req.req_header.dword_1 = cpu_to_be32(tm_function << 16);
6797 * The host shall provide the same value for LUN field in the basic
6798 * header and for Input Parameter.
6800 treq.upiu_req.input_param1 = cpu_to_be32(lun_id);
6801 treq.upiu_req.input_param2 = cpu_to_be32(task_id);
6803 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function);
6804 if (err == -ETIMEDOUT)
6807 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
6808 if (ocs_value != OCS_SUCCESS)
6809 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n",
6810 __func__, ocs_value);
6811 else if (tm_response)
6812 *tm_response = be32_to_cpu(treq.upiu_rsp.output_param1) &
6813 MASK_TM_SERVICE_RESP;
6818 * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests
6819 * @hba: per-adapter instance
6820 * @req_upiu: upiu request
6821 * @rsp_upiu: upiu reply
6822 * @desc_buff: pointer to descriptor buffer, NULL if NA
6823 * @buff_len: descriptor size, 0 if NA
6824 * @cmd_type: specifies the type (NOP, Query...)
6825 * @desc_op: descriptor operation
6827 * Those type of requests uses UTP Transfer Request Descriptor - utrd.
6828 * Therefore, it "rides" the device management infrastructure: uses its tag and
6829 * tasks work queues.
6831 * Since there is only one available tag for device management commands,
6832 * the caller is expected to hold the hba->dev_cmd.lock mutex.
6834 static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba,
6835 struct utp_upiu_req *req_upiu,
6836 struct utp_upiu_req *rsp_upiu,
6837 u8 *desc_buff, int *buff_len,
6838 enum dev_cmd_type cmd_type,
6839 enum query_opcode desc_op)
6841 DECLARE_COMPLETION_ONSTACK(wait);
6842 const u32 tag = hba->reserved_slot;
6843 struct ufshcd_lrb *lrbp;
6847 /* Protects use of hba->reserved_slot. */
6848 lockdep_assert_held(&hba->dev_cmd.lock);
6850 down_read(&hba->clk_scaling_lock);
6852 lrbp = &hba->lrb[tag];
6855 lrbp->task_tag = tag;
6857 lrbp->intr_cmd = true;
6858 ufshcd_prepare_lrbp_crypto(NULL, lrbp);
6859 hba->dev_cmd.type = cmd_type;
6861 if (hba->ufs_version <= ufshci_version(1, 1))
6862 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE;
6864 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE;
6866 /* update the task tag in the request upiu */
6867 req_upiu->header.dword_0 |= cpu_to_be32(tag);
6869 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE);
6871 /* just copy the upiu request as it is */
6872 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr));
6873 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) {
6874 /* The Data Segment Area is optional depending upon the query
6875 * function value. for WRITE DESCRIPTOR, the data segment
6876 * follows right after the tsf.
6878 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len);
6882 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
6884 hba->dev_cmd.complete = &wait;
6886 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr);
6888 ufshcd_send_command(hba, tag);
6890 * ignore the returning value here - ufshcd_check_query_response is
6891 * bound to fail since dev_cmd.query and dev_cmd.type were left empty.
6892 * read the response directly ignoring all errors.
6894 ufshcd_wait_for_dev_cmd(hba, lrbp, QUERY_REQ_TIMEOUT);
6896 /* just copy the upiu response as it is */
6897 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu));
6898 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) {
6899 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu);
6900 u16 resp_len = be32_to_cpu(lrbp->ucd_rsp_ptr->header.dword_2) &
6901 MASK_QUERY_DATA_SEG_LEN;
6903 if (*buff_len >= resp_len) {
6904 memcpy(desc_buff, descp, resp_len);
6905 *buff_len = resp_len;
6908 "%s: rsp size %d is bigger than buffer size %d",
6909 __func__, resp_len, *buff_len);
6914 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP,
6915 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr);
6917 up_read(&hba->clk_scaling_lock);
6922 * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands
6923 * @hba: per-adapter instance
6924 * @req_upiu: upiu request
6925 * @rsp_upiu: upiu reply - only 8 DW as we do not support scsi commands
6926 * @msgcode: message code, one of UPIU Transaction Codes Initiator to Target
6927 * @desc_buff: pointer to descriptor buffer, NULL if NA
6928 * @buff_len: descriptor size, 0 if NA
6929 * @desc_op: descriptor operation
6931 * Supports UTP Transfer requests (nop and query), and UTP Task
6932 * Management requests.
6933 * It is up to the caller to fill the upiu conent properly, as it will
6934 * be copied without any further input validations.
6936 int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
6937 struct utp_upiu_req *req_upiu,
6938 struct utp_upiu_req *rsp_upiu,
6940 u8 *desc_buff, int *buff_len,
6941 enum query_opcode desc_op)
6944 enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY;
6945 struct utp_task_req_desc treq = { { 0 }, };
6946 enum utp_ocs ocs_value;
6947 u8 tm_f = be32_to_cpu(req_upiu->header.dword_1) >> 16 & MASK_TM_FUNC;
6950 case UPIU_TRANSACTION_NOP_OUT:
6951 cmd_type = DEV_CMD_TYPE_NOP;
6953 case UPIU_TRANSACTION_QUERY_REQ:
6954 ufshcd_hold(hba, false);
6955 mutex_lock(&hba->dev_cmd.lock);
6956 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu,
6957 desc_buff, buff_len,
6959 mutex_unlock(&hba->dev_cmd.lock);
6960 ufshcd_release(hba);
6963 case UPIU_TRANSACTION_TASK_REQ:
6964 treq.header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
6965 treq.header.dword_2 = cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
6967 memcpy(&treq.upiu_req, req_upiu, sizeof(*req_upiu));
6969 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f);
6970 if (err == -ETIMEDOUT)
6973 ocs_value = le32_to_cpu(treq.header.dword_2) & MASK_OCS;
6974 if (ocs_value != OCS_SUCCESS) {
6975 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__,
6980 memcpy(rsp_upiu, &treq.upiu_rsp, sizeof(*rsp_upiu));
6993 * ufshcd_eh_device_reset_handler() - Reset a single logical unit.
6994 * @cmd: SCSI command pointer
6996 * Returns SUCCESS/FAILED
6998 static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd)
7000 unsigned long flags, pending_reqs = 0, not_cleared = 0;
7001 struct Scsi_Host *host;
7002 struct ufs_hba *hba;
7007 host = cmd->device->host;
7008 hba = shost_priv(host);
7010 lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun);
7011 err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp);
7012 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
7018 /* clear the commands that were pending for corresponding LUN */
7019 spin_lock_irqsave(&hba->outstanding_lock, flags);
7020 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs)
7021 if (hba->lrb[pos].lun == lun)
7022 __set_bit(pos, &pending_reqs);
7023 hba->outstanding_reqs &= ~pending_reqs;
7024 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
7026 if (ufshcd_clear_cmds(hba, pending_reqs) < 0) {
7027 spin_lock_irqsave(&hba->outstanding_lock, flags);
7028 not_cleared = pending_reqs &
7029 ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7030 hba->outstanding_reqs |= not_cleared;
7031 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
7033 dev_err(hba->dev, "%s: failed to clear requests %#lx\n",
7034 __func__, not_cleared);
7036 __ufshcd_transfer_req_compl(hba, pending_reqs & ~not_cleared);
7039 hba->req_abort_count = 0;
7040 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, (u32)err);
7044 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
7050 static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap)
7052 struct ufshcd_lrb *lrbp;
7055 for_each_set_bit(tag, &bitmap, hba->nutrs) {
7056 lrbp = &hba->lrb[tag];
7057 lrbp->req_abort_skip = true;
7062 * ufshcd_try_to_abort_task - abort a specific task
7063 * @hba: Pointer to adapter instance
7064 * @tag: Task tag/index to be aborted
7066 * Abort the pending command in device by sending UFS_ABORT_TASK task management
7067 * command, and in host controller by clearing the door-bell register. There can
7068 * be race between controller sending the command to the device while abort is
7069 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is
7070 * really issued and then try to abort it.
7072 * Returns zero on success, non-zero on failure
7074 static int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag)
7076 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
7082 for (poll_cnt = 100; poll_cnt; poll_cnt--) {
7083 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
7084 UFS_QUERY_TASK, &resp);
7085 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) {
7086 /* cmd pending in the device */
7087 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n",
7090 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
7092 * cmd not pending in the device, check if it is
7095 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n",
7097 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7098 if (reg & (1 << tag)) {
7099 /* sleep for max. 200us to stabilize */
7100 usleep_range(100, 200);
7103 /* command completed already */
7104 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n",
7109 "%s: no response from device. tag = %d, err %d\n",
7110 __func__, tag, err);
7112 err = resp; /* service response error */
7122 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag,
7123 UFS_ABORT_TASK, &resp);
7124 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) {
7126 err = resp; /* service response error */
7127 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n",
7128 __func__, tag, err);
7133 err = ufshcd_clear_cmds(hba, 1U << tag);
7135 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n",
7136 __func__, tag, err);
7143 * ufshcd_abort - scsi host template eh_abort_handler callback
7144 * @cmd: SCSI command pointer
7146 * Returns SUCCESS/FAILED
7148 static int ufshcd_abort(struct scsi_cmnd *cmd)
7150 struct Scsi_Host *host = cmd->device->host;
7151 struct ufs_hba *hba = shost_priv(host);
7152 int tag = scsi_cmd_to_rq(cmd)->tag;
7153 struct ufshcd_lrb *lrbp = &hba->lrb[tag];
7154 unsigned long flags;
7159 WARN_ONCE(tag < 0, "Invalid tag %d\n", tag);
7161 ufshcd_hold(hba, false);
7162 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
7163 /* If command is already aborted/completed, return FAILED. */
7164 if (!(test_bit(tag, &hba->outstanding_reqs))) {
7166 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n",
7167 __func__, tag, hba->outstanding_reqs, reg);
7171 /* Print Transfer Request of aborted task */
7172 dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag);
7175 * Print detailed info about aborted request.
7176 * As more than one request might get aborted at the same time,
7177 * print full information only for the first aborted request in order
7178 * to reduce repeated printouts. For other aborted requests only print
7181 scsi_print_command(cmd);
7182 if (!hba->req_abort_count) {
7183 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, tag);
7184 ufshcd_print_evt_hist(hba);
7185 ufshcd_print_host_state(hba);
7186 ufshcd_print_pwr_info(hba);
7187 ufshcd_print_trs(hba, 1 << tag, true);
7189 ufshcd_print_trs(hba, 1 << tag, false);
7191 hba->req_abort_count++;
7193 if (!(reg & (1 << tag))) {
7195 "%s: cmd was completed, but without a notifying intr, tag = %d",
7197 __ufshcd_transfer_req_compl(hba, 1UL << tag);
7202 * Task abort to the device W-LUN is illegal. When this command
7203 * will fail, due to spec violation, scsi err handling next step
7204 * will be to send LU reset which, again, is a spec violation.
7205 * To avoid these unnecessary/illegal steps, first we clean up
7206 * the lrb taken by this cmd and re-set it in outstanding_reqs,
7207 * then queue the eh_work and bail.
7209 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) {
7210 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun);
7212 spin_lock_irqsave(host->host_lock, flags);
7213 hba->force_reset = true;
7214 ufshcd_schedule_eh_work(hba);
7215 spin_unlock_irqrestore(host->host_lock, flags);
7219 /* Skip task abort in case previous aborts failed and report failure */
7220 if (lrbp->req_abort_skip) {
7221 dev_err(hba->dev, "%s: skipping abort\n", __func__);
7222 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
7226 err = ufshcd_try_to_abort_task(hba, tag);
7228 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err);
7229 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs);
7235 * Clear the corresponding bit from outstanding_reqs since the command
7236 * has been aborted successfully.
7238 spin_lock_irqsave(&hba->outstanding_lock, flags);
7239 outstanding = __test_and_clear_bit(tag, &hba->outstanding_reqs);
7240 spin_unlock_irqrestore(&hba->outstanding_lock, flags);
7243 ufshcd_release_scsi_cmd(hba, lrbp);
7248 /* Matches the ufshcd_hold() call at the start of this function. */
7249 ufshcd_release(hba);
7254 * ufshcd_host_reset_and_restore - reset and restore host controller
7255 * @hba: per-adapter instance
7257 * Note that host controller reset may issue DME_RESET to
7258 * local and remote (device) Uni-Pro stack and the attributes
7259 * are reset to default state.
7261 * Returns zero on success, non-zero on failure
7263 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba)
7268 * Stop the host controller and complete the requests
7271 ufshpb_toggle_state(hba, HPB_PRESENT, HPB_RESET);
7272 ufshcd_hba_stop(hba);
7273 hba->silence_err_logs = true;
7274 ufshcd_complete_requests(hba);
7275 hba->silence_err_logs = false;
7277 /* scale up clocks to max frequency before full reinitialization */
7278 ufshcd_scale_clks(hba, true);
7280 err = ufshcd_hba_enable(hba);
7282 /* Establish the link again and restore the device */
7284 err = ufshcd_probe_hba(hba, false);
7287 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err);
7288 ufshcd_update_evt_hist(hba, UFS_EVT_HOST_RESET, (u32)err);
7293 * ufshcd_reset_and_restore - reset and re-initialize host/device
7294 * @hba: per-adapter instance
7296 * Reset and recover device, host and re-establish link. This
7297 * is helpful to recover the communication in fatal error conditions.
7299 * Returns zero on success, non-zero on failure
7301 static int ufshcd_reset_and_restore(struct ufs_hba *hba)
7304 u32 saved_uic_err = 0;
7306 unsigned long flags;
7307 int retries = MAX_HOST_RESET_RETRIES;
7309 spin_lock_irqsave(hba->host->host_lock, flags);
7312 * This is a fresh start, cache and clear saved error first,
7313 * in case new error generated during reset and restore.
7315 saved_err |= hba->saved_err;
7316 saved_uic_err |= hba->saved_uic_err;
7318 hba->saved_uic_err = 0;
7319 hba->force_reset = false;
7320 hba->ufshcd_state = UFSHCD_STATE_RESET;
7321 spin_unlock_irqrestore(hba->host->host_lock, flags);
7323 /* Reset the attached device */
7324 ufshcd_device_reset(hba);
7326 err = ufshcd_host_reset_and_restore(hba);
7328 spin_lock_irqsave(hba->host->host_lock, flags);
7331 /* Do not exit unless operational or dead */
7332 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL &&
7333 hba->ufshcd_state != UFSHCD_STATE_ERROR &&
7334 hba->ufshcd_state != UFSHCD_STATE_EH_SCHEDULED_NON_FATAL)
7336 } while (err && --retries);
7339 * Inform scsi mid-layer that we did reset and allow to handle
7340 * Unit Attention properly.
7342 scsi_report_bus_reset(hba->host, 0);
7344 hba->ufshcd_state = UFSHCD_STATE_ERROR;
7345 hba->saved_err |= saved_err;
7346 hba->saved_uic_err |= saved_uic_err;
7348 spin_unlock_irqrestore(hba->host->host_lock, flags);
7354 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer
7355 * @cmd: SCSI command pointer
7357 * Returns SUCCESS/FAILED
7359 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd)
7362 unsigned long flags;
7363 struct ufs_hba *hba;
7365 hba = shost_priv(cmd->device->host);
7367 spin_lock_irqsave(hba->host->host_lock, flags);
7368 hba->force_reset = true;
7369 ufshcd_schedule_eh_work(hba);
7370 dev_err(hba->dev, "%s: reset in progress - 1\n", __func__);
7371 spin_unlock_irqrestore(hba->host->host_lock, flags);
7373 flush_work(&hba->eh_work);
7375 spin_lock_irqsave(hba->host->host_lock, flags);
7376 if (hba->ufshcd_state == UFSHCD_STATE_ERROR)
7378 spin_unlock_irqrestore(hba->host->host_lock, flags);
7384 * ufshcd_get_max_icc_level - calculate the ICC level
7385 * @sup_curr_uA: max. current supported by the regulator
7386 * @start_scan: row at the desc table to start scan from
7387 * @buff: power descriptor buffer
7389 * Returns calculated max ICC level for specific regulator
7391 static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, char *buff)
7398 for (i = start_scan; i >= 0; i--) {
7399 data = get_unaligned_be16(&buff[2 * i]);
7400 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >>
7401 ATTR_ICC_LVL_UNIT_OFFSET;
7402 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK;
7404 case UFSHCD_NANO_AMP:
7405 curr_uA = curr_uA / 1000;
7407 case UFSHCD_MILI_AMP:
7408 curr_uA = curr_uA * 1000;
7411 curr_uA = curr_uA * 1000 * 1000;
7413 case UFSHCD_MICRO_AMP:
7417 if (sup_curr_uA >= curr_uA)
7422 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i);
7429 * ufshcd_find_max_sup_active_icc_level - calculate the max ICC level
7430 * In case regulators are not initialized we'll return 0
7431 * @hba: per-adapter instance
7432 * @desc_buf: power descriptor buffer to extract ICC levels from.
7433 * @len: length of desc_buff
7435 * Returns calculated ICC level
7437 static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba,
7438 u8 *desc_buf, int len)
7442 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq ||
7443 !hba->vreg_info.vccq2) {
7445 * Using dev_dbg to avoid messages during runtime PM to avoid
7446 * never-ending cycles of messages written back to storage by
7447 * user space causing runtime resume, causing more messages and
7451 "%s: Regulator capability was not set, actvIccLevel=%d",
7452 __func__, icc_level);
7456 if (hba->vreg_info.vcc->max_uA)
7457 icc_level = ufshcd_get_max_icc_level(
7458 hba->vreg_info.vcc->max_uA,
7459 POWER_DESC_MAX_ACTV_ICC_LVLS - 1,
7460 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]);
7462 if (hba->vreg_info.vccq->max_uA)
7463 icc_level = ufshcd_get_max_icc_level(
7464 hba->vreg_info.vccq->max_uA,
7466 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]);
7468 if (hba->vreg_info.vccq2->max_uA)
7469 icc_level = ufshcd_get_max_icc_level(
7470 hba->vreg_info.vccq2->max_uA,
7472 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]);
7477 static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba)
7480 int buff_len = hba->desc_size[QUERY_DESC_IDN_POWER];
7484 desc_buf = kmalloc(buff_len, GFP_KERNEL);
7488 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0,
7489 desc_buf, buff_len);
7492 "%s: Failed reading power descriptor.len = %d ret = %d",
7493 __func__, buff_len, ret);
7497 icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf,
7499 dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level);
7501 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
7502 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level);
7506 "%s: Failed configuring bActiveICCLevel = %d ret = %d",
7507 __func__, icc_level, ret);
7513 static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev)
7515 scsi_autopm_get_device(sdev);
7516 blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev);
7517 if (sdev->rpm_autosuspend)
7518 pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev,
7519 RPM_AUTOSUSPEND_DELAY_MS);
7520 scsi_autopm_put_device(sdev);
7524 * ufshcd_scsi_add_wlus - Adds required W-LUs
7525 * @hba: per-adapter instance
7527 * UFS device specification requires the UFS devices to support 4 well known
7529 * "REPORT_LUNS" (address: 01h)
7530 * "UFS Device" (address: 50h)
7531 * "RPMB" (address: 44h)
7532 * "BOOT" (address: 30h)
7533 * UFS device's power management needs to be controlled by "POWER CONDITION"
7534 * field of SSU (START STOP UNIT) command. But this "power condition" field
7535 * will take effect only when its sent to "UFS device" well known logical unit
7536 * hence we require the scsi_device instance to represent this logical unit in
7537 * order for the UFS host driver to send the SSU command for power management.
7539 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory
7540 * Block) LU so user space process can control this LU. User space may also
7541 * want to have access to BOOT LU.
7543 * This function adds scsi device instances for each of all well known LUs
7544 * (except "REPORT LUNS" LU).
7546 * Returns zero on success (all required W-LUs are added successfully),
7547 * non-zero error value on failure (if failed to add any of the required W-LU).
7549 static int ufshcd_scsi_add_wlus(struct ufs_hba *hba)
7552 struct scsi_device *sdev_boot, *sdev_rpmb;
7554 hba->ufs_device_wlun = __scsi_add_device(hba->host, 0, 0,
7555 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL);
7556 if (IS_ERR(hba->ufs_device_wlun)) {
7557 ret = PTR_ERR(hba->ufs_device_wlun);
7558 hba->ufs_device_wlun = NULL;
7561 scsi_device_put(hba->ufs_device_wlun);
7563 sdev_rpmb = __scsi_add_device(hba->host, 0, 0,
7564 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL);
7565 if (IS_ERR(sdev_rpmb)) {
7566 ret = PTR_ERR(sdev_rpmb);
7567 goto remove_ufs_device_wlun;
7569 ufshcd_blk_pm_runtime_init(sdev_rpmb);
7570 scsi_device_put(sdev_rpmb);
7572 sdev_boot = __scsi_add_device(hba->host, 0, 0,
7573 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL);
7574 if (IS_ERR(sdev_boot)) {
7575 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__);
7577 ufshcd_blk_pm_runtime_init(sdev_boot);
7578 scsi_device_put(sdev_boot);
7582 remove_ufs_device_wlun:
7583 scsi_remove_device(hba->ufs_device_wlun);
7588 static void ufshcd_wb_probe(struct ufs_hba *hba, u8 *desc_buf)
7590 struct ufs_dev_info *dev_info = &hba->dev_info;
7592 u32 d_lu_wb_buf_alloc;
7593 u32 ext_ufs_feature;
7595 if (!ufshcd_is_wb_allowed(hba))
7599 * Probe WB only for UFS-2.2 and UFS-3.1 (and later) devices or
7600 * UFS devices with quirk UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES
7603 if (!(dev_info->wspecversion >= 0x310 ||
7604 dev_info->wspecversion == 0x220 ||
7605 (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES)))
7608 if (hba->desc_size[QUERY_DESC_IDN_DEVICE] <
7609 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP + 4)
7612 ext_ufs_feature = get_unaligned_be32(desc_buf +
7613 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
7615 if (!(ext_ufs_feature & UFS_DEV_WRITE_BOOSTER_SUP))
7619 * WB may be supported but not configured while provisioning. The spec
7620 * says, in dedicated wb buffer mode, a max of 1 lun would have wb
7621 * buffer configured.
7623 dev_info->wb_buffer_type = desc_buf[DEVICE_DESC_PARAM_WB_TYPE];
7625 dev_info->b_presrv_uspc_en =
7626 desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN];
7628 if (dev_info->wb_buffer_type == WB_BUF_MODE_SHARED) {
7629 if (!get_unaligned_be32(desc_buf +
7630 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS))
7633 for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) {
7634 d_lu_wb_buf_alloc = 0;
7635 ufshcd_read_unit_desc_param(hba,
7637 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS,
7638 (u8 *)&d_lu_wb_buf_alloc,
7639 sizeof(d_lu_wb_buf_alloc));
7640 if (d_lu_wb_buf_alloc) {
7641 dev_info->wb_dedicated_lu = lun;
7646 if (!d_lu_wb_buf_alloc)
7650 if (!ufshcd_is_wb_buf_lifetime_available(hba))
7656 hba->caps &= ~UFSHCD_CAP_WB_EN;
7659 static void ufshcd_temp_notif_probe(struct ufs_hba *hba, u8 *desc_buf)
7661 struct ufs_dev_info *dev_info = &hba->dev_info;
7662 u32 ext_ufs_feature;
7665 if (!(hba->caps & UFSHCD_CAP_TEMP_NOTIF) || dev_info->wspecversion < 0x300)
7668 ext_ufs_feature = get_unaligned_be32(desc_buf + DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP);
7670 if (ext_ufs_feature & UFS_DEV_LOW_TEMP_NOTIF)
7671 mask |= MASK_EE_TOO_LOW_TEMP;
7673 if (ext_ufs_feature & UFS_DEV_HIGH_TEMP_NOTIF)
7674 mask |= MASK_EE_TOO_HIGH_TEMP;
7677 ufshcd_enable_ee(hba, mask);
7678 ufs_hwmon_probe(hba, mask);
7682 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba,
7683 const struct ufs_dev_quirk *fixups)
7685 const struct ufs_dev_quirk *f;
7686 struct ufs_dev_info *dev_info = &hba->dev_info;
7691 for (f = fixups; f->quirk; f++) {
7692 if ((f->wmanufacturerid == dev_info->wmanufacturerid ||
7693 f->wmanufacturerid == UFS_ANY_VENDOR) &&
7694 ((dev_info->model &&
7695 STR_PRFX_EQUAL(f->model, dev_info->model)) ||
7696 !strcmp(f->model, UFS_ANY_MODEL)))
7697 hba->dev_quirks |= f->quirk;
7700 EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks);
7702 static void ufs_fixup_device_setup(struct ufs_hba *hba)
7704 /* fix by general quirk table */
7705 ufshcd_fixup_dev_quirks(hba, ufs_fixups);
7707 /* allow vendors to fix quirks */
7708 ufshcd_vops_fixup_dev_quirks(hba);
7711 static int ufs_get_device_desc(struct ufs_hba *hba)
7715 u8 b_ufs_feature_sup;
7717 struct ufs_dev_info *dev_info = &hba->dev_info;
7719 desc_buf = kmalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL);
7725 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf,
7726 hba->desc_size[QUERY_DESC_IDN_DEVICE]);
7728 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
7734 * getting vendor (manufacturerID) and Bank Index in big endian
7737 dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
7738 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
7740 /* getting Specification Version in big endian format */
7741 dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 |
7742 desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1];
7743 b_ufs_feature_sup = desc_buf[DEVICE_DESC_PARAM_UFS_FEAT];
7745 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
7747 if (dev_info->wspecversion >= UFS_DEV_HPB_SUPPORT_VERSION &&
7748 (b_ufs_feature_sup & UFS_DEV_HPB_SUPPORT)) {
7749 bool hpb_en = false;
7751 ufshpb_get_dev_info(hba, desc_buf);
7753 if (!ufshpb_is_legacy(hba))
7754 err = ufshcd_query_flag_retry(hba,
7755 UPIU_QUERY_OPCODE_READ_FLAG,
7756 QUERY_FLAG_IDN_HPB_EN, 0,
7759 if (ufshpb_is_legacy(hba) || (!err && hpb_en))
7760 dev_info->hpb_enabled = true;
7763 err = ufshcd_read_string_desc(hba, model_index,
7764 &dev_info->model, SD_ASCII_STD);
7766 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
7771 hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] +
7772 desc_buf[DEVICE_DESC_PARAM_NUM_WLU];
7774 ufs_fixup_device_setup(hba);
7776 ufshcd_wb_probe(hba, desc_buf);
7778 ufshcd_temp_notif_probe(hba, desc_buf);
7781 * ufshcd_read_string_desc returns size of the string
7782 * reset the error value
7791 static void ufs_put_device_desc(struct ufs_hba *hba)
7793 struct ufs_dev_info *dev_info = &hba->dev_info;
7795 kfree(dev_info->model);
7796 dev_info->model = NULL;
7800 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro
7801 * @hba: per-adapter instance
7803 * PA_TActivate parameter can be tuned manually if UniPro version is less than
7804 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's
7805 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce
7806 * the hibern8 exit latency.
7808 * Returns zero on success, non-zero error value on failure.
7810 static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba)
7813 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate;
7815 ret = ufshcd_dme_peer_get(hba,
7817 RX_MIN_ACTIVATETIME_CAPABILITY,
7818 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
7819 &peer_rx_min_activatetime);
7823 /* make sure proper unit conversion is applied */
7824 tuned_pa_tactivate =
7825 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US)
7826 / PA_TACTIVATE_TIME_UNIT_US);
7827 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
7828 tuned_pa_tactivate);
7835 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro
7836 * @hba: per-adapter instance
7838 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than
7839 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's
7840 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY.
7841 * This optimal value can help reduce the hibern8 exit latency.
7843 * Returns zero on success, non-zero error value on failure.
7845 static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba)
7848 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0;
7849 u32 max_hibern8_time, tuned_pa_hibern8time;
7851 ret = ufshcd_dme_get(hba,
7852 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY,
7853 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)),
7854 &local_tx_hibern8_time_cap);
7858 ret = ufshcd_dme_peer_get(hba,
7859 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY,
7860 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)),
7861 &peer_rx_hibern8_time_cap);
7865 max_hibern8_time = max(local_tx_hibern8_time_cap,
7866 peer_rx_hibern8_time_cap);
7867 /* make sure proper unit conversion is applied */
7868 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US)
7869 / PA_HIBERN8_TIME_UNIT_US);
7870 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
7871 tuned_pa_hibern8time);
7877 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is
7878 * less than device PA_TACTIVATE time.
7879 * @hba: per-adapter instance
7881 * Some UFS devices require host PA_TACTIVATE to be lower than device
7882 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk
7885 * Returns zero on success, non-zero error value on failure.
7887 static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba)
7890 u32 granularity, peer_granularity;
7891 u32 pa_tactivate, peer_pa_tactivate;
7892 u32 pa_tactivate_us, peer_pa_tactivate_us;
7893 u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100};
7895 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
7900 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
7905 if ((granularity < PA_GRANULARITY_MIN_VAL) ||
7906 (granularity > PA_GRANULARITY_MAX_VAL)) {
7907 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d",
7908 __func__, granularity);
7912 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) ||
7913 (peer_granularity > PA_GRANULARITY_MAX_VAL)) {
7914 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d",
7915 __func__, peer_granularity);
7919 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate);
7923 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE),
7924 &peer_pa_tactivate);
7928 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1];
7929 peer_pa_tactivate_us = peer_pa_tactivate *
7930 gran_to_us_table[peer_granularity - 1];
7932 if (pa_tactivate_us >= peer_pa_tactivate_us) {
7933 u32 new_peer_pa_tactivate;
7935 new_peer_pa_tactivate = pa_tactivate_us /
7936 gran_to_us_table[peer_granularity - 1];
7937 new_peer_pa_tactivate++;
7938 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
7939 new_peer_pa_tactivate);
7946 static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
7948 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) {
7949 ufshcd_tune_pa_tactivate(hba);
7950 ufshcd_tune_pa_hibern8time(hba);
7953 ufshcd_vops_apply_dev_quirks(hba);
7955 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE)
7956 /* set 1ms timeout for PA_TACTIVATE */
7957 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10);
7959 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE)
7960 ufshcd_quirk_tune_host_pa_tactivate(hba);
7963 static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
7965 hba->ufs_stats.hibern8_exit_cnt = 0;
7966 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0);
7967 hba->req_abort_count = 0;
7970 static int ufshcd_device_geo_params_init(struct ufs_hba *hba)
7976 buff_len = hba->desc_size[QUERY_DESC_IDN_GEOMETRY];
7977 desc_buf = kmalloc(buff_len, GFP_KERNEL);
7983 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0,
7984 desc_buf, buff_len);
7986 dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n",
7991 if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1)
7992 hba->dev_info.max_lu_supported = 32;
7993 else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0)
7994 hba->dev_info.max_lu_supported = 8;
7996 if (hba->desc_size[QUERY_DESC_IDN_GEOMETRY] >=
7997 GEOMETRY_DESC_PARAM_HPB_MAX_ACTIVE_REGS)
7998 ufshpb_get_geo_info(hba, desc_buf);
8005 struct ufs_ref_clk {
8006 unsigned long freq_hz;
8007 enum ufs_ref_clk_freq val;
8010 static struct ufs_ref_clk ufs_ref_clk_freqs[] = {
8011 {19200000, REF_CLK_FREQ_19_2_MHZ},
8012 {26000000, REF_CLK_FREQ_26_MHZ},
8013 {38400000, REF_CLK_FREQ_38_4_MHZ},
8014 {52000000, REF_CLK_FREQ_52_MHZ},
8015 {0, REF_CLK_FREQ_INVAL},
8018 static enum ufs_ref_clk_freq
8019 ufs_get_bref_clk_from_hz(unsigned long freq)
8023 for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++)
8024 if (ufs_ref_clk_freqs[i].freq_hz == freq)
8025 return ufs_ref_clk_freqs[i].val;
8027 return REF_CLK_FREQ_INVAL;
8030 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk)
8034 freq = clk_get_rate(refclk);
8036 hba->dev_ref_clk_freq =
8037 ufs_get_bref_clk_from_hz(freq);
8039 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL)
8041 "invalid ref_clk setting = %ld\n", freq);
8044 static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba)
8048 u32 freq = hba->dev_ref_clk_freq;
8050 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR,
8051 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk);
8054 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n",
8059 if (ref_clk == freq)
8060 goto out; /* nothing to update */
8062 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR,
8063 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq);
8066 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n",
8067 ufs_ref_clk_freqs[freq].freq_hz);
8071 dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n",
8072 ufs_ref_clk_freqs[freq].freq_hz);
8078 static int ufshcd_device_params_init(struct ufs_hba *hba)
8083 /* Init device descriptor sizes */
8084 for (i = 0; i < QUERY_DESC_IDN_MAX; i++)
8085 hba->desc_size[i] = QUERY_DESC_MAX_SIZE;
8087 /* Init UFS geometry descriptor related parameters */
8088 ret = ufshcd_device_geo_params_init(hba);
8092 /* Check and apply UFS device quirks */
8093 ret = ufs_get_device_desc(hba);
8095 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
8100 ufshcd_get_ref_clk_gating_wait(hba);
8102 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
8103 QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag))
8104 hba->dev_info.f_power_on_wp_en = flag;
8106 /* Probe maximum power mode co-supported by both UFS host and device */
8107 if (ufshcd_get_max_pwr_mode(hba))
8109 "%s: Failed getting max supported power mode\n",
8116 * ufshcd_add_lus - probe and add UFS logical units
8117 * @hba: per-adapter instance
8119 static int ufshcd_add_lus(struct ufs_hba *hba)
8123 /* Add required well known logical units to scsi mid layer */
8124 ret = ufshcd_scsi_add_wlus(hba);
8128 /* Initialize devfreq after UFS device is detected */
8129 if (ufshcd_is_clkscaling_supported(hba)) {
8130 memcpy(&hba->clk_scaling.saved_pwr_info.info,
8132 sizeof(struct ufs_pa_layer_attr));
8133 hba->clk_scaling.saved_pwr_info.is_valid = true;
8134 hba->clk_scaling.is_allowed = true;
8136 ret = ufshcd_devfreq_init(hba);
8140 hba->clk_scaling.is_enabled = true;
8141 ufshcd_init_clk_scaling_sysfs(hba);
8146 scsi_scan_host(hba->host);
8147 pm_runtime_put_sync(hba->dev);
8154 * ufshcd_probe_hba - probe hba to detect device and initialize it
8155 * @hba: per-adapter instance
8156 * @init_dev_params: whether or not to call ufshcd_device_params_init().
8158 * Execute link-startup and verify device initialization
8160 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params)
8163 unsigned long flags;
8164 ktime_t start = ktime_get();
8166 hba->ufshcd_state = UFSHCD_STATE_RESET;
8168 ret = ufshcd_link_startup(hba);
8172 if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION)
8175 /* Debug counters initialization */
8176 ufshcd_clear_dbg_ufs_stats(hba);
8178 /* UniPro link is active now */
8179 ufshcd_set_link_active(hba);
8181 /* Verify device initialization by sending NOP OUT UPIU */
8182 ret = ufshcd_verify_dev_init(hba);
8186 /* Initiate UFS initialization, and waiting until completion */
8187 ret = ufshcd_complete_dev_init(hba);
8192 * Initialize UFS device parameters used by driver, these
8193 * parameters are associated with UFS descriptors.
8195 if (init_dev_params) {
8196 ret = ufshcd_device_params_init(hba);
8201 ufshcd_tune_unipro_params(hba);
8203 /* UFS device is also active now */
8204 ufshcd_set_ufs_dev_active(hba);
8205 ufshcd_force_reset_auto_bkops(hba);
8207 /* Gear up to HS gear if supported */
8208 if (hba->max_pwr_info.is_valid) {
8210 * Set the right value to bRefClkFreq before attempting to
8211 * switch to HS gears.
8213 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL)
8214 ufshcd_set_dev_ref_clk(hba);
8215 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
8217 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
8221 ufshcd_print_pwr_info(hba);
8225 * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec)
8226 * and for removable UFS card as well, hence always set the parameter.
8227 * Note: Error handler may issue the device reset hence resetting
8228 * bActiveICCLevel as well so it is always safe to set this here.
8230 ufshcd_set_active_icc_lvl(hba);
8232 ufshcd_wb_config(hba);
8233 if (hba->ee_usr_mask)
8234 ufshcd_write_ee_control(hba);
8235 /* Enable Auto-Hibernate if configured */
8236 ufshcd_auto_hibern8_enable(hba);
8238 ufshpb_toggle_state(hba, HPB_RESET, HPB_PRESENT);
8240 spin_lock_irqsave(hba->host->host_lock, flags);
8242 hba->ufshcd_state = UFSHCD_STATE_ERROR;
8243 else if (hba->ufshcd_state == UFSHCD_STATE_RESET)
8244 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
8245 spin_unlock_irqrestore(hba->host->host_lock, flags);
8247 trace_ufshcd_init(dev_name(hba->dev), ret,
8248 ktime_to_us(ktime_sub(ktime_get(), start)),
8249 hba->curr_dev_pwr_mode, hba->uic_link_state);
8254 * ufshcd_async_scan - asynchronous execution for probing hba
8255 * @data: data pointer to pass to this function
8256 * @cookie: cookie data
8258 static void ufshcd_async_scan(void *data, async_cookie_t cookie)
8260 struct ufs_hba *hba = (struct ufs_hba *)data;
8263 down(&hba->host_sem);
8264 /* Initialize hba, detect and initialize UFS device */
8265 ret = ufshcd_probe_hba(hba, true);
8270 /* Probe and add UFS logical units */
8271 ret = ufshcd_add_lus(hba);
8274 * If we failed to initialize the device or the device is not
8275 * present, turn off the power/clocks etc.
8278 pm_runtime_put_sync(hba->dev);
8279 ufshcd_hba_exit(hba);
8283 static const struct attribute_group *ufshcd_driver_groups[] = {
8284 &ufs_sysfs_unit_descriptor_group,
8285 &ufs_sysfs_lun_attributes_group,
8286 #ifdef CONFIG_SCSI_UFS_HPB
8287 &ufs_sysfs_hpb_stat_group,
8288 &ufs_sysfs_hpb_param_group,
8293 static struct ufs_hba_variant_params ufs_hba_vps = {
8294 .hba_enable_delay_us = 1000,
8295 .wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(40),
8296 .devfreq_profile.polling_ms = 100,
8297 .devfreq_profile.target = ufshcd_devfreq_target,
8298 .devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status,
8299 .ondemand_data.upthreshold = 70,
8300 .ondemand_data.downdifferential = 5,
8303 static struct scsi_host_template ufshcd_driver_template = {
8304 .module = THIS_MODULE,
8306 .proc_name = UFSHCD,
8307 .map_queues = ufshcd_map_queues,
8308 .queuecommand = ufshcd_queuecommand,
8309 .mq_poll = ufshcd_poll,
8310 .slave_alloc = ufshcd_slave_alloc,
8311 .slave_configure = ufshcd_slave_configure,
8312 .slave_destroy = ufshcd_slave_destroy,
8313 .change_queue_depth = ufshcd_change_queue_depth,
8314 .eh_abort_handler = ufshcd_abort,
8315 .eh_device_reset_handler = ufshcd_eh_device_reset_handler,
8316 .eh_host_reset_handler = ufshcd_eh_host_reset_handler,
8318 .sg_tablesize = SG_ALL,
8319 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
8320 .can_queue = UFSHCD_CAN_QUEUE,
8321 .max_segment_size = PRDT_DATA_BYTE_COUNT_MAX,
8322 .max_host_blocked = 1,
8323 .track_queue_depth = 1,
8324 .sdev_groups = ufshcd_driver_groups,
8325 .dma_boundary = PAGE_SIZE - 1,
8326 .rpm_autosuspend_delay = RPM_AUTOSUSPEND_DELAY_MS,
8329 static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg,
8338 * "set_load" operation shall be required on those regulators
8339 * which specifically configured current limitation. Otherwise
8340 * zero max_uA may cause unexpected behavior when regulator is
8341 * enabled or set as high power mode.
8346 ret = regulator_set_load(vreg->reg, ua);
8348 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n",
8349 __func__, vreg->name, ua, ret);
8355 static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba,
8356 struct ufs_vreg *vreg)
8358 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA);
8361 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba,
8362 struct ufs_vreg *vreg)
8367 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA);
8370 static int ufshcd_config_vreg(struct device *dev,
8371 struct ufs_vreg *vreg, bool on)
8373 if (regulator_count_voltages(vreg->reg) <= 0)
8376 return ufshcd_config_vreg_load(dev, vreg, on ? vreg->max_uA : 0);
8379 static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg)
8383 if (!vreg || vreg->enabled)
8386 ret = ufshcd_config_vreg(dev, vreg, true);
8388 ret = regulator_enable(vreg->reg);
8391 vreg->enabled = true;
8393 dev_err(dev, "%s: %s enable failed, err=%d\n",
8394 __func__, vreg->name, ret);
8399 static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg)
8403 if (!vreg || !vreg->enabled || vreg->always_on)
8406 ret = regulator_disable(vreg->reg);
8409 /* ignore errors on applying disable config */
8410 ufshcd_config_vreg(dev, vreg, false);
8411 vreg->enabled = false;
8413 dev_err(dev, "%s: %s disable failed, err=%d\n",
8414 __func__, vreg->name, ret);
8420 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on)
8423 struct device *dev = hba->dev;
8424 struct ufs_vreg_info *info = &hba->vreg_info;
8426 ret = ufshcd_toggle_vreg(dev, info->vcc, on);
8430 ret = ufshcd_toggle_vreg(dev, info->vccq, on);
8434 ret = ufshcd_toggle_vreg(dev, info->vccq2, on);
8438 ufshcd_toggle_vreg(dev, info->vccq2, false);
8439 ufshcd_toggle_vreg(dev, info->vccq, false);
8440 ufshcd_toggle_vreg(dev, info->vcc, false);
8445 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on)
8447 struct ufs_vreg_info *info = &hba->vreg_info;
8449 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on);
8452 static int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg)
8459 vreg->reg = devm_regulator_get(dev, vreg->name);
8460 if (IS_ERR(vreg->reg)) {
8461 ret = PTR_ERR(vreg->reg);
8462 dev_err(dev, "%s: %s get failed, err=%d\n",
8463 __func__, vreg->name, ret);
8469 static int ufshcd_init_vreg(struct ufs_hba *hba)
8472 struct device *dev = hba->dev;
8473 struct ufs_vreg_info *info = &hba->vreg_info;
8475 ret = ufshcd_get_vreg(dev, info->vcc);
8479 ret = ufshcd_get_vreg(dev, info->vccq);
8481 ret = ufshcd_get_vreg(dev, info->vccq2);
8486 static int ufshcd_init_hba_vreg(struct ufs_hba *hba)
8488 struct ufs_vreg_info *info = &hba->vreg_info;
8490 return ufshcd_get_vreg(hba->dev, info->vdd_hba);
8493 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on)
8496 struct ufs_clk_info *clki;
8497 struct list_head *head = &hba->clk_list_head;
8498 unsigned long flags;
8499 ktime_t start = ktime_get();
8500 bool clk_state_changed = false;
8502 if (list_empty(head))
8505 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE);
8509 list_for_each_entry(clki, head, list) {
8510 if (!IS_ERR_OR_NULL(clki->clk)) {
8512 * Don't disable clocks which are needed
8513 * to keep the link active.
8515 if (ufshcd_is_link_active(hba) &&
8516 clki->keep_link_active)
8519 clk_state_changed = on ^ clki->enabled;
8520 if (on && !clki->enabled) {
8521 ret = clk_prepare_enable(clki->clk);
8523 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n",
8524 __func__, clki->name, ret);
8527 } else if (!on && clki->enabled) {
8528 clk_disable_unprepare(clki->clk);
8531 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__,
8532 clki->name, on ? "en" : "dis");
8536 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE);
8542 list_for_each_entry(clki, head, list) {
8543 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled)
8544 clk_disable_unprepare(clki->clk);
8546 } else if (!ret && on) {
8547 spin_lock_irqsave(hba->host->host_lock, flags);
8548 hba->clk_gating.state = CLKS_ON;
8549 trace_ufshcd_clk_gating(dev_name(hba->dev),
8550 hba->clk_gating.state);
8551 spin_unlock_irqrestore(hba->host->host_lock, flags);
8554 if (clk_state_changed)
8555 trace_ufshcd_profile_clk_gating(dev_name(hba->dev),
8556 (on ? "on" : "off"),
8557 ktime_to_us(ktime_sub(ktime_get(), start)), ret);
8561 static int ufshcd_init_clocks(struct ufs_hba *hba)
8564 struct ufs_clk_info *clki;
8565 struct device *dev = hba->dev;
8566 struct list_head *head = &hba->clk_list_head;
8568 if (list_empty(head))
8571 list_for_each_entry(clki, head, list) {
8575 clki->clk = devm_clk_get(dev, clki->name);
8576 if (IS_ERR(clki->clk)) {
8577 ret = PTR_ERR(clki->clk);
8578 dev_err(dev, "%s: %s clk get failed, %d\n",
8579 __func__, clki->name, ret);
8584 * Parse device ref clk freq as per device tree "ref_clk".
8585 * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL
8586 * in ufshcd_alloc_host().
8588 if (!strcmp(clki->name, "ref_clk"))
8589 ufshcd_parse_dev_ref_clk_freq(hba, clki->clk);
8591 if (clki->max_freq) {
8592 ret = clk_set_rate(clki->clk, clki->max_freq);
8594 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n",
8595 __func__, clki->name,
8596 clki->max_freq, ret);
8599 clki->curr_freq = clki->max_freq;
8601 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__,
8602 clki->name, clk_get_rate(clki->clk));
8608 static int ufshcd_variant_hba_init(struct ufs_hba *hba)
8615 err = ufshcd_vops_init(hba);
8617 dev_err(hba->dev, "%s: variant %s init failed err %d\n",
8618 __func__, ufshcd_get_var_name(hba), err);
8623 static void ufshcd_variant_hba_exit(struct ufs_hba *hba)
8628 ufshcd_vops_exit(hba);
8631 static int ufshcd_hba_init(struct ufs_hba *hba)
8636 * Handle host controller power separately from the UFS device power
8637 * rails as it will help controlling the UFS host controller power
8638 * collapse easily which is different than UFS device power collapse.
8639 * Also, enable the host controller power before we go ahead with rest
8640 * of the initialization here.
8642 err = ufshcd_init_hba_vreg(hba);
8646 err = ufshcd_setup_hba_vreg(hba, true);
8650 err = ufshcd_init_clocks(hba);
8652 goto out_disable_hba_vreg;
8654 err = ufshcd_setup_clocks(hba, true);
8656 goto out_disable_hba_vreg;
8658 err = ufshcd_init_vreg(hba);
8660 goto out_disable_clks;
8662 err = ufshcd_setup_vreg(hba, true);
8664 goto out_disable_clks;
8666 err = ufshcd_variant_hba_init(hba);
8668 goto out_disable_vreg;
8670 ufs_debugfs_hba_init(hba);
8672 hba->is_powered = true;
8676 ufshcd_setup_vreg(hba, false);
8678 ufshcd_setup_clocks(hba, false);
8679 out_disable_hba_vreg:
8680 ufshcd_setup_hba_vreg(hba, false);
8685 static void ufshcd_hba_exit(struct ufs_hba *hba)
8687 if (hba->is_powered) {
8688 ufshcd_exit_clk_scaling(hba);
8689 ufshcd_exit_clk_gating(hba);
8691 destroy_workqueue(hba->eh_wq);
8692 ufs_debugfs_hba_exit(hba);
8693 ufshcd_variant_hba_exit(hba);
8694 ufshcd_setup_vreg(hba, false);
8695 ufshcd_setup_clocks(hba, false);
8696 ufshcd_setup_hba_vreg(hba, false);
8697 hba->is_powered = false;
8698 ufs_put_device_desc(hba);
8703 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device
8705 * @hba: per adapter instance
8706 * @pwr_mode: device power mode to set
8708 * Returns 0 if requested power mode is set successfully
8709 * Returns < 0 if failed to set the requested power mode
8711 static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba,
8712 enum ufs_dev_pwr_mode pwr_mode)
8714 unsigned char cmd[6] = { START_STOP };
8715 struct scsi_sense_hdr sshdr;
8716 struct scsi_device *sdp;
8717 unsigned long flags;
8720 spin_lock_irqsave(hba->host->host_lock, flags);
8721 sdp = hba->ufs_device_wlun;
8723 ret = scsi_device_get(sdp);
8724 if (!ret && !scsi_device_online(sdp)) {
8726 scsi_device_put(sdp);
8731 spin_unlock_irqrestore(hba->host->host_lock, flags);
8737 * If scsi commands fail, the scsi mid-layer schedules scsi error-
8738 * handling, which would wait for host to be resumed. Since we know
8739 * we are functional while we are here, skip host resume in error
8742 hba->host->eh_noresume = 1;
8744 cmd[4] = pwr_mode << 4;
8747 * Current function would be generally called from the power management
8748 * callbacks hence set the RQF_PM flag so that it doesn't resume the
8749 * already suspended childs.
8751 for (retries = 3; retries > 0; --retries) {
8752 ret = scsi_execute(sdp, cmd, DMA_NONE, NULL, 0, NULL, &sshdr,
8753 START_STOP_TIMEOUT, 0, 0, RQF_PM, NULL);
8754 if (!scsi_status_is_check_condition(ret) ||
8755 !scsi_sense_valid(&sshdr) ||
8756 sshdr.sense_key != UNIT_ATTENTION)
8760 sdev_printk(KERN_WARNING, sdp,
8761 "START_STOP failed for power mode: %d, result %x\n",
8764 if (scsi_sense_valid(&sshdr))
8765 scsi_print_sense_hdr(sdp, NULL, &sshdr);
8771 hba->curr_dev_pwr_mode = pwr_mode;
8773 scsi_device_put(sdp);
8774 hba->host->eh_noresume = 0;
8778 static int ufshcd_link_state_transition(struct ufs_hba *hba,
8779 enum uic_link_state req_link_state,
8780 int check_for_bkops)
8784 if (req_link_state == hba->uic_link_state)
8787 if (req_link_state == UIC_LINK_HIBERN8_STATE) {
8788 ret = ufshcd_uic_hibern8_enter(hba);
8790 ufshcd_set_link_hibern8(hba);
8792 dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
8798 * If autobkops is enabled, link can't be turned off because
8799 * turning off the link would also turn off the device, except in the
8800 * case of DeepSleep where the device is expected to remain powered.
8802 else if ((req_link_state == UIC_LINK_OFF_STATE) &&
8803 (!check_for_bkops || !hba->auto_bkops_enabled)) {
8805 * Let's make sure that link is in low power mode, we are doing
8806 * this currently by putting the link in Hibern8. Otherway to
8807 * put the link in low power mode is to send the DME end point
8808 * to device and then send the DME reset command to local
8809 * unipro. But putting the link in hibern8 is much faster.
8811 * Note also that putting the link in Hibern8 is a requirement
8812 * for entering DeepSleep.
8814 ret = ufshcd_uic_hibern8_enter(hba);
8816 dev_err(hba->dev, "%s: hibern8 enter failed %d\n",
8821 * Change controller state to "reset state" which
8822 * should also put the link in off/reset state
8824 ufshcd_hba_stop(hba);
8826 * TODO: Check if we need any delay to make sure that
8827 * controller is reset
8829 ufshcd_set_link_off(hba);
8836 static void ufshcd_vreg_set_lpm(struct ufs_hba *hba)
8838 bool vcc_off = false;
8841 * It seems some UFS devices may keep drawing more than sleep current
8842 * (atleast for 500us) from UFS rails (especially from VCCQ rail).
8843 * To avoid this situation, add 2ms delay before putting these UFS
8844 * rails in LPM mode.
8846 if (!ufshcd_is_link_active(hba) &&
8847 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM)
8848 usleep_range(2000, 2100);
8851 * If UFS device is either in UFS_Sleep turn off VCC rail to save some
8854 * If UFS device and link is in OFF state, all power supplies (VCC,
8855 * VCCQ, VCCQ2) can be turned off if power on write protect is not
8856 * required. If UFS link is inactive (Hibern8 or OFF state) and device
8857 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode.
8859 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway
8860 * in low power state which would save some power.
8862 * If Write Booster is enabled and the device needs to flush the WB
8863 * buffer OR if bkops status is urgent for WB, keep Vcc on.
8865 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
8866 !hba->dev_info.is_lu_power_on_wp) {
8867 ufshcd_setup_vreg(hba, false);
8869 } else if (!ufshcd_is_ufs_dev_active(hba)) {
8870 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
8872 if (ufshcd_is_link_hibern8(hba) || ufshcd_is_link_off(hba)) {
8873 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
8874 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2);
8879 * Some UFS devices require delay after VCC power rail is turned-off.
8881 if (vcc_off && hba->vreg_info.vcc &&
8882 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM)
8883 usleep_range(5000, 5100);
8887 static int ufshcd_vreg_set_hpm(struct ufs_hba *hba)
8891 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) &&
8892 !hba->dev_info.is_lu_power_on_wp) {
8893 ret = ufshcd_setup_vreg(hba, true);
8894 } else if (!ufshcd_is_ufs_dev_active(hba)) {
8895 if (!ufshcd_is_link_active(hba)) {
8896 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq);
8899 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2);
8903 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true);
8908 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq);
8910 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false);
8914 #endif /* CONFIG_PM */
8916 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba)
8918 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
8919 ufshcd_setup_hba_vreg(hba, false);
8922 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba)
8924 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba))
8925 ufshcd_setup_hba_vreg(hba, true);
8928 static int __ufshcd_wl_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
8931 int check_for_bkops;
8932 enum ufs_pm_level pm_lvl;
8933 enum ufs_dev_pwr_mode req_dev_pwr_mode;
8934 enum uic_link_state req_link_state;
8936 hba->pm_op_in_progress = true;
8937 if (pm_op != UFS_SHUTDOWN_PM) {
8938 pm_lvl = pm_op == UFS_RUNTIME_PM ?
8939 hba->rpm_lvl : hba->spm_lvl;
8940 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl);
8941 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl);
8943 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE;
8944 req_link_state = UIC_LINK_OFF_STATE;
8947 ufshpb_suspend(hba);
8950 * If we can't transition into any of the low power modes
8951 * just gate the clocks.
8953 ufshcd_hold(hba, false);
8954 hba->clk_gating.is_suspended = true;
8956 if (ufshcd_is_clkscaling_supported(hba))
8957 ufshcd_clk_scaling_suspend(hba, true);
8959 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE &&
8960 req_link_state == UIC_LINK_ACTIVE_STATE) {
8964 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) &&
8965 (req_link_state == hba->uic_link_state))
8966 goto enable_scaling;
8968 /* UFS device & link must be active before we enter in this function */
8969 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) {
8971 goto enable_scaling;
8974 if (pm_op == UFS_RUNTIME_PM) {
8975 if (ufshcd_can_autobkops_during_suspend(hba)) {
8977 * The device is idle with no requests in the queue,
8978 * allow background operations if bkops status shows
8979 * that performance might be impacted.
8981 ret = ufshcd_urgent_bkops(hba);
8983 goto enable_scaling;
8985 /* make sure that auto bkops is disabled */
8986 ufshcd_disable_auto_bkops(hba);
8989 * If device needs to do BKOP or WB buffer flush during
8990 * Hibern8, keep device power mode as "active power mode"
8993 hba->dev_info.b_rpm_dev_flush_capable =
8994 hba->auto_bkops_enabled ||
8995 (((req_link_state == UIC_LINK_HIBERN8_STATE) ||
8996 ((req_link_state == UIC_LINK_ACTIVE_STATE) &&
8997 ufshcd_is_auto_hibern8_enabled(hba))) &&
8998 ufshcd_wb_need_flush(hba));
9001 flush_work(&hba->eeh_work);
9003 ret = ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE);
9005 goto enable_scaling;
9007 if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) {
9008 if (pm_op != UFS_RUNTIME_PM)
9009 /* ensure that bkops is disabled */
9010 ufshcd_disable_auto_bkops(hba);
9012 if (!hba->dev_info.b_rpm_dev_flush_capable) {
9013 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode);
9015 goto enable_scaling;
9020 * In the case of DeepSleep, the device is expected to remain powered
9021 * with the link off, so do not check for bkops.
9023 check_for_bkops = !ufshcd_is_ufs_dev_deepsleep(hba);
9024 ret = ufshcd_link_state_transition(hba, req_link_state, check_for_bkops);
9026 goto set_dev_active;
9030 * Call vendor specific suspend callback. As these callbacks may access
9031 * vendor specific host controller register space call them before the
9032 * host clocks are ON.
9034 ret = ufshcd_vops_suspend(hba, pm_op, POST_CHANGE);
9036 goto set_link_active;
9041 * Device hardware reset is required to exit DeepSleep. Also, for
9042 * DeepSleep, the link is off so host reset and restore will be done
9045 if (ufshcd_is_ufs_dev_deepsleep(hba)) {
9046 ufshcd_device_reset(hba);
9047 WARN_ON(!ufshcd_is_link_off(hba));
9049 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba))
9050 ufshcd_set_link_active(hba);
9051 else if (ufshcd_is_link_off(hba))
9052 ufshcd_host_reset_and_restore(hba);
9054 /* Can also get here needing to exit DeepSleep */
9055 if (ufshcd_is_ufs_dev_deepsleep(hba)) {
9056 ufshcd_device_reset(hba);
9057 ufshcd_host_reset_and_restore(hba);
9059 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE))
9060 ufshcd_disable_auto_bkops(hba);
9062 if (ufshcd_is_clkscaling_supported(hba))
9063 ufshcd_clk_scaling_suspend(hba, false);
9065 hba->dev_info.b_rpm_dev_flush_capable = false;
9067 if (hba->dev_info.b_rpm_dev_flush_capable) {
9068 schedule_delayed_work(&hba->rpm_dev_flush_recheck_work,
9069 msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS));
9073 ufshcd_update_evt_hist(hba, UFS_EVT_WL_SUSP_ERR, (u32)ret);
9074 hba->clk_gating.is_suspended = false;
9075 ufshcd_release(hba);
9078 hba->pm_op_in_progress = false;
9083 static int __ufshcd_wl_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
9086 enum uic_link_state old_link_state = hba->uic_link_state;
9088 hba->pm_op_in_progress = true;
9091 * Call vendor specific resume callback. As these callbacks may access
9092 * vendor specific host controller register space call them when the
9093 * host clocks are ON.
9095 ret = ufshcd_vops_resume(hba, pm_op);
9099 /* For DeepSleep, the only supported option is to have the link off */
9100 WARN_ON(ufshcd_is_ufs_dev_deepsleep(hba) && !ufshcd_is_link_off(hba));
9102 if (ufshcd_is_link_hibern8(hba)) {
9103 ret = ufshcd_uic_hibern8_exit(hba);
9105 ufshcd_set_link_active(hba);
9107 dev_err(hba->dev, "%s: hibern8 exit failed %d\n",
9109 goto vendor_suspend;
9111 } else if (ufshcd_is_link_off(hba)) {
9113 * A full initialization of the host and the device is
9114 * required since the link was put to off during suspend.
9115 * Note, in the case of DeepSleep, the device will exit
9116 * DeepSleep due to device reset.
9118 ret = ufshcd_reset_and_restore(hba);
9120 * ufshcd_reset_and_restore() should have already
9121 * set the link state as active
9123 if (ret || !ufshcd_is_link_active(hba))
9124 goto vendor_suspend;
9127 if (!ufshcd_is_ufs_dev_active(hba)) {
9128 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE);
9130 goto set_old_link_state;
9133 if (ufshcd_keep_autobkops_enabled_except_suspend(hba))
9134 ufshcd_enable_auto_bkops(hba);
9137 * If BKOPs operations are urgently needed at this moment then
9138 * keep auto-bkops enabled or else disable it.
9140 ufshcd_urgent_bkops(hba);
9142 if (hba->ee_usr_mask)
9143 ufshcd_write_ee_control(hba);
9145 if (ufshcd_is_clkscaling_supported(hba))
9146 ufshcd_clk_scaling_suspend(hba, false);
9148 if (hba->dev_info.b_rpm_dev_flush_capable) {
9149 hba->dev_info.b_rpm_dev_flush_capable = false;
9150 cancel_delayed_work(&hba->rpm_dev_flush_recheck_work);
9153 /* Enable Auto-Hibernate if configured */
9154 ufshcd_auto_hibern8_enable(hba);
9160 ufshcd_link_state_transition(hba, old_link_state, 0);
9162 ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE);
9163 ufshcd_vops_suspend(hba, pm_op, POST_CHANGE);
9166 ufshcd_update_evt_hist(hba, UFS_EVT_WL_RES_ERR, (u32)ret);
9167 hba->clk_gating.is_suspended = false;
9168 ufshcd_release(hba);
9169 hba->pm_op_in_progress = false;
9173 static int ufshcd_wl_runtime_suspend(struct device *dev)
9175 struct scsi_device *sdev = to_scsi_device(dev);
9176 struct ufs_hba *hba;
9178 ktime_t start = ktime_get();
9180 hba = shost_priv(sdev->host);
9182 ret = __ufshcd_wl_suspend(hba, UFS_RUNTIME_PM);
9184 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9186 trace_ufshcd_wl_runtime_suspend(dev_name(dev), ret,
9187 ktime_to_us(ktime_sub(ktime_get(), start)),
9188 hba->curr_dev_pwr_mode, hba->uic_link_state);
9193 static int ufshcd_wl_runtime_resume(struct device *dev)
9195 struct scsi_device *sdev = to_scsi_device(dev);
9196 struct ufs_hba *hba;
9198 ktime_t start = ktime_get();
9200 hba = shost_priv(sdev->host);
9202 ret = __ufshcd_wl_resume(hba, UFS_RUNTIME_PM);
9204 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9206 trace_ufshcd_wl_runtime_resume(dev_name(dev), ret,
9207 ktime_to_us(ktime_sub(ktime_get(), start)),
9208 hba->curr_dev_pwr_mode, hba->uic_link_state);
9214 #ifdef CONFIG_PM_SLEEP
9215 static int ufshcd_wl_suspend(struct device *dev)
9217 struct scsi_device *sdev = to_scsi_device(dev);
9218 struct ufs_hba *hba;
9220 ktime_t start = ktime_get();
9222 hba = shost_priv(sdev->host);
9223 down(&hba->host_sem);
9225 if (pm_runtime_suspended(dev))
9228 ret = __ufshcd_wl_suspend(hba, UFS_SYSTEM_PM);
9230 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9236 hba->is_sys_suspended = true;
9237 trace_ufshcd_wl_suspend(dev_name(dev), ret,
9238 ktime_to_us(ktime_sub(ktime_get(), start)),
9239 hba->curr_dev_pwr_mode, hba->uic_link_state);
9244 static int ufshcd_wl_resume(struct device *dev)
9246 struct scsi_device *sdev = to_scsi_device(dev);
9247 struct ufs_hba *hba;
9249 ktime_t start = ktime_get();
9251 hba = shost_priv(sdev->host);
9253 if (pm_runtime_suspended(dev))
9256 ret = __ufshcd_wl_resume(hba, UFS_SYSTEM_PM);
9258 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret);
9260 trace_ufshcd_wl_resume(dev_name(dev), ret,
9261 ktime_to_us(ktime_sub(ktime_get(), start)),
9262 hba->curr_dev_pwr_mode, hba->uic_link_state);
9264 hba->is_sys_suspended = false;
9270 static void ufshcd_wl_shutdown(struct device *dev)
9272 struct scsi_device *sdev = to_scsi_device(dev);
9273 struct ufs_hba *hba;
9275 hba = shost_priv(sdev->host);
9277 down(&hba->host_sem);
9278 hba->shutting_down = true;
9281 /* Turn on everything while shutting down */
9282 ufshcd_rpm_get_sync(hba);
9283 scsi_device_quiesce(sdev);
9284 shost_for_each_device(sdev, hba->host) {
9285 if (sdev == hba->ufs_device_wlun)
9287 scsi_device_quiesce(sdev);
9289 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
9293 * ufshcd_suspend - helper function for suspend operations
9294 * @hba: per adapter instance
9296 * This function will put disable irqs, turn off clocks
9297 * and set vreg and hba-vreg in lpm mode.
9299 static int ufshcd_suspend(struct ufs_hba *hba)
9303 if (!hba->is_powered)
9306 * Disable the host irq as host controller as there won't be any
9307 * host controller transaction expected till resume.
9309 ufshcd_disable_irq(hba);
9310 ret = ufshcd_setup_clocks(hba, false);
9312 ufshcd_enable_irq(hba);
9315 if (ufshcd_is_clkgating_allowed(hba)) {
9316 hba->clk_gating.state = CLKS_OFF;
9317 trace_ufshcd_clk_gating(dev_name(hba->dev),
9318 hba->clk_gating.state);
9321 ufshcd_vreg_set_lpm(hba);
9322 /* Put the host controller in low power mode if possible */
9323 ufshcd_hba_vreg_set_lpm(hba);
9329 * ufshcd_resume - helper function for resume operations
9330 * @hba: per adapter instance
9332 * This function basically turns on the regulators, clocks and
9335 * Returns 0 for success and non-zero for failure
9337 static int ufshcd_resume(struct ufs_hba *hba)
9341 if (!hba->is_powered)
9344 ufshcd_hba_vreg_set_hpm(hba);
9345 ret = ufshcd_vreg_set_hpm(hba);
9349 /* Make sure clocks are enabled before accessing controller */
9350 ret = ufshcd_setup_clocks(hba, true);
9354 /* enable the host irq as host controller would be active soon */
9355 ufshcd_enable_irq(hba);
9359 ufshcd_vreg_set_lpm(hba);
9362 ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)ret);
9365 #endif /* CONFIG_PM */
9367 #ifdef CONFIG_PM_SLEEP
9369 * ufshcd_system_suspend - system suspend callback
9370 * @dev: Device associated with the UFS controller.
9372 * Executed before putting the system into a sleep state in which the contents
9373 * of main memory are preserved.
9375 * Returns 0 for success and non-zero for failure
9377 int ufshcd_system_suspend(struct device *dev)
9379 struct ufs_hba *hba = dev_get_drvdata(dev);
9381 ktime_t start = ktime_get();
9383 if (pm_runtime_suspended(hba->dev))
9386 ret = ufshcd_suspend(hba);
9388 trace_ufshcd_system_suspend(dev_name(hba->dev), ret,
9389 ktime_to_us(ktime_sub(ktime_get(), start)),
9390 hba->curr_dev_pwr_mode, hba->uic_link_state);
9393 EXPORT_SYMBOL(ufshcd_system_suspend);
9396 * ufshcd_system_resume - system resume callback
9397 * @dev: Device associated with the UFS controller.
9399 * Executed after waking the system up from a sleep state in which the contents
9400 * of main memory were preserved.
9402 * Returns 0 for success and non-zero for failure
9404 int ufshcd_system_resume(struct device *dev)
9406 struct ufs_hba *hba = dev_get_drvdata(dev);
9407 ktime_t start = ktime_get();
9410 if (pm_runtime_suspended(hba->dev))
9413 ret = ufshcd_resume(hba);
9416 trace_ufshcd_system_resume(dev_name(hba->dev), ret,
9417 ktime_to_us(ktime_sub(ktime_get(), start)),
9418 hba->curr_dev_pwr_mode, hba->uic_link_state);
9422 EXPORT_SYMBOL(ufshcd_system_resume);
9423 #endif /* CONFIG_PM_SLEEP */
9427 * ufshcd_runtime_suspend - runtime suspend callback
9428 * @dev: Device associated with the UFS controller.
9430 * Check the description of ufshcd_suspend() function for more details.
9432 * Returns 0 for success and non-zero for failure
9434 int ufshcd_runtime_suspend(struct device *dev)
9436 struct ufs_hba *hba = dev_get_drvdata(dev);
9438 ktime_t start = ktime_get();
9440 ret = ufshcd_suspend(hba);
9442 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret,
9443 ktime_to_us(ktime_sub(ktime_get(), start)),
9444 hba->curr_dev_pwr_mode, hba->uic_link_state);
9447 EXPORT_SYMBOL(ufshcd_runtime_suspend);
9450 * ufshcd_runtime_resume - runtime resume routine
9451 * @dev: Device associated with the UFS controller.
9453 * This function basically brings controller
9454 * to active state. Following operations are done in this function:
9456 * 1. Turn on all the controller related clocks
9457 * 2. Turn ON VCC rail
9459 int ufshcd_runtime_resume(struct device *dev)
9461 struct ufs_hba *hba = dev_get_drvdata(dev);
9463 ktime_t start = ktime_get();
9465 ret = ufshcd_resume(hba);
9467 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret,
9468 ktime_to_us(ktime_sub(ktime_get(), start)),
9469 hba->curr_dev_pwr_mode, hba->uic_link_state);
9472 EXPORT_SYMBOL(ufshcd_runtime_resume);
9473 #endif /* CONFIG_PM */
9476 * ufshcd_shutdown - shutdown routine
9477 * @hba: per adapter instance
9479 * This function would turn off both UFS device and UFS hba
9480 * regulators. It would also disable clocks.
9482 * Returns 0 always to allow force shutdown even in case of errors.
9484 int ufshcd_shutdown(struct ufs_hba *hba)
9486 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba))
9489 pm_runtime_get_sync(hba->dev);
9491 ufshcd_suspend(hba);
9493 hba->is_powered = false;
9494 /* allow force shutdown even in case of errors */
9497 EXPORT_SYMBOL(ufshcd_shutdown);
9500 * ufshcd_remove - de-allocate SCSI host and host memory space
9501 * data structure memory
9502 * @hba: per adapter instance
9504 void ufshcd_remove(struct ufs_hba *hba)
9506 if (hba->ufs_device_wlun)
9507 ufshcd_rpm_get_sync(hba);
9508 ufs_hwmon_remove(hba);
9509 ufs_bsg_remove(hba);
9511 ufs_sysfs_remove_nodes(hba->dev);
9512 blk_mq_destroy_queue(hba->tmf_queue);
9513 blk_mq_free_tag_set(&hba->tmf_tag_set);
9514 scsi_remove_host(hba->host);
9515 /* disable interrupts */
9516 ufshcd_disable_intr(hba, hba->intr_mask);
9517 ufshcd_hba_stop(hba);
9518 ufshcd_hba_exit(hba);
9520 EXPORT_SYMBOL_GPL(ufshcd_remove);
9523 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA)
9524 * @hba: pointer to Host Bus Adapter (HBA)
9526 void ufshcd_dealloc_host(struct ufs_hba *hba)
9528 scsi_host_put(hba->host);
9530 EXPORT_SYMBOL_GPL(ufshcd_dealloc_host);
9533 * ufshcd_set_dma_mask - Set dma mask based on the controller
9534 * addressing capability
9535 * @hba: per adapter instance
9537 * Returns 0 for success, non-zero for failure
9539 static int ufshcd_set_dma_mask(struct ufs_hba *hba)
9541 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) {
9542 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64)))
9545 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32));
9549 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA)
9550 * @dev: pointer to device handle
9551 * @hba_handle: driver private handle
9552 * Returns 0 on success, non-zero value on failure
9554 int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle)
9556 struct Scsi_Host *host;
9557 struct ufs_hba *hba;
9562 "Invalid memory reference for dev is NULL\n");
9567 host = scsi_host_alloc(&ufshcd_driver_template,
9568 sizeof(struct ufs_hba));
9570 dev_err(dev, "scsi_host_alloc failed\n");
9574 host->nr_maps = HCTX_TYPE_POLL + 1;
9575 hba = shost_priv(host);
9578 hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL;
9579 hba->nop_out_timeout = NOP_OUT_TIMEOUT;
9580 INIT_LIST_HEAD(&hba->clk_list_head);
9581 spin_lock_init(&hba->outstanding_lock);
9588 EXPORT_SYMBOL(ufshcd_alloc_host);
9590 /* This function exists because blk_mq_alloc_tag_set() requires this. */
9591 static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx,
9592 const struct blk_mq_queue_data *qd)
9595 return BLK_STS_NOTSUPP;
9598 static const struct blk_mq_ops ufshcd_tmf_ops = {
9599 .queue_rq = ufshcd_queue_tmf,
9603 * ufshcd_init - Driver initialization routine
9604 * @hba: per-adapter instance
9605 * @mmio_base: base register address
9606 * @irq: Interrupt line of device
9607 * Returns 0 on success, non-zero value on failure
9609 int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq)
9612 struct Scsi_Host *host = hba->host;
9613 struct device *dev = hba->dev;
9614 char eh_wq_name[sizeof("ufs_eh_wq_00")];
9617 * dev_set_drvdata() must be called before any callbacks are registered
9618 * that use dev_get_drvdata() (frequency scaling, clock scaling, hwmon,
9621 dev_set_drvdata(dev, hba);
9625 "Invalid memory reference for mmio_base is NULL\n");
9630 hba->mmio_base = mmio_base;
9632 hba->vps = &ufs_hba_vps;
9634 err = ufshcd_hba_init(hba);
9638 /* Read capabilities registers */
9639 err = ufshcd_hba_capabilities(hba);
9643 /* Get UFS version supported by the controller */
9644 hba->ufs_version = ufshcd_get_ufs_version(hba);
9646 /* Get Interrupt bit mask per version */
9647 hba->intr_mask = ufshcd_get_intr_mask(hba);
9649 err = ufshcd_set_dma_mask(hba);
9651 dev_err(hba->dev, "set dma mask failed\n");
9655 /* Allocate memory for host memory space */
9656 err = ufshcd_memory_alloc(hba);
9658 dev_err(hba->dev, "Memory allocation failed\n");
9663 ufshcd_host_memory_configure(hba);
9665 host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED;
9666 host->cmd_per_lun = hba->nutrs - UFSHCD_NUM_RESERVED;
9667 host->max_id = UFSHCD_MAX_ID;
9668 host->max_lun = UFS_MAX_LUNS;
9669 host->max_channel = UFSHCD_MAX_CHANNEL;
9670 host->unique_id = host->host_no;
9671 host->max_cmd_len = UFS_CDB_SIZE;
9673 hba->max_pwr_info.is_valid = false;
9675 /* Initialize work queues */
9676 snprintf(eh_wq_name, sizeof(eh_wq_name), "ufs_eh_wq_%d",
9677 hba->host->host_no);
9678 hba->eh_wq = create_singlethread_workqueue(eh_wq_name);
9680 dev_err(hba->dev, "%s: failed to create eh workqueue\n",
9685 INIT_WORK(&hba->eh_work, ufshcd_err_handler);
9686 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler);
9688 sema_init(&hba->host_sem, 1);
9690 /* Initialize UIC command mutex */
9691 mutex_init(&hba->uic_cmd_mutex);
9693 /* Initialize mutex for device management commands */
9694 mutex_init(&hba->dev_cmd.lock);
9696 /* Initialize mutex for exception event control */
9697 mutex_init(&hba->ee_ctrl_mutex);
9699 init_rwsem(&hba->clk_scaling_lock);
9701 ufshcd_init_clk_gating(hba);
9703 ufshcd_init_clk_scaling(hba);
9706 * In order to avoid any spurious interrupt immediately after
9707 * registering UFS controller interrupt handler, clear any pending UFS
9708 * interrupt status and disable all the UFS interrupts.
9710 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
9711 REG_INTERRUPT_STATUS);
9712 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
9714 * Make sure that UFS interrupts are disabled and any pending interrupt
9715 * status is cleared before registering UFS interrupt handler.
9719 /* IRQ registration */
9720 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
9722 dev_err(hba->dev, "request irq failed\n");
9725 hba->is_irq_enabled = true;
9728 err = scsi_add_host(host, hba->dev);
9730 dev_err(hba->dev, "scsi_add_host failed\n");
9734 hba->tmf_tag_set = (struct blk_mq_tag_set) {
9736 .queue_depth = hba->nutmrs,
9737 .ops = &ufshcd_tmf_ops,
9738 .flags = BLK_MQ_F_NO_SCHED,
9740 err = blk_mq_alloc_tag_set(&hba->tmf_tag_set);
9742 goto out_remove_scsi_host;
9743 hba->tmf_queue = blk_mq_init_queue(&hba->tmf_tag_set);
9744 if (IS_ERR(hba->tmf_queue)) {
9745 err = PTR_ERR(hba->tmf_queue);
9746 goto free_tmf_tag_set;
9748 hba->tmf_rqs = devm_kcalloc(hba->dev, hba->nutmrs,
9749 sizeof(*hba->tmf_rqs), GFP_KERNEL);
9750 if (!hba->tmf_rqs) {
9752 goto free_tmf_queue;
9755 /* Reset the attached device */
9756 ufshcd_device_reset(hba);
9758 ufshcd_init_crypto(hba);
9760 /* Host controller enable */
9761 err = ufshcd_hba_enable(hba);
9763 dev_err(hba->dev, "Host controller enable failed\n");
9764 ufshcd_print_evt_hist(hba);
9765 ufshcd_print_host_state(hba);
9766 goto free_tmf_queue;
9770 * Set the default power management level for runtime and system PM.
9771 * Default power saving mode is to keep UFS link in Hibern8 state
9772 * and UFS device in sleep state.
9774 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
9776 UIC_LINK_HIBERN8_STATE);
9777 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state(
9779 UIC_LINK_HIBERN8_STATE);
9781 INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work,
9782 ufshcd_rpm_dev_flush_recheck_work);
9784 /* Set the default auto-hiberate idle timer value to 150 ms */
9785 if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) {
9786 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) |
9787 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3);
9790 /* Hold auto suspend until async scan completes */
9791 pm_runtime_get_sync(dev);
9792 atomic_set(&hba->scsi_block_reqs_cnt, 0);
9794 * We are assuming that device wasn't put in sleep/power-down
9795 * state exclusively during the boot stage before kernel.
9796 * This assumption helps avoid doing link startup twice during
9797 * ufshcd_probe_hba().
9799 ufshcd_set_ufs_dev_active(hba);
9801 async_schedule(ufshcd_async_scan, hba);
9802 ufs_sysfs_add_nodes(hba->dev);
9804 device_enable_async_suspend(dev);
9808 blk_mq_destroy_queue(hba->tmf_queue);
9810 blk_mq_free_tag_set(&hba->tmf_tag_set);
9811 out_remove_scsi_host:
9812 scsi_remove_host(hba->host);
9814 hba->is_irq_enabled = false;
9815 ufshcd_hba_exit(hba);
9819 EXPORT_SYMBOL_GPL(ufshcd_init);
9821 void ufshcd_resume_complete(struct device *dev)
9823 struct ufs_hba *hba = dev_get_drvdata(dev);
9825 if (hba->complete_put) {
9826 ufshcd_rpm_put(hba);
9827 hba->complete_put = false;
9830 EXPORT_SYMBOL_GPL(ufshcd_resume_complete);
9832 static bool ufshcd_rpm_ok_for_spm(struct ufs_hba *hba)
9834 struct device *dev = &hba->ufs_device_wlun->sdev_gendev;
9835 enum ufs_dev_pwr_mode dev_pwr_mode;
9836 enum uic_link_state link_state;
9837 unsigned long flags;
9840 spin_lock_irqsave(&dev->power.lock, flags);
9841 dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl);
9842 link_state = ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl);
9843 res = pm_runtime_suspended(dev) &&
9844 hba->curr_dev_pwr_mode == dev_pwr_mode &&
9845 hba->uic_link_state == link_state &&
9846 !hba->dev_info.b_rpm_dev_flush_capable;
9847 spin_unlock_irqrestore(&dev->power.lock, flags);
9852 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm)
9854 struct ufs_hba *hba = dev_get_drvdata(dev);
9858 * SCSI assumes that runtime-pm and system-pm for scsi drivers
9859 * are same. And it doesn't wake up the device for system-suspend
9860 * if it's runtime suspended. But ufs doesn't follow that.
9861 * Refer ufshcd_resume_complete()
9863 if (hba->ufs_device_wlun) {
9864 /* Prevent runtime suspend */
9865 ufshcd_rpm_get_noresume(hba);
9867 * Check if already runtime suspended in same state as system
9870 if (!rpm_ok_for_spm || !ufshcd_rpm_ok_for_spm(hba)) {
9871 /* RPM state is not ok for SPM, so runtime resume */
9872 ret = ufshcd_rpm_resume(hba);
9873 if (ret < 0 && ret != -EACCES) {
9874 ufshcd_rpm_put(hba);
9878 hba->complete_put = true;
9882 EXPORT_SYMBOL_GPL(__ufshcd_suspend_prepare);
9884 int ufshcd_suspend_prepare(struct device *dev)
9886 return __ufshcd_suspend_prepare(dev, true);
9888 EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare);
9890 #ifdef CONFIG_PM_SLEEP
9891 static int ufshcd_wl_poweroff(struct device *dev)
9893 struct scsi_device *sdev = to_scsi_device(dev);
9894 struct ufs_hba *hba = shost_priv(sdev->host);
9896 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM);
9901 static int ufshcd_wl_probe(struct device *dev)
9903 struct scsi_device *sdev = to_scsi_device(dev);
9905 if (!is_device_wlun(sdev))
9908 blk_pm_runtime_init(sdev->request_queue, dev);
9909 pm_runtime_set_autosuspend_delay(dev, 0);
9910 pm_runtime_allow(dev);
9915 static int ufshcd_wl_remove(struct device *dev)
9917 pm_runtime_forbid(dev);
9921 static const struct dev_pm_ops ufshcd_wl_pm_ops = {
9922 #ifdef CONFIG_PM_SLEEP
9923 .suspend = ufshcd_wl_suspend,
9924 .resume = ufshcd_wl_resume,
9925 .freeze = ufshcd_wl_suspend,
9926 .thaw = ufshcd_wl_resume,
9927 .poweroff = ufshcd_wl_poweroff,
9928 .restore = ufshcd_wl_resume,
9930 SET_RUNTIME_PM_OPS(ufshcd_wl_runtime_suspend, ufshcd_wl_runtime_resume, NULL)
9934 * ufs_dev_wlun_template - describes ufs device wlun
9935 * ufs-device wlun - used to send pm commands
9936 * All luns are consumers of ufs-device wlun.
9938 * Currently, no sd driver is present for wluns.
9939 * Hence the no specific pm operations are performed.
9940 * With ufs design, SSU should be sent to ufs-device wlun.
9941 * Hence register a scsi driver for ufs wluns only.
9943 static struct scsi_driver ufs_dev_wlun_template = {
9945 .name = "ufs_device_wlun",
9946 .owner = THIS_MODULE,
9947 .probe = ufshcd_wl_probe,
9948 .remove = ufshcd_wl_remove,
9949 .pm = &ufshcd_wl_pm_ops,
9950 .shutdown = ufshcd_wl_shutdown,
9954 static int __init ufshcd_core_init(void)
9958 /* Verify that there are no gaps in struct utp_transfer_cmd_desc. */
9959 static_assert(sizeof(struct utp_transfer_cmd_desc) ==
9960 2 * ALIGNED_UPIU_SIZE +
9961 SG_ALL * sizeof(struct ufshcd_sg_entry));
9965 ret = scsi_register_driver(&ufs_dev_wlun_template.gendrv);
9971 static void __exit ufshcd_core_exit(void)
9974 scsi_unregister_driver(&ufs_dev_wlun_template.gendrv);
9977 module_init(ufshcd_core_init);
9978 module_exit(ufshcd_core_exit);
9980 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
9981 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
9982 MODULE_DESCRIPTION("Generic UFS host controller driver Core");
9983 MODULE_LICENSE("GPL");