drivers/tty/serial/sunzilog.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* sunzilog.c: Zilog serial driver for Sparc systems.
   3  *
   4  * Driver for Zilog serial chips found on Sun workstations and
   5  * servers.  This driver could actually be made more generic.
   6  *
   7  * This is based on the old drivers/sbus/char/zs.c code.  A lot
   8  * of code has been simply moved over directly from there but
   9  * much has been rewritten.  Credits therefore go out to Eddie
  10  * C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell for their
  11  * work there.
  12  *
  13  * Copyright (C) 2002, 2006, 2007 David S. Miller (davem@davemloft.net)
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/kernel.h>
  18 #include <linux/errno.h>
  19 #include <linux/delay.h>
  20 #include <linux/tty.h>
  21 #include <linux/tty_flip.h>
  22 #include <linux/major.h>
  23 #include <linux/string.h>
  24 #include <linux/ptrace.h>
  25 #include <linux/ioport.h>
  26 #include <linux/slab.h>
  27 #include <linux/circ_buf.h>
  28 #include <linux/serial.h>
  29 #include <linux/sysrq.h>
  30 #include <linux/console.h>
  31 #include <linux/spinlock.h>
  32 #ifdef CONFIG_SERIO
  33 #include <linux/serio.h>
  34 #endif
  35 #include <linux/init.h>
  36 #include <linux/of_device.h>
  37
  38 #include <linux/io.h>
  39 #include <asm/irq.h>
  40 #include <asm/prom.h>
  41 #include <asm/setup.h>
  42
  43 #include <linux/serial_core.h>
  44 #include <linux/sunserialcore.h>
  45
  46 #include "sunzilog.h"
  47
  48 /* On 32-bit sparcs we need to delay after register accesses
  49  * to accommodate sun4 systems, but we do not need to flush writes.
  50  * On 64-bit sparc we only need to flush single writes to ensure
  51  * completion.
  52  */
  53 #ifndef CONFIG_SPARC64
  54 #define ZSDELAY()               udelay(5)
  55 #define ZSDELAY_LONG()          udelay(20)
  56 #define ZS_WSYNC(channel)       do { } while (0)
  57 #else
  58 #define ZSDELAY()
  59 #define ZSDELAY_LONG()
  60 #define ZS_WSYNC(__channel) \
  61         readb(&((__channel)->control))
  62 #endif
  63
  64 #define ZS_CLOCK                4915200 /* Zilog input clock rate. */
  65 #define ZS_CLOCK_DIVISOR        16      /* Divisor this driver uses. */
  66
  67 /*
  68  * We wrap our port structure around the generic uart_port.
  69  */
  70 struct uart_sunzilog_port {
  71         struct uart_port                port;
  72
  73         /* IRQ servicing chain.  */
  74         struct uart_sunzilog_port       *next;
  75
  76         /* Current values of Zilog write registers.  */
  77         unsigned char                   curregs[NUM_ZSREGS];
  78
  79         unsigned int                    flags;
  80 #define SUNZILOG_FLAG_CONS_KEYB         0x00000001
  81 #define SUNZILOG_FLAG_CONS_MOUSE        0x00000002
  82 #define SUNZILOG_FLAG_IS_CONS           0x00000004
  83 #define SUNZILOG_FLAG_IS_KGDB           0x00000008
  84 #define SUNZILOG_FLAG_MODEM_STATUS      0x00000010
  85 #define SUNZILOG_FLAG_IS_CHANNEL_A      0x00000020
  86 #define SUNZILOG_FLAG_REGS_HELD         0x00000040
  87 #define SUNZILOG_FLAG_TX_STOPPED        0x00000080
  88 #define SUNZILOG_FLAG_TX_ACTIVE         0x00000100
  89 #define SUNZILOG_FLAG_ESCC              0x00000200
  90 #define SUNZILOG_FLAG_ISR_HANDLER       0x00000400
  91
  92         unsigned int cflag;
  93
  94         unsigned char                   parity_mask;
  95         unsigned char                   prev_status;
  96
  97 #ifdef CONFIG_SERIO
  98         struct serio                    serio;
  99         int                             serio_open;
 100 #endif
 101 };
 102
 103 static void sunzilog_putchar(struct uart_port *port, int ch);
 104
 105 #define ZILOG_CHANNEL_FROM_PORT(PORT)   ((struct zilog_channel __iomem *)((PORT)->membase))
 106 #define UART_ZILOG(PORT)                ((struct uart_sunzilog_port *)(PORT))
 107
 108 #define ZS_IS_KEYB(UP)  ((UP)->flags & SUNZILOG_FLAG_CONS_KEYB)
 109 #define ZS_IS_MOUSE(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_MOUSE)
 110 #define ZS_IS_CONS(UP)  ((UP)->flags & SUNZILOG_FLAG_IS_CONS)
 111 #define ZS_IS_KGDB(UP)  ((UP)->flags & SUNZILOG_FLAG_IS_KGDB)
 112 #define ZS_WANTS_MODEM_STATUS(UP)       ((UP)->flags & SUNZILOG_FLAG_MODEM_STATUS)
 113 #define ZS_IS_CHANNEL_A(UP)     ((UP)->flags & SUNZILOG_FLAG_IS_CHANNEL_A)
 114 #define ZS_REGS_HELD(UP)        ((UP)->flags & SUNZILOG_FLAG_REGS_HELD)
 115 #define ZS_TX_STOPPED(UP)       ((UP)->flags & SUNZILOG_FLAG_TX_STOPPED)
 116 #define ZS_TX_ACTIVE(UP)        ((UP)->flags & SUNZILOG_FLAG_TX_ACTIVE)
 117
 118 /* Reading and writing Zilog8530 registers.  The delays are to make this
 119  * driver work on the Sun4 which needs a settling delay after each chip
 120  * register access, other machines handle this in hardware via auxiliary
 121  * flip-flops which implement the settle time we do in software.
 122  *
 123  * The port lock must be held and local IRQs must be disabled
 124  * when {read,write}_zsreg is invoked.
 125  */
 126 static unsigned char read_zsreg(struct zilog_channel __iomem *channel,
 127                                 unsigned char reg)
 128 {
 129         unsigned char retval;
 130
 131         writeb(reg, &channel->control);
 132         ZSDELAY();
 133         retval = readb(&channel->control);
 134         ZSDELAY();
 135
 136         return retval;
 137 }
 138
 139 static void write_zsreg(struct zilog_channel __iomem *channel,
 140                         unsigned char reg, unsigned char value)
 141 {
 142         writeb(reg, &channel->control);
 143         ZSDELAY();
 144         writeb(value, &channel->control);
 145         ZSDELAY();
 146 }
 147
 148 static void sunzilog_clear_fifo(struct zilog_channel __iomem *channel)
 149 {
 150         int i;
 151
 152         for (i = 0; i < 32; i++) {
 153                 unsigned char regval;
 154
 155                 regval = readb(&channel->control);
 156                 ZSDELAY();
 157                 if (regval & Rx_CH_AV)
 158                         break;
 159
 160                 regval = read_zsreg(channel, R1);
 161                 readb(&channel->data);
 162                 ZSDELAY();
 163
 164                 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
 165                         writeb(ERR_RES, &channel->control);
 166                         ZSDELAY();
 167                         ZS_WSYNC(channel);
 168                 }
 169         }
 170 }
 171
 172 /* This function must only be called when the TX is not busy.  The UART
 173  * port lock must be held and local interrupts disabled.
 174  */
 175 static int __load_zsregs(struct zilog_channel __iomem *channel, unsigned char *regs)
 176 {
 177         int i;
 178         int escc;
 179         unsigned char r15;
 180
 181         /* Let pending transmits finish.  */
 182         for (i = 0; i < 1000; i++) {
 183                 unsigned char stat = read_zsreg(channel, R1);
 184                 if (stat & ALL_SNT)
 185                         break;
 186                 udelay(100);
 187         }
 188
 189         writeb(ERR_RES, &channel->control);
 190         ZSDELAY();
 191         ZS_WSYNC(channel);
 192
 193         sunzilog_clear_fifo(channel);
 194
 195         /* Disable all interrupts.  */
 196         write_zsreg(channel, R1,
 197                     regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
 198
 199         /* Set parity, sync config, stop bits, and clock divisor.  */
 200         write_zsreg(channel, R4, regs[R4]);
 201
 202         /* Set misc. TX/RX control bits.  */
 203         write_zsreg(channel, R10, regs[R10]);
 204
 205         /* Set TX/RX controls sans the enable bits.  */
 206         write_zsreg(channel, R3, regs[R3] & ~RxENAB);
 207         write_zsreg(channel, R5, regs[R5] & ~TxENAB);
 208
 209         /* Synchronous mode config.  */
 210         write_zsreg(channel, R6, regs[R6]);
 211         write_zsreg(channel, R7, regs[R7]);
 212
 213         /* Don't mess with the interrupt vector (R2, unused by us) and
 214          * master interrupt control (R9).  We make sure this is setup
 215          * properly at probe time then never touch it again.
 216          */
 217
 218         /* Disable baud generator.  */
 219         write_zsreg(channel, R14, regs[R14] & ~BRENAB);
 220
 221         /* Clock mode control.  */
 222         write_zsreg(channel, R11, regs[R11]);
 223
 224         /* Lower and upper byte of baud rate generator divisor.  */
 225         write_zsreg(channel, R12, regs[R12]);
 226         write_zsreg(channel, R13, regs[R13]);
 227
 228         /* Now rewrite R14, with BRENAB (if set).  */
 229         write_zsreg(channel, R14, regs[R14]);
 230
 231         /* External status interrupt control.  */
 232         write_zsreg(channel, R15, (regs[R15] | WR7pEN) & ~FIFOEN);
 233
 234         /* ESCC Extension Register */
 235         r15 = read_zsreg(channel, R15);
 236         if (r15 & 0x01) {
 237                 write_zsreg(channel, R7,  regs[R7p]);
 238
 239                 /* External status interrupt and FIFO control.  */
 240                 write_zsreg(channel, R15, regs[R15] & ~WR7pEN);
 241                 escc = 1;
 242         } else {
 243                  /* Clear FIFO bit case it is an issue */
 244                 regs[R15] &= ~FIFOEN;
 245                 escc = 0;
 246         }
 247
 248         /* Reset external status interrupts.  */
 249         write_zsreg(channel, R0, RES_EXT_INT); /* First Latch  */
 250         write_zsreg(channel, R0, RES_EXT_INT); /* Second Latch */
 251
 252         /* Rewrite R3/R5, this time without enables masked.  */
 253         write_zsreg(channel, R3, regs[R3]);
 254         write_zsreg(channel, R5, regs[R5]);
 255
 256         /* Rewrite R1, this time without IRQ enabled masked.  */
 257         write_zsreg(channel, R1, regs[R1]);
 258
 259         return escc;
 260 }
 261
 262 /* Reprogram the Zilog channel HW registers with the copies found in the
 263  * software state struct.  If the transmitter is busy, we defer this update
 264  * until the next TX complete interrupt.  Else, we do it right now.
 265  *
 266  * The UART port lock must be held and local interrupts disabled.
 267  */
 268 static void sunzilog_maybe_update_regs(struct uart_sunzilog_port *up,
 269                                        struct zilog_channel __iomem *channel)
 270 {
 271         if (!ZS_REGS_HELD(up)) {
 272                 if (ZS_TX_ACTIVE(up)) {
 273                         up->flags |= SUNZILOG_FLAG_REGS_HELD;
 274                 } else {
 275                         __load_zsregs(channel, up->curregs);
 276                 }
 277         }
 278 }
 279
 280 static void sunzilog_change_mouse_baud(struct uart_sunzilog_port *up)
 281 {
 282         unsigned int cur_cflag = up->cflag;
 283         int brg, new_baud;
 284
 285         up->cflag &= ~CBAUD;
 286         up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
 287
 288         brg = BPS_TO_BRG(new_baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
 289         up->curregs[R12] = (brg & 0xff);
 290         up->curregs[R13] = (brg >> 8) & 0xff;
 291         sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(&up->port));
 292 }
 293
 294 static void sunzilog_kbdms_receive_chars(struct uart_sunzilog_port *up,
 295                                          unsigned char ch, int is_break)
 296 {
 297         if (ZS_IS_KEYB(up)) {
 298                 /* Stop-A is handled by drivers/char/keyboard.c now. */
 299 #ifdef CONFIG_SERIO
 300                 if (up->serio_open)
 301                         serio_interrupt(&up->serio, ch, 0);
 302 #endif
 303         } else if (ZS_IS_MOUSE(up)) {
 304                 int ret = suncore_mouse_baud_detection(ch, is_break);
 305
 306                 switch (ret) {
 307                 case 2:
 308                         sunzilog_change_mouse_baud(up);
 309                         fallthrough;
 310                 case 1:
 311                         break;
 312
 313                 case 0:
 314 #ifdef CONFIG_SERIO
 315                         if (up->serio_open)
 316                                 serio_interrupt(&up->serio, ch, 0);
 317 #endif
 318                         break;
 319                 }
 320         }
 321 }
 322
 323 static struct tty_port *
 324 sunzilog_receive_chars(struct uart_sunzilog_port *up,
 325                        struct zilog_channel __iomem *channel)
 326 {
 327         struct tty_port *port = NULL;
 328         unsigned char ch, r1, flag;
 329
 330         if (up->port.state != NULL)             /* Unopened serial console */
 331                 port = &up->port.state->port;
 332
 333         for (;;) {
 334
 335                 r1 = read_zsreg(channel, R1);
 336                 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
 337                         writeb(ERR_RES, &channel->control);
 338                         ZSDELAY();
 339                         ZS_WSYNC(channel);
 340                 }
 341
 342                 ch = readb(&channel->control);
 343                 ZSDELAY();
 344
 345                 /* This funny hack depends upon BRK_ABRT not interfering
 346                  * with the other bits we care about in R1.
 347                  */
 348                 if (ch & BRK_ABRT)
 349                         r1 |= BRK_ABRT;
 350
 351                 if (!(ch & Rx_CH_AV))
 352                         break;
 353
 354                 ch = readb(&channel->data);
 355                 ZSDELAY();
 356
 357                 ch &= up->parity_mask;
 358
 359                 if (unlikely(ZS_IS_KEYB(up)) || unlikely(ZS_IS_MOUSE(up))) {
 360                         sunzilog_kbdms_receive_chars(up, ch, 0);
 361                         continue;
 362                 }
 363
 364                 /* A real serial line, record the character and status.  */
 365                 flag = TTY_NORMAL;
 366                 up->port.icount.rx++;
 367                 if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) {
 368                         if (r1 & BRK_ABRT) {
 369                                 r1 &= ~(PAR_ERR | CRC_ERR);
 370                                 up->port.icount.brk++;
 371                                 if (uart_handle_break(&up->port))
 372                                         continue;
 373                         }
 374                         else if (r1 & PAR_ERR)
 375                                 up->port.icount.parity++;
 376                         else if (r1 & CRC_ERR)
 377                                 up->port.icount.frame++;
 378                         if (r1 & Rx_OVR)
 379                                 up->port.icount.overrun++;
 380                         r1 &= up->port.read_status_mask;
 381                         if (r1 & BRK_ABRT)
 382                                 flag = TTY_BREAK;
 383                         else if (r1 & PAR_ERR)
 384                                 flag = TTY_PARITY;
 385                         else if (r1 & CRC_ERR)
 386                                 flag = TTY_FRAME;
 387                 }
 388                 if (uart_handle_sysrq_char(&up->port, ch) || !port)
 389                         continue;
 390
 391                 if (up->port.ignore_status_mask == 0xff ||
 392                     (r1 & up->port.ignore_status_mask) == 0) {
 393                         tty_insert_flip_char(port, ch, flag);
 394                 }
 395                 if (r1 & Rx_OVR)
 396                         tty_insert_flip_char(port, 0, TTY_OVERRUN);
 397         }
 398
 399         return port;
 400 }
 401
 402 static void sunzilog_status_handle(struct uart_sunzilog_port *up,
 403                                    struct zilog_channel __iomem *channel)
 404 {
 405         unsigned char status;
 406
 407         status = readb(&channel->control);
 408         ZSDELAY();
 409
 410         writeb(RES_EXT_INT, &channel->control);
 411         ZSDELAY();
 412         ZS_WSYNC(channel);
 413
 414         if (status & BRK_ABRT) {
 415                 if (ZS_IS_MOUSE(up))
 416                         sunzilog_kbdms_receive_chars(up, 0, 1);
 417                 if (ZS_IS_CONS(up)) {
 418                         /* Wait for BREAK to deassert to avoid potentially
 419                          * confusing the PROM.
 420                          */
 421                         while (1) {
 422                                 status = readb(&channel->control);
 423                                 ZSDELAY();
 424                                 if (!(status & BRK_ABRT))
 425                                         break;
 426                         }
 427                         sun_do_break();
 428                         return;
 429                 }
 430         }
 431
 432         if (ZS_WANTS_MODEM_STATUS(up)) {
 433                 if (status & SYNC)
 434                         up->port.icount.dsr++;
 435
 436                 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
 437                  * But it does not tell us which bit has changed, we have to keep
 438                  * track of this ourselves.
 439                  */
 440                 if ((status ^ up->prev_status) ^ DCD)
 441                         uart_handle_dcd_change(&up->port,
 442                                                (status & DCD));
 443                 if ((status ^ up->prev_status) ^ CTS)
 444                         uart_handle_cts_change(&up->port,
 445                                                (status & CTS));
 446
 447                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 448         }
 449
 450         up->prev_status = status;
 451 }
 452
 453 static void sunzilog_transmit_chars(struct uart_sunzilog_port *up,
 454                                     struct zilog_channel __iomem *channel)
 455 {
 456         struct circ_buf *xmit;
 457
 458         if (ZS_IS_CONS(up)) {
 459                 unsigned char status = readb(&channel->control);
 460                 ZSDELAY();
 461
 462                 /* TX still busy?  Just wait for the next TX done interrupt.
 463                  *
 464                  * It can occur because of how we do serial console writes.  It would
 465                  * be nice to transmit console writes just like we normally would for
 466                  * a TTY line. (ie. buffered and TX interrupt driven).  That is not
 467                  * easy because console writes cannot sleep.  One solution might be
 468                  * to poll on enough port->xmit space becoming free.  -DaveM
 469                  */
 470                 if (!(status & Tx_BUF_EMP))
 471                         return;
 472         }
 473
 474         up->flags &= ~SUNZILOG_FLAG_TX_ACTIVE;
 475
 476         if (ZS_REGS_HELD(up)) {
 477                 __load_zsregs(channel, up->curregs);
 478                 up->flags &= ~SUNZILOG_FLAG_REGS_HELD;
 479         }
 480
 481         if (ZS_TX_STOPPED(up)) {
 482                 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
 483                 goto ack_tx_int;
 484         }
 485
 486         if (up->port.x_char) {
 487                 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
 488                 writeb(up->port.x_char, &channel->data);
 489                 ZSDELAY();
 490                 ZS_WSYNC(channel);
 491
 492                 up->port.icount.tx++;
 493                 up->port.x_char = 0;
 494                 return;
 495         }
 496
 497         if (up->port.state == NULL)
 498                 goto ack_tx_int;
 499         xmit = &up->port.state->xmit;
 500         if (uart_circ_empty(xmit))
 501                 goto ack_tx_int;
 502
 503         if (uart_tx_stopped(&up->port))
 504                 goto ack_tx_int;
 505
 506         up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
 507         writeb(xmit->buf[xmit->tail], &channel->data);
 508         ZSDELAY();
 509         ZS_WSYNC(channel);
 510
 511         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 512         up->port.icount.tx++;
 513
 514         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 515                 uart_write_wakeup(&up->port);
 516
 517         return;
 518
 519 ack_tx_int:
 520         writeb(RES_Tx_P, &channel->control);
 521         ZSDELAY();
 522         ZS_WSYNC(channel);
 523 }
 524
 525 static irqreturn_t sunzilog_interrupt(int irq, void *dev_id)
 526 {
 527         struct uart_sunzilog_port *up = dev_id;
 528
 529         while (up) {
 530                 struct zilog_channel __iomem *channel
 531                         = ZILOG_CHANNEL_FROM_PORT(&up->port);
 532                 struct tty_port *port;
 533                 unsigned char r3;
 534
 535                 spin_lock(&up->port.lock);
 536                 r3 = read_zsreg(channel, R3);
 537
 538                 /* Channel A */
 539                 port = NULL;
 540                 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
 541                         writeb(RES_H_IUS, &channel->control);
 542                         ZSDELAY();
 543                         ZS_WSYNC(channel);
 544
 545                         if (r3 & CHARxIP)
 546                                 port = sunzilog_receive_chars(up, channel);
 547                         if (r3 & CHAEXT)
 548                                 sunzilog_status_handle(up, channel);
 549                         if (r3 & CHATxIP)
 550                                 sunzilog_transmit_chars(up, channel);
 551                 }
 552                 spin_unlock(&up->port.lock);
 553
 554                 if (port)
 555                         tty_flip_buffer_push(port);
 556
 557                 /* Channel B */
 558                 up = up->next;
 559                 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
 560
 561                 spin_lock(&up->port.lock);
 562                 port = NULL;
 563                 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
 564                         writeb(RES_H_IUS, &channel->control);
 565                         ZSDELAY();
 566                         ZS_WSYNC(channel);
 567
 568                         if (r3 & CHBRxIP)
 569                                 port = sunzilog_receive_chars(up, channel);
 570                         if (r3 & CHBEXT)
 571                                 sunzilog_status_handle(up, channel);
 572                         if (r3 & CHBTxIP)
 573                                 sunzilog_transmit_chars(up, channel);
 574                 }
 575                 spin_unlock(&up->port.lock);
 576
 577                 if (port)
 578                         tty_flip_buffer_push(port);
 579
 580                 up = up->next;
 581         }
 582
 583         return IRQ_HANDLED;
 584 }
 585
 586 /* A convenient way to quickly get R0 status.  The caller must _not_ hold the
 587  * port lock, it is acquired here.
 588  */
 589 static __inline__ unsigned char sunzilog_read_channel_status(struct uart_port *port)
 590 {
 591         struct zilog_channel __iomem *channel;
 592         unsigned char status;
 593
 594         channel = ZILOG_CHANNEL_FROM_PORT(port);
 595         status = readb(&channel->control);
 596         ZSDELAY();
 597
 598         return status;
 599 }
 600
 601 /* The port lock is not held.  */
 602 static unsigned int sunzilog_tx_empty(struct uart_port *port)
 603 {
 604         unsigned long flags;
 605         unsigned char status;
 606         unsigned int ret;
 607
 608         spin_lock_irqsave(&port->lock, flags);
 609
 610         status = sunzilog_read_channel_status(port);
 611
 612         spin_unlock_irqrestore(&port->lock, flags);
 613
 614         if (status & Tx_BUF_EMP)
 615                 ret = TIOCSER_TEMT;
 616         else
 617                 ret = 0;
 618
 619         return ret;
 620 }
 621
 622 /* The port lock is held and interrupts are disabled.  */
 623 static unsigned int sunzilog_get_mctrl(struct uart_port *port)
 624 {
 625         unsigned char status;
 626         unsigned int ret;
 627
 628         status = sunzilog_read_channel_status(port);
 629
 630         ret = 0;
 631         if (status & DCD)
 632                 ret |= TIOCM_CAR;
 633         if (status & SYNC)
 634                 ret |= TIOCM_DSR;
 635         if (status & CTS)
 636                 ret |= TIOCM_CTS;
 637
 638         return ret;
 639 }
 640
 641 /* The port lock is held and interrupts are disabled.  */
 642 static void sunzilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
 643 {
 644         struct uart_sunzilog_port *up =
 645                 container_of(port, struct uart_sunzilog_port, port);
 646         struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
 647         unsigned char set_bits, clear_bits;
 648
 649         set_bits = clear_bits = 0;
 650
 651         if (mctrl & TIOCM_RTS)
 652                 set_bits |= RTS;
 653         else
 654                 clear_bits |= RTS;
 655         if (mctrl & TIOCM_DTR)
 656                 set_bits |= DTR;
 657         else
 658                 clear_bits |= DTR;
 659
 660         /* NOTE: Not subject to 'transmitter active' rule.  */
 661         up->curregs[R5] |= set_bits;
 662         up->curregs[R5] &= ~clear_bits;
 663         write_zsreg(channel, R5, up->curregs[R5]);
 664 }
 665
 666 /* The port lock is held and interrupts are disabled.  */
 667 static void sunzilog_stop_tx(struct uart_port *port)
 668 {
 669         struct uart_sunzilog_port *up =
 670                 container_of(port, struct uart_sunzilog_port, port);
 671
 672         up->flags |= SUNZILOG_FLAG_TX_STOPPED;
 673 }
 674
 675 /* The port lock is held and interrupts are disabled.  */
 676 static void sunzilog_start_tx(struct uart_port *port)
 677 {
 678         struct uart_sunzilog_port *up =
 679                 container_of(port, struct uart_sunzilog_port, port);
 680         struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
 681         unsigned char status;
 682
 683         up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
 684         up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
 685
 686         status = readb(&channel->control);
 687         ZSDELAY();
 688
 689         /* TX busy?  Just wait for the TX done interrupt.  */
 690         if (!(status & Tx_BUF_EMP))
 691                 return;
 692
 693         /* Send the first character to jump-start the TX done
 694          * IRQ sending engine.
 695          */
 696         if (port->x_char) {
 697                 writeb(port->x_char, &channel->data);
 698                 ZSDELAY();
 699                 ZS_WSYNC(channel);
 700
 701                 port->icount.tx++;
 702                 port->x_char = 0;
 703         } else {
 704                 struct circ_buf *xmit = &port->state->xmit;
 705
 706                 if (uart_circ_empty(xmit))
 707                         return;
 708                 writeb(xmit->buf[xmit->tail], &channel->data);
 709                 ZSDELAY();
 710                 ZS_WSYNC(channel);
 711
 712                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 713                 port->icount.tx++;
 714
 715                 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 716                         uart_write_wakeup(&up->port);
 717         }
 718 }
 719
 720 /* The port lock is held.  */
 721 static void sunzilog_stop_rx(struct uart_port *port)
 722 {
 723         struct uart_sunzilog_port *up = UART_ZILOG(port);
 724         struct zilog_channel __iomem *channel;
 725
 726         if (ZS_IS_CONS(up))
 727                 return;
 728
 729         channel = ZILOG_CHANNEL_FROM_PORT(port);
 730
 731         /* Disable all RX interrupts.  */
 732         up->curregs[R1] &= ~RxINT_MASK;
 733         sunzilog_maybe_update_regs(up, channel);
 734 }
 735
 736 /* The port lock is held.  */
 737 static void sunzilog_enable_ms(struct uart_port *port)
 738 {
 739         struct uart_sunzilog_port *up =
 740                 container_of(port, struct uart_sunzilog_port, port);
 741         struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
 742         unsigned char new_reg;
 743
 744         new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
 745         if (new_reg != up->curregs[R15]) {
 746                 up->curregs[R15] = new_reg;
 747
 748                 /* NOTE: Not subject to 'transmitter active' rule.  */
 749                 write_zsreg(channel, R15, up->curregs[R15] & ~WR7pEN);
 750         }
 751 }
 752
 753 /* The port lock is not held.  */
 754 static void sunzilog_break_ctl(struct uart_port *port, int break_state)
 755 {
 756         struct uart_sunzilog_port *up =
 757                 container_of(port, struct uart_sunzilog_port, port);
 758         struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
 759         unsigned char set_bits, clear_bits, new_reg;
 760         unsigned long flags;
 761
 762         set_bits = clear_bits = 0;
 763
 764         if (break_state)
 765                 set_bits |= SND_BRK;
 766         else
 767                 clear_bits |= SND_BRK;
 768
 769         spin_lock_irqsave(&port->lock, flags);
 770
 771         new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
 772         if (new_reg != up->curregs[R5]) {
 773                 up->curregs[R5] = new_reg;
 774
 775                 /* NOTE: Not subject to 'transmitter active' rule.  */
 776                 write_zsreg(channel, R5, up->curregs[R5]);
 777         }
 778
 779         spin_unlock_irqrestore(&port->lock, flags);
 780 }
 781
 782 static void __sunzilog_startup(struct uart_sunzilog_port *up)
 783 {
 784         struct zilog_channel __iomem *channel;
 785
 786         channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
 787         up->prev_status = readb(&channel->control);
 788
 789         /* Enable receiver and transmitter.  */
 790         up->curregs[R3] |= RxENAB;
 791         up->curregs[R5] |= TxENAB;
 792
 793         up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
 794         sunzilog_maybe_update_regs(up, channel);
 795 }
 796
 797 static int sunzilog_startup(struct uart_port *port)
 798 {
 799         struct uart_sunzilog_port *up = UART_ZILOG(port);
 800         unsigned long flags;
 801
 802         if (ZS_IS_CONS(up))
 803                 return 0;
 804
 805         spin_lock_irqsave(&port->lock, flags);
 806         __sunzilog_startup(up);
 807         spin_unlock_irqrestore(&port->lock, flags);
 808         return 0;
 809 }
 810
 811 /*
 812  * The test for ZS_IS_CONS is explained by the following e-mail:
 813  *****
 814  * From: Russell King <rmk@arm.linux.org.uk>
 815  * Date: Sun, 8 Dec 2002 10:18:38 +0000
 816  *
 817  * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
 818  * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
 819  * > and I noticed that something is not right with reference
 820  * > counting in this case. It seems that when the console
 821  * > is open by kernel initially, this is not accounted
 822  * > as an open, and uart_startup is not called.
 823  *
 824  * That is correct.  We are unable to call uart_startup when the serial
 825  * console is initialised because it may need to allocate memory (as
 826  * request_irq does) and the memory allocators may not have been
 827  * initialised.
 828  *
 829  * 1. initialise the port into a state where it can send characters in the
 830  *    console write method.
 831  *
 832  * 2. don't do the actual hardware shutdown in your shutdown() method (but
 833  *    do the normal software shutdown - ie, free irqs etc)
 834  *****
 835  */
 836 static void sunzilog_shutdown(struct uart_port *port)
 837 {
 838         struct uart_sunzilog_port *up = UART_ZILOG(port);
 839         struct zilog_channel __iomem *channel;
 840         unsigned long flags;
 841
 842         if (ZS_IS_CONS(up))
 843                 return;
 844
 845         spin_lock_irqsave(&port->lock, flags);
 846
 847         channel = ZILOG_CHANNEL_FROM_PORT(port);
 848
 849         /* Disable receiver and transmitter.  */
 850         up->curregs[R3] &= ~RxENAB;
 851         up->curregs[R5] &= ~TxENAB;
 852
 853         /* Disable all interrupts and BRK assertion.  */
 854         up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
 855         up->curregs[R5] &= ~SND_BRK;
 856         sunzilog_maybe_update_regs(up, channel);
 857
 858         spin_unlock_irqrestore(&port->lock, flags);
 859 }
 860
 861 /* Shared by TTY driver and serial console setup.  The port lock is held
 862  * and local interrupts are disabled.
 863  */
 864 static void
 865 sunzilog_convert_to_zs(struct uart_sunzilog_port *up, unsigned int cflag,
 866                        unsigned int iflag, int brg)
 867 {
 868
 869         up->curregs[R10] = NRZ;
 870         up->curregs[R11] = TCBR | RCBR;
 871
 872         /* Program BAUD and clock source. */
 873         up->curregs[R4] &= ~XCLK_MASK;
 874         up->curregs[R4] |= X16CLK;
 875         up->curregs[R12] = brg & 0xff;
 876         up->curregs[R13] = (brg >> 8) & 0xff;
 877         up->curregs[R14] = BRSRC | BRENAB;
 878
 879         /* Character size, stop bits, and parity. */
 880         up->curregs[R3] &= ~RxN_MASK;
 881         up->curregs[R5] &= ~TxN_MASK;
 882         switch (cflag & CSIZE) {
 883         case CS5:
 884                 up->curregs[R3] |= Rx5;
 885                 up->curregs[R5] |= Tx5;
 886                 up->parity_mask = 0x1f;
 887                 break;
 888         case CS6:
 889                 up->curregs[R3] |= Rx6;
 890                 up->curregs[R5] |= Tx6;
 891                 up->parity_mask = 0x3f;
 892                 break;
 893         case CS7:
 894                 up->curregs[R3] |= Rx7;
 895                 up->curregs[R5] |= Tx7;
 896                 up->parity_mask = 0x7f;
 897                 break;
 898         case CS8:
 899         default:
 900                 up->curregs[R3] |= Rx8;
 901                 up->curregs[R5] |= Tx8;
 902                 up->parity_mask = 0xff;
 903                 break;
 904         }
 905         up->curregs[R4] &= ~0x0c;
 906         if (cflag & CSTOPB)
 907                 up->curregs[R4] |= SB2;
 908         else
 909                 up->curregs[R4] |= SB1;
 910         if (cflag & PARENB)
 911                 up->curregs[R4] |= PAR_ENAB;
 912         else
 913                 up->curregs[R4] &= ~PAR_ENAB;
 914         if (!(cflag & PARODD))
 915                 up->curregs[R4] |= PAR_EVEN;
 916         else
 917                 up->curregs[R4] &= ~PAR_EVEN;
 918
 919         up->port.read_status_mask = Rx_OVR;
 920         if (iflag & INPCK)
 921                 up->port.read_status_mask |= CRC_ERR | PAR_ERR;
 922         if (iflag & (IGNBRK | BRKINT | PARMRK))
 923                 up->port.read_status_mask |= BRK_ABRT;
 924
 925         up->port.ignore_status_mask = 0;
 926         if (iflag & IGNPAR)
 927                 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
 928         if (iflag & IGNBRK) {
 929                 up->port.ignore_status_mask |= BRK_ABRT;
 930                 if (iflag & IGNPAR)
 931                         up->port.ignore_status_mask |= Rx_OVR;
 932         }
 933
 934         if ((cflag & CREAD) == 0)
 935                 up->port.ignore_status_mask = 0xff;
 936 }
 937
 938 /* The port lock is not held.  */
 939 static void
 940 sunzilog_set_termios(struct uart_port *port, struct ktermios *termios,
 941                      struct ktermios *old)
 942 {
 943         struct uart_sunzilog_port *up =
 944                 container_of(port, struct uart_sunzilog_port, port);
 945         unsigned long flags;
 946         int baud, brg;
 947
 948         baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
 949
 950         spin_lock_irqsave(&up->port.lock, flags);
 951
 952         brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
 953
 954         sunzilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
 955
 956         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 957                 up->flags |= SUNZILOG_FLAG_MODEM_STATUS;
 958         else
 959                 up->flags &= ~SUNZILOG_FLAG_MODEM_STATUS;
 960
 961         up->cflag = termios->c_cflag;
 962
 963         sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
 964
 965         uart_update_timeout(port, termios->c_cflag, baud);
 966
 967         spin_unlock_irqrestore(&up->port.lock, flags);
 968 }
 969
 970 static const char *sunzilog_type(struct uart_port *port)
 971 {
 972         struct uart_sunzilog_port *up = UART_ZILOG(port);
 973
 974         return (up->flags & SUNZILOG_FLAG_ESCC) ? "zs (ESCC)" : "zs";
 975 }
 976
 977 /* We do not request/release mappings of the registers here, this
 978  * happens at early serial probe time.
 979  */
 980 static void sunzilog_release_port(struct uart_port *port)
 981 {
 982 }
 983
 984 static int sunzilog_request_port(struct uart_port *port)
 985 {
 986         return 0;
 987 }
 988
 989 /* These do not need to do anything interesting either.  */
 990 static void sunzilog_config_port(struct uart_port *port, int flags)
 991 {
 992 }
 993
 994 /* We do not support letting the user mess with the divisor, IRQ, etc. */
 995 static int sunzilog_verify_port(struct uart_port *port, struct serial_struct *ser)
 996 {
 997         return -EINVAL;
 998 }
 999
1000 #ifdef CONFIG_CONSOLE_POLL
1001 static int sunzilog_get_poll_char(struct uart_port *port)
1002 {
1003         unsigned char ch, r1;
1004         struct uart_sunzilog_port *up =
1005                 container_of(port, struct uart_sunzilog_port, port);
1006         struct zilog_channel __iomem *channel
1007                 = ZILOG_CHANNEL_FROM_PORT(&up->port);
1008
1009
1010         r1 = read_zsreg(channel, R1);
1011         if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
1012                 writeb(ERR_RES, &channel->control);
1013                 ZSDELAY();
1014                 ZS_WSYNC(channel);
1015         }
1016
1017         ch = readb(&channel->control);
1018         ZSDELAY();
1019
1020         /* This funny hack depends upon BRK_ABRT not interfering
1021          * with the other bits we care about in R1.
1022          */
1023         if (ch & BRK_ABRT)
1024                 r1 |= BRK_ABRT;
1025
1026         if (!(ch & Rx_CH_AV))
1027                 return NO_POLL_CHAR;
1028
1029         ch = readb(&channel->data);
1030         ZSDELAY();
1031
1032         ch &= up->parity_mask;
1033         return ch;
1034 }
1035
1036 static void sunzilog_put_poll_char(struct uart_port *port,
1037                         unsigned char ch)
1038 {
1039         struct uart_sunzilog_port *up =
1040                 container_of(port, struct uart_sunzilog_port, port);
1041
1042         sunzilog_putchar(&up->port, ch);
1043 }
1044 #endif /* CONFIG_CONSOLE_POLL */
1045
1046 static const struct uart_ops sunzilog_pops = {
1047         .tx_empty       =       sunzilog_tx_empty,
1048         .set_mctrl      =       sunzilog_set_mctrl,
1049         .get_mctrl      =       sunzilog_get_mctrl,
1050         .stop_tx        =       sunzilog_stop_tx,
1051         .start_tx       =       sunzilog_start_tx,
1052         .stop_rx        =       sunzilog_stop_rx,
1053         .enable_ms      =       sunzilog_enable_ms,
1054         .break_ctl      =       sunzilog_break_ctl,
1055         .startup        =       sunzilog_startup,
1056         .shutdown       =       sunzilog_shutdown,
1057         .set_termios    =       sunzilog_set_termios,
1058         .type           =       sunzilog_type,
1059         .release_port   =       sunzilog_release_port,
1060         .request_port   =       sunzilog_request_port,
1061         .config_port    =       sunzilog_config_port,
1062         .verify_port    =       sunzilog_verify_port,
1063 #ifdef CONFIG_CONSOLE_POLL
1064         .poll_get_char  =       sunzilog_get_poll_char,
1065         .poll_put_char  =       sunzilog_put_poll_char,
1066 #endif
1067 };
1068
1069 static int uart_chip_count;
1070 static struct uart_sunzilog_port *sunzilog_port_table;
1071 static struct zilog_layout __iomem **sunzilog_chip_regs;
1072
1073 static struct uart_sunzilog_port *sunzilog_irq_chain;
1074
1075 static struct uart_driver sunzilog_reg = {
1076         .owner          =       THIS_MODULE,
1077         .driver_name    =       "sunzilog",
1078         .dev_name       =       "ttyS",
1079         .major          =       TTY_MAJOR,
1080 };
1081
1082 static int __init sunzilog_alloc_tables(int num_sunzilog)
1083 {
1084         struct uart_sunzilog_port *up;
1085         unsigned long size;
1086         int num_channels = num_sunzilog * 2;
1087         int i;
1088
1089         size = num_channels * sizeof(struct uart_sunzilog_port);
1090         sunzilog_port_table = kzalloc(size, GFP_KERNEL);
1091         if (!sunzilog_port_table)
1092                 return -ENOMEM;
1093
1094         for (i = 0; i < num_channels; i++) {
1095                 up = &sunzilog_port_table[i];
1096
1097                 spin_lock_init(&up->port.lock);
1098
1099                 if (i == 0)
1100                         sunzilog_irq_chain = up;
1101
1102                 if (i < num_channels - 1)
1103                         up->next = up + 1;
1104                 else
1105                         up->next = NULL;
1106         }
1107
1108         size = num_sunzilog * sizeof(struct zilog_layout __iomem *);
1109         sunzilog_chip_regs = kzalloc(size, GFP_KERNEL);
1110         if (!sunzilog_chip_regs) {
1111                 kfree(sunzilog_port_table);
1112                 sunzilog_irq_chain = NULL;
1113                 return -ENOMEM;
1114         }
1115
1116         return 0;
1117 }
1118
1119 static void sunzilog_free_tables(void)
1120 {
1121         kfree(sunzilog_port_table);
1122         sunzilog_irq_chain = NULL;
1123         kfree(sunzilog_chip_regs);
1124 }
1125
1126 #define ZS_PUT_CHAR_MAX_DELAY   2000    /* 10 ms */
1127
1128 static void __maybe_unused sunzilog_putchar(struct uart_port *port, int ch)
1129 {
1130         struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
1131         int loops = ZS_PUT_CHAR_MAX_DELAY;
1132
1133         /* This is a timed polling loop so do not switch the explicit
1134          * udelay with ZSDELAY as that is a NOP on some platforms.  -DaveM
1135          */
1136         do {
1137                 unsigned char val = readb(&channel->control);
1138                 if (val & Tx_BUF_EMP) {
1139                         ZSDELAY();
1140                         break;
1141                 }
1142                 udelay(5);
1143         } while (--loops);
1144
1145         writeb(ch, &channel->data);
1146         ZSDELAY();
1147         ZS_WSYNC(channel);
1148 }
1149
1150 #ifdef CONFIG_SERIO
1151
1152 static DEFINE_SPINLOCK(sunzilog_serio_lock);
1153
1154 static int sunzilog_serio_write(struct serio *serio, unsigned char ch)
1155 {
1156         struct uart_sunzilog_port *up = serio->port_data;
1157         unsigned long flags;
1158
1159         spin_lock_irqsave(&sunzilog_serio_lock, flags);
1160
1161         sunzilog_putchar(&up->port, ch);
1162
1163         spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1164
1165         return 0;
1166 }
1167
1168 static int sunzilog_serio_open(struct serio *serio)
1169 {
1170         struct uart_sunzilog_port *up = serio->port_data;
1171         unsigned long flags;
1172         int ret;
1173
1174         spin_lock_irqsave(&sunzilog_serio_lock, flags);
1175         if (!up->serio_open) {
1176                 up->serio_open = 1;
1177                 ret = 0;
1178         } else
1179                 ret = -EBUSY;
1180         spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1181
1182         return ret;
1183 }
1184
1185 static void sunzilog_serio_close(struct serio *serio)
1186 {
1187         struct uart_sunzilog_port *up = serio->port_data;
1188         unsigned long flags;
1189
1190         spin_lock_irqsave(&sunzilog_serio_lock, flags);
1191         up->serio_open = 0;
1192         spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1193 }
1194
1195 #endif /* CONFIG_SERIO */
1196
1197 #ifdef CONFIG_SERIAL_SUNZILOG_CONSOLE
1198 static void
1199 sunzilog_console_write(struct console *con, const char *s, unsigned int count)
1200 {
1201         struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1202         unsigned long flags;
1203         int locked = 1;
1204
1205         if (up->port.sysrq || oops_in_progress)
1206                 locked = spin_trylock_irqsave(&up->port.lock, flags);
1207         else
1208                 spin_lock_irqsave(&up->port.lock, flags);
1209
1210         uart_console_write(&up->port, s, count, sunzilog_putchar);
1211         udelay(2);
1212
1213         if (locked)
1214                 spin_unlock_irqrestore(&up->port.lock, flags);
1215 }
1216
1217 static int __init sunzilog_console_setup(struct console *con, char *options)
1218 {
1219         struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1220         unsigned long flags;
1221         int baud, brg;
1222
1223         if (up->port.type != PORT_SUNZILOG)
1224                 return -EINVAL;
1225
1226         printk(KERN_INFO "Console: ttyS%d (SunZilog zs%d)\n",
1227                (sunzilog_reg.minor - 64) + con->index, con->index);
1228
1229         /* Get firmware console settings.  */
1230         sunserial_console_termios(con, up->port.dev->of_node);
1231
1232         /* Firmware console speed is limited to 150-->38400 baud so
1233          * this hackish cflag thing is OK.
1234          */
1235         switch (con->cflag & CBAUD) {
1236         case B150: baud = 150; break;
1237         case B300: baud = 300; break;
1238         case B600: baud = 600; break;
1239         case B1200: baud = 1200; break;
1240         case B2400: baud = 2400; break;
1241         case B4800: baud = 4800; break;
1242         default: case B9600: baud = 9600; break;
1243         case B19200: baud = 19200; break;
1244         case B38400: baud = 38400; break;
1245         }
1246
1247         brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1248
1249         spin_lock_irqsave(&up->port.lock, flags);
1250
1251         up->curregs[R15] |= BRKIE;
1252         sunzilog_convert_to_zs(up, con->cflag, 0, brg);
1253
1254         sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1255         __sunzilog_startup(up);
1256
1257         spin_unlock_irqrestore(&up->port.lock, flags);
1258
1259         return 0;
1260 }
1261
1262 static struct console sunzilog_console_ops = {
1263         .name   =       "ttyS",
1264         .write  =       sunzilog_console_write,
1265         .device =       uart_console_device,
1266         .setup  =       sunzilog_console_setup,
1267         .flags  =       CON_PRINTBUFFER,
1268         .index  =       -1,
1269         .data   =       &sunzilog_reg,
1270 };
1271
1272 static inline struct console *SUNZILOG_CONSOLE(void)
1273 {
1274         return &sunzilog_console_ops;
1275 }
1276
1277 #else
1278 #define SUNZILOG_CONSOLE()      (NULL)
1279 #endif
1280
1281 static void sunzilog_init_kbdms(struct uart_sunzilog_port *up)
1282 {
1283         int baud, brg;
1284
1285         if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1286                 up->cflag = B1200 | CS8 | CLOCAL | CREAD;
1287                 baud = 1200;
1288         } else {
1289                 up->cflag = B4800 | CS8 | CLOCAL | CREAD;
1290                 baud = 4800;
1291         }
1292
1293         up->curregs[R15] |= BRKIE;
1294         brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1295         sunzilog_convert_to_zs(up, up->cflag, 0, brg);
1296         sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1297         __sunzilog_startup(up);
1298 }
1299
1300 #ifdef CONFIG_SERIO
1301 static void sunzilog_register_serio(struct uart_sunzilog_port *up)
1302 {
1303         struct serio *serio = &up->serio;
1304
1305         serio->port_data = up;
1306
1307         serio->id.type = SERIO_RS232;
1308         if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1309                 serio->id.proto = SERIO_SUNKBD;
1310                 strlcpy(serio->name, "zskbd", sizeof(serio->name));
1311         } else {
1312                 serio->id.proto = SERIO_SUN;
1313                 serio->id.extra = 1;
1314                 strlcpy(serio->name, "zsms", sizeof(serio->name));
1315         }
1316         strlcpy(serio->phys,
1317                 ((up->flags & SUNZILOG_FLAG_CONS_KEYB) ?
1318                  "zs/serio0" : "zs/serio1"),
1319                 sizeof(serio->phys));
1320
1321         serio->write = sunzilog_serio_write;
1322         serio->open = sunzilog_serio_open;
1323         serio->close = sunzilog_serio_close;
1324         serio->dev.parent = up->port.dev;
1325
1326         serio_register_port(serio);
1327 }
1328 #endif
1329
1330 static void sunzilog_init_hw(struct uart_sunzilog_port *up)
1331 {
1332         struct zilog_channel __iomem *channel;
1333         unsigned long flags;
1334         int baud, brg;
1335
1336         channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1337
1338         spin_lock_irqsave(&up->port.lock, flags);
1339         if (ZS_IS_CHANNEL_A(up)) {
1340                 write_zsreg(channel, R9, FHWRES);
1341                 ZSDELAY_LONG();
1342                 (void) read_zsreg(channel, R0);
1343         }
1344
1345         if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1346                          SUNZILOG_FLAG_CONS_MOUSE)) {
1347                 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1348                 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1349                 up->curregs[R3] = RxENAB | Rx8;
1350                 up->curregs[R5] = TxENAB | Tx8;
1351                 up->curregs[R6] = 0x00; /* SDLC Address */
1352                 up->curregs[R7] = 0x7E; /* SDLC Flag    */
1353                 up->curregs[R9] = NV;
1354                 up->curregs[R7p] = 0x00;
1355                 sunzilog_init_kbdms(up);
1356                 /* Only enable interrupts if an ISR handler available */
1357                 if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
1358                         up->curregs[R9] |= MIE;
1359                 write_zsreg(channel, R9, up->curregs[R9]);
1360         } else {
1361                 /* Normal serial TTY. */
1362                 up->parity_mask = 0xff;
1363                 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1364                 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1365                 up->curregs[R3] = RxENAB | Rx8;
1366                 up->curregs[R5] = TxENAB | Tx8;
1367                 up->curregs[R6] = 0x00; /* SDLC Address */
1368                 up->curregs[R7] = 0x7E; /* SDLC Flag    */
1369                 up->curregs[R9] = NV;
1370                 up->curregs[R10] = NRZ;
1371                 up->curregs[R11] = TCBR | RCBR;
1372                 baud = 9600;
1373                 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1374                 up->curregs[R12] = (brg & 0xff);
1375                 up->curregs[R13] = (brg >> 8) & 0xff;
1376                 up->curregs[R14] = BRSRC | BRENAB;
1377                 up->curregs[R15] = FIFOEN; /* Use FIFO if on ESCC */
1378                 up->curregs[R7p] = TxFIFO_LVL | RxFIFO_LVL;
1379                 if (__load_zsregs(channel, up->curregs)) {
1380                         up->flags |= SUNZILOG_FLAG_ESCC;
1381                 }
1382                 /* Only enable interrupts if an ISR handler available */
1383                 if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
1384                         up->curregs[R9] |= MIE;
1385                 write_zsreg(channel, R9, up->curregs[R9]);
1386         }
1387
1388         spin_unlock_irqrestore(&up->port.lock, flags);
1389
1390 #ifdef CONFIG_SERIO
1391         if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1392                          SUNZILOG_FLAG_CONS_MOUSE))
1393                 sunzilog_register_serio(up);
1394 #endif
1395 }
1396
1397 static int zilog_irq;
1398
1399 static int zs_probe(struct platform_device *op)
1400 {
1401         static int kbm_inst, uart_inst;
1402         int inst;
1403         struct uart_sunzilog_port *up;
1404         struct zilog_layout __iomem *rp;
1405         int keyboard_mouse = 0;
1406         int err;
1407
1408         if (of_find_property(op->dev.of_node, "keyboard", NULL))
1409                 keyboard_mouse = 1;
1410
1411         /* uarts must come before keyboards/mice */
1412         if (keyboard_mouse)
1413                 inst = uart_chip_count + kbm_inst;
1414         else
1415                 inst = uart_inst;
1416
1417         sunzilog_chip_regs[inst] = of_ioremap(&op->resource[0], 0,
1418                                               sizeof(struct zilog_layout),
1419                                               "zs");
1420         if (!sunzilog_chip_regs[inst])
1421                 return -ENOMEM;
1422
1423         rp = sunzilog_chip_regs[inst];
1424
1425         if (!zilog_irq)
1426                 zilog_irq = op->archdata.irqs[0];
1427
1428         up = &sunzilog_port_table[inst * 2];
1429
1430         /* Channel A */
1431         up[0].port.mapbase = op->resource[0].start + 0x00;
1432         up[0].port.membase = (void __iomem *) &rp->channelA;
1433         up[0].port.iotype = UPIO_MEM;
1434         up[0].port.irq = op->archdata.irqs[0];
1435         up[0].port.uartclk = ZS_CLOCK;
1436         up[0].port.fifosize = 1;
1437         up[0].port.ops = &sunzilog_pops;
1438         up[0].port.type = PORT_SUNZILOG;
1439         up[0].port.flags = 0;
1440         up[0].port.line = (inst * 2) + 0;
1441         up[0].port.dev = &op->dev;
1442         up[0].flags |= SUNZILOG_FLAG_IS_CHANNEL_A;
1443         up[0].port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SUNZILOG_CONSOLE);
1444         if (keyboard_mouse)
1445                 up[0].flags |= SUNZILOG_FLAG_CONS_KEYB;
1446         sunzilog_init_hw(&up[0]);
1447
1448         /* Channel B */
1449         up[1].port.mapbase = op->resource[0].start + 0x04;
1450         up[1].port.membase = (void __iomem *) &rp->channelB;
1451         up[1].port.iotype = UPIO_MEM;
1452         up[1].port.irq = op->archdata.irqs[0];
1453         up[1].port.uartclk = ZS_CLOCK;
1454         up[1].port.fifosize = 1;
1455         up[1].port.ops = &sunzilog_pops;
1456         up[1].port.type = PORT_SUNZILOG;
1457         up[1].port.flags = 0;
1458         up[1].port.line = (inst * 2) + 1;
1459         up[1].port.dev = &op->dev;
1460         up[1].flags |= 0;
1461         up[1].port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SUNZILOG_CONSOLE);
1462         if (keyboard_mouse)
1463                 up[1].flags |= SUNZILOG_FLAG_CONS_MOUSE;
1464         sunzilog_init_hw(&up[1]);
1465
1466         if (!keyboard_mouse) {
1467                 if (sunserial_console_match(SUNZILOG_CONSOLE(), op->dev.of_node,
1468                                             &sunzilog_reg, up[0].port.line,
1469                                             false))
1470                         up->flags |= SUNZILOG_FLAG_IS_CONS;
1471                 err = uart_add_one_port(&sunzilog_reg, &up[0].port);
1472                 if (err) {
1473                         of_iounmap(&op->resource[0],
1474                                    rp, sizeof(struct zilog_layout));
1475                         return err;
1476                 }
1477                 if (sunserial_console_match(SUNZILOG_CONSOLE(), op->dev.of_node,
1478                                             &sunzilog_reg, up[1].port.line,
1479                                             false))
1480                         up->flags |= SUNZILOG_FLAG_IS_CONS;
1481                 err = uart_add_one_port(&sunzilog_reg, &up[1].port);
1482                 if (err) {
1483                         uart_remove_one_port(&sunzilog_reg, &up[0].port);
1484                         of_iounmap(&op->resource[0],
1485                                    rp, sizeof(struct zilog_layout));
1486                         return err;
1487                 }
1488                 uart_inst++;
1489         } else {
1490                 printk(KERN_INFO "%s: Keyboard at MMIO 0x%llx (irq = %d) "
1491                        "is a %s\n",
1492                        dev_name(&op->dev),
1493                        (unsigned long long) up[0].port.mapbase,
1494                        op->archdata.irqs[0], sunzilog_type(&up[0].port));
1495                 printk(KERN_INFO "%s: Mouse at MMIO 0x%llx (irq = %d) "
1496                        "is a %s\n",
1497                        dev_name(&op->dev),
1498                        (unsigned long long) up[1].port.mapbase,
1499                        op->archdata.irqs[0], sunzilog_type(&up[1].port));
1500                 kbm_inst++;
1501         }
1502
1503         platform_set_drvdata(op, &up[0]);
1504
1505         return 0;
1506 }
1507
1508 static void zs_remove_one(struct uart_sunzilog_port *up)
1509 {
1510         if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up)) {
1511 #ifdef CONFIG_SERIO
1512                 serio_unregister_port(&up->serio);
1513 #endif
1514         } else
1515                 uart_remove_one_port(&sunzilog_reg, &up->port);
1516 }
1517
1518 static int zs_remove(struct platform_device *op)
1519 {
1520         struct uart_sunzilog_port *up = platform_get_drvdata(op);
1521         struct zilog_layout __iomem *regs;
1522
1523         zs_remove_one(&up[0]);
1524         zs_remove_one(&up[1]);
1525
1526         regs = sunzilog_chip_regs[up[0].port.line / 2];
1527         of_iounmap(&op->resource[0], regs, sizeof(struct zilog_layout));
1528
1529         return 0;
1530 }
1531
1532 static const struct of_device_id zs_match[] = {
1533         {
1534                 .name = "zs",
1535         },
1536         {},
1537 };
1538 MODULE_DEVICE_TABLE(of, zs_match);
1539
1540 static struct platform_driver zs_driver = {
1541         .driver = {
1542                 .name = "zs",
1543                 .of_match_table = zs_match,
1544         },
1545         .probe          = zs_probe,
1546         .remove         = zs_remove,
1547 };
1548
1549 static int __init sunzilog_init(void)
1550 {
1551         struct device_node *dp;
1552         int err;
1553         int num_keybms = 0;
1554         int num_sunzilog = 0;
1555
1556         for_each_node_by_name(dp, "zs") {
1557                 num_sunzilog++;
1558                 if (of_find_property(dp, "keyboard", NULL))
1559                         num_keybms++;
1560         }
1561
1562         if (num_sunzilog) {
1563                 err = sunzilog_alloc_tables(num_sunzilog);
1564                 if (err)
1565                         goto out;
1566
1567                 uart_chip_count = num_sunzilog - num_keybms;
1568
1569                 err = sunserial_register_minors(&sunzilog_reg,
1570                                                 uart_chip_count * 2);
1571                 if (err)
1572                         goto out_free_tables;
1573         }
1574
1575         err = platform_driver_register(&zs_driver);
1576         if (err)
1577                 goto out_unregister_uart;
1578
1579         if (zilog_irq) {
1580                 struct uart_sunzilog_port *up = sunzilog_irq_chain;
1581                 err = request_irq(zilog_irq, sunzilog_interrupt, IRQF_SHARED,
1582                                   "zs", sunzilog_irq_chain);
1583                 if (err)
1584                         goto out_unregister_driver;
1585
1586                 /* Enable Interrupts */
1587                 while (up) {
1588                         struct zilog_channel __iomem *channel;
1589
1590                         /* printk (KERN_INFO "Enable IRQ for ZILOG Hardware %p\n", up); */
1591                         channel          = ZILOG_CHANNEL_FROM_PORT(&up->port);
1592                         up->flags       |= SUNZILOG_FLAG_ISR_HANDLER;
1593                         up->curregs[R9] |= MIE;
1594                         write_zsreg(channel, R9, up->curregs[R9]);
1595                         up = up->next;
1596                 }
1597         }
1598
1599 out:
1600         return err;
1601
1602 out_unregister_driver:
1603         platform_driver_unregister(&zs_driver);
1604
1605 out_unregister_uart:
1606         if (num_sunzilog) {
1607                 sunserial_unregister_minors(&sunzilog_reg, num_sunzilog);
1608                 sunzilog_reg.cons = NULL;
1609         }
1610
1611 out_free_tables:
1612         sunzilog_free_tables();
1613         goto out;
1614 }
1615
1616 static void __exit sunzilog_exit(void)
1617 {
1618         platform_driver_unregister(&zs_driver);
1619
1620         if (zilog_irq) {
1621                 struct uart_sunzilog_port *up = sunzilog_irq_chain;
1622
1623                 /* Disable Interrupts */
1624                 while (up) {
1625                         struct zilog_channel __iomem *channel;
1626
1627                         /* printk (KERN_INFO "Disable IRQ for ZILOG Hardware %p\n", up); */
1628                         channel          = ZILOG_CHANNEL_FROM_PORT(&up->port);
1629                         up->flags       &= ~SUNZILOG_FLAG_ISR_HANDLER;
1630                         up->curregs[R9] &= ~MIE;
1631                         write_zsreg(channel, R9, up->curregs[R9]);
1632                         up = up->next;
1633                 }
1634
1635                 free_irq(zilog_irq, sunzilog_irq_chain);
1636                 zilog_irq = 0;
1637         }
1638
1639         if (sunzilog_reg.nr) {
1640                 sunserial_unregister_minors(&sunzilog_reg, sunzilog_reg.nr);
1641                 sunzilog_free_tables();
1642         }
1643 }
1644
1645 module_init(sunzilog_init);
1646 module_exit(sunzilog_exit);
1647
1648 MODULE_AUTHOR("David S. Miller");
1649 MODULE_DESCRIPTION("Sun Zilog serial port driver");
1650 MODULE_VERSION("2.0");
1651 MODULE_LICENSE("GPL");